2013-01-26 16:33:56 +00:00
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enum {
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IRQtimer0 = 0,
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IRQtimer1 = 1,
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IRQtimer2 = 2,
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IRQtimer3 = 3,
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IRQclock = IRQtimer3,
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IRQusb = 9,
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IRQdma0 = 16,
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#define IRQDMA(chan) (IRQdma0+(chan))
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IRQaux = 29,
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2018-10-20 17:56:31 +00:00
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IRQi2c = 53,
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IRQspi = 54,
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IRQsdhost = 56,
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2019-04-11 11:21:06 +00:00
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IRQuart = 57,
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2013-01-26 16:33:56 +00:00
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IRQmmc = 62,
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IRQbasic = 64,
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IRQtimerArm = IRQbasic + 0,
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2018-10-20 17:56:31 +00:00
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IRQlocal = 96,
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IRQcntps = IRQlocal + 0,
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IRQcntpns = IRQlocal + 1,
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IRQmbox0 = IRQlocal + 4,
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IRQmbox1 = IRQlocal + 5,
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IRQmbox2 = IRQlocal + 6,
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IRQmbox3 = IRQlocal + 7,
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IRQlocaltmr = IRQlocal + 11,
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2013-01-26 16:33:56 +00:00
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IRQfiq = IRQusb, /* only one source can be FIQ */
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DmaD2M = 0, /* device to memory */
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DmaM2D = 1, /* memory to device */
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DmaM2M = 2, /* memory to memory */
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DmaChanEmmc = 4, /* can only use 2-5, maybe 0 */
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2018-10-20 17:56:31 +00:00
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DmaChanSdhost = 5,
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DmaChanSpiTx= 2,
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DmaChanSpiRx= 0,
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DmaDevSpiTx = 6,
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DmaDevSpiRx = 7,
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2013-01-26 16:33:56 +00:00
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DmaDevEmmc = 11,
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2018-10-20 17:56:31 +00:00
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DmaDevSdhost = 13,
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2013-01-26 16:33:56 +00:00
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PowerSd = 0,
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PowerUart0,
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PowerUart1,
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PowerUsb,
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PowerI2c0,
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PowerI2c1,
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PowerI2c2,
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PowerSpi,
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PowerCcp2tx,
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ClkEmmc = 1,
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ClkUart,
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ClkArm,
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ClkCore,
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ClkV3d,
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ClkH264,
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ClkIsp,
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ClkSdram,
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ClkPixel,
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ClkPwm,
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};
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