2022-06-13 23:00:06 +00:00
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#include "u.h"
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#include "../port/lib.h"
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#include "../port/error.h"
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#include "mem.h"
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#include "dat.h"
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#include "fns.h"
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#include "io.h"
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/* gpio registers */
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enum {
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GPIO_DR = 0x00/4,
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GPIO_GDIR = 0x04/4,
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GPIO_PSR = 0x08/4,
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GPIO_ICR1 = 0x0C/4,
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GPIO_ICR2 = 0x10/4,
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GPIO_IMR = 0x14/4,
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GPIO_ISR = 0x18/4,
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GPIO_EDGE_SEL = 0x1C/4,
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};
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typedef struct Ctlr Ctlr;
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struct Ctlr
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{
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u32int *reg;
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char *clk;
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u32int dir;
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int enabled;
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};
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static Ctlr ctlrs[5] = {
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{(u32int*)(VIRTIO + 0x200000), "gpio1.ipg_clk_s" },
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{(u32int*)(VIRTIO + 0x210000), "gpio2.ipg_clk_s" },
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{(u32int*)(VIRTIO + 0x220000), "gpio3.ipg_clk_s" },
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{(u32int*)(VIRTIO + 0x230000), "gpio4.ipg_clk_s" },
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{(u32int*)(VIRTIO + 0x240000), "gpio5.ipg_clk_s" },
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};
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static Ctlr*
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enable(uint pin)
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{
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2022-06-13 23:24:14 +00:00
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Ctlr *ctlr;
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2022-06-13 23:00:06 +00:00
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2022-06-13 23:24:14 +00:00
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pin /= 32;
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if(pin < 1 || pin > nelem(ctlrs))
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return nil;
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2022-06-13 23:00:06 +00:00
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2022-06-13 23:24:14 +00:00
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ctlr = &ctlrs[pin-1];
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2022-06-13 23:00:06 +00:00
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if(!ctlr->enabled){
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setclkgate(ctlr->clk, 1);
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ctlr->reg[GPIO_IMR] = 0;
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ctlr->dir = ctlr->reg[GPIO_GDIR];
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ctlr->enabled = 1;
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}
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return ctlr;
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}
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void
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gpioout(uint pin, int set)
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{
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2022-06-13 23:26:14 +00:00
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u32int bit = 1 << (pin % 32);
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2022-06-13 23:00:06 +00:00
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Ctlr *ctlr = enable(pin);
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2022-06-13 23:24:14 +00:00
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if(ctlr == nil)
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return;
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2022-06-13 23:00:06 +00:00
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if((ctlr->dir & bit) == 0)
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ctlr->reg[GPIO_GDIR] = ctlr->dir |= bit;
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if(set)
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ctlr->reg[GPIO_DR] |= bit;
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else
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ctlr->reg[GPIO_DR] &= ~bit;
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}
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int
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gpioin(uint pin)
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{
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2022-06-13 23:26:14 +00:00
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u32int bit = 1 << (pin % 32);
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2022-06-13 23:00:06 +00:00
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Ctlr *ctlr = enable(pin);
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2022-06-13 23:24:14 +00:00
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if(ctlr == nil)
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return -1;
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2022-06-13 23:00:06 +00:00
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if(ctlr->dir & bit)
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ctlr->reg[GPIO_GDIR] = ctlr->dir &= ~bit;
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return (ctlr->reg[GPIO_DR] & bit) != 0;
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}
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