2011-03-30 12:46:40 +00:00
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#include "u.h"
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#include "../port/lib.h"
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#include "mem.h"
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#include "dat.h"
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#include "fns.h"
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#include "io.h"
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/*
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* SMBus support for the PIIX4
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*/
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enum
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{
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IntelVendID= 0x8086,
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Piix4PMID= 0x7113, /* PIIX4 power management function */
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/* SMBus configuration registers (function 3) */
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SMBbase= 0x90, /* 4 byte base address (bit 0 == 1, bit 3:1 == 0) */
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SMBconfig= 0xd2,
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SMBintrselect= (7<<1),
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SMIenable= (0<<1), /* interrupts sent to SMI# */
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IRQ9enable= (4<<1), /* interrupts sent to IRQ9 */
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SMBenable= (1<<0), /* 1 enables */
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/* SMBus IO space registers */
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Hoststatus= 0x0, /* (writing 1 bits reset the interrupt bits) */
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Failed= (1<<4), /* transaction terminated by KILL */
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Bus_error= (1<<3), /* transaction collision */
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Dev_error= (1<<2), /* device error interrupt */
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Host_complete= (1<<1), /* host command completion interrupt */
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Host_busy= (1<<0), /* */
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Slavestatus= 0x1, /* (writing 1 bits reset) */
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Alert_sts= (1<<5), /* someone asserted SMBALERT# */
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Shdw2_sts= (1<<4), /* slave accessed shadow 2 port */
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Shdw1_sts= (1<<3), /* slave accessed shadow 1 port */
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Slv_sts= (1<<2), /* slave accessed shadow 1 port */
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Slv_bsy= (1<<0),
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Hostcontrol= 0x2,
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Start= (1<<6), /* start execution */
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Cmd_prot= (7<<2), /* command protocol mask */
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Quick= (0<<2), /* address only */
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Byte= (1<<2), /* address + cmd */
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ByteData= (2<<2), /* address + cmd + data */
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WordData= (3<<2), /* address + cmd + data + data */
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Kill= (1<<1), /* abort in progress command */
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Ienable= (1<<0), /* enable completion interrupts */
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Hostcommand= 0x3,
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Hostaddress= 0x4,
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AddressMask= (0x7f<<1), /* target address */
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Read= (1<<0), /* 1 == read, 0 == write */
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Hostdata0= 0x5,
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Hostdata1= 0x6,
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Blockdata= 0x7,
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Slavecontrol= 0x8,
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Alert_en= (1<<3), /* enable inter on SMBALERT# */
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Shdw2_en= (1<<2), /* enable inter on external shadow 2 access */
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Shdw1_en= (1<<1), /* enable inter on external shadow 1 access */
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Slv_en= (1<<0), /* enable inter on access of host ctlr slave port */
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Shadowcommand= 0x9,
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Slaveevent= 0xa,
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Slavedata= 0xc,
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};
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static struct
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{
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int rw;
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int cmd;
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int len;
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int proto;
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} proto[] =
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{
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[SMBquick] { 0, 0, 0, Quick },
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[SMBsend] { 0, 1, 0, Byte },
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[SMBbytewrite] { 0, 1, 1, ByteData },
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[SMBwordwrite] { 0, 1, 2, WordData },
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[SMBrecv] { Read, 0, 1, Byte },
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[SMBbyteread] { Read, 1, 1, ByteData },
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[SMBwordread] { Read, 1, 2, WordData },
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};
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static void
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transact(SMBus *s, int type, int addr, int cmd, uchar *data)
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{
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int tries, status;
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char err[256];
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if(type < 0 || type > nelem(proto))
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panic("piix4smbus: illegal transaction type %d", type);
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if(waserror()){
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qunlock(s);
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nexterror();
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}
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qlock(s);
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/* wait a while for the host interface to be available */
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for(tries = 0; tries < 1000000; tries++){
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if((inb(s->base+Hoststatus) & Host_busy) == 0)
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break;
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sched();
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}
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if(tries >= 1000000){
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/* try aborting current transaction */
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outb(s->base+Hostcontrol, Kill);
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for(tries = 0; tries < 1000000; tries++){
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if((inb(s->base+Hoststatus) & Host_busy) == 0)
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break;
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sched();
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}
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if(tries >= 1000000){
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snprint(err, sizeof(err), "SMBus jammed: %2.2ux", inb(s->base+Hoststatus));
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error(err);
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}
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}
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/* set up for transaction */
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outb(s->base+Hostaddress, (addr<<1)|proto[type].rw);
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if(proto[type].cmd)
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outb(s->base+Hostcommand, cmd);
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if(proto[type].rw != Read){
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switch(proto[type].len){
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case 2:
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outb(s->base+Hostdata1, data[1]);
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/* fall through */
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case 1:
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outb(s->base+Hostdata0, data[0]);
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break;
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}
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}
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/* reset the completion/error bits and start transaction */
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outb(s->base+Hoststatus, Failed|Bus_error|Dev_error|Host_complete);
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outb(s->base+Hostcontrol, Start|proto[type].proto);
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/* wait for completion */
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status = 0;
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for(tries = 0; tries < 1000000; tries++){
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status = inb(s->base+Hoststatus);
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if(status & (Failed|Bus_error|Dev_error|Host_complete))
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break;
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sched();
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}
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if((status & Host_complete) == 0){
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snprint(err, sizeof(err), "SMBus request failed: %2.2ux", status);
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error(err);
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}
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/* get results */
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if(proto[type].rw == Read){
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switch(proto[type].len){
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case 2:
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data[1] = inb(s->base+Hostdata1);
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/* fall through */
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case 1:
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data[0] = inb(s->base+Hostdata0);
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break;
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}
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}
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qunlock(s);
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poperror();
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}
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static SMBus smbusproto =
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{
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.transact = transact,
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};
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/*
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* return 0 if this is a piix4 with an smbus interface
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*/
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SMBus*
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piix4smbus(void)
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{
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Pcidev *p;
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static SMBus *s;
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if(s != nil)
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return s;
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p = pcimatch(nil, IntelVendID, Piix4PMID);
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if(p == nil)
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return nil;
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2011-12-12 15:55:26 +00:00
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s = malloc(sizeof(*s));
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if(s == nil)
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panic("piix4smbus: no memory for SMBus");
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2011-03-30 12:46:40 +00:00
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memmove(s, &smbusproto, sizeof(*s));
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s->arg = p;
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/* disable the smbus */
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pcicfgw8(p, SMBconfig, IRQ9enable|0);
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/* see if bios gave us a viable port space */
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s->base = pcicfgr32(p, SMBbase) & ~1;
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print("SMB base from bios is 0x%lux\n", s->base);
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if(ioalloc(s->base, 0xd, 0, "piix4smbus") < 0){
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s->base = ioalloc(-1, 0xd, 2, "piix4smbus");
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if(s->base < 0){
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free(s);
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print("piix4smbus: can't allocate io port\n");
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return nil;
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}
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print("SMB base ialloc is 0x%lux\n", s->base);
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pcicfgw32(p, SMBbase, s->base|1);
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}
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/* disable SMBus interrupts, abort any transaction in progress */
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outb(s->base+Hostcontrol, Kill);
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outb(s->base+Slavecontrol, 0);
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/* enable the smbus */
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pcicfgw8(p, SMBconfig, IRQ9enable|SMBenable);
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return s;
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}
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