489 lines
5.6 KiB
C
489 lines
5.6 KiB
C
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#define NSNAME 8
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#define NSYM 50
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#define NREG 32
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#define NOPROF (1<<0)
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#define DUPOK (1<<1)
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enum
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{
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REGZERO = 0, /* set to zero */
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REGSP = 1,
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REGSB = 2,
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REGRET = 3,
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REGARG = 3,
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REGMIN = 7, /* register variables allocated from here to REGMAX */
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REGMAX = 27,
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REGEXT = 30, /* external registers allocated from here down */
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REGTMP = 31, /* used by the linker */
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FREGRET = 0,
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FREGMIN = 17, /* first register variable */
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FREGEXT = 26, /* first external register */
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FREGCVI = 27, /* floating conversion constant */
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FREGZERO = 28, /* both float and double */
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FREGHALF = 29, /* double */
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FREGONE = 30, /* double */
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FREGTWO = 31 /* double */
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/*
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* GENERAL:
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*
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* compiler allocates R3 up as temps
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* compiler allocates register variables R7-R27
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* compiler allocates external registers R30 down
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*
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* compiler allocates register variables F17-F26
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* compiler allocates external registers F26 down
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*/
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};
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enum as
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{
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AXXX = 0,
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AADD,
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AADDCC,
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AADDV,
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AADDVCC,
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AADDC,
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AADDCCC,
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AADDCV,
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AADDCVCC,
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AADDME,
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AADDMECC,
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AADDMEVCC,
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AADDMEV,
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AADDE,
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AADDECC,
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AADDEVCC,
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AADDEV,
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AADDZE,
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AADDZECC,
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AADDZEVCC,
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AADDZEV,
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AAND,
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AANDCC,
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AANDN,
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AANDNCC,
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ABC,
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ABCL,
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ABEQ,
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ABGE,
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ABGT,
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ABL,
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ABLE,
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ABLT,
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ABNE,
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ABR,
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ABVC,
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ABVS,
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ACMP,
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ACMPU,
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ACNTLZW,
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ACNTLZWCC,
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ACRAND,
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ACRANDN,
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ACREQV,
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ACRNAND,
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ACRNOR,
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ACROR,
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ACRORN,
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ACRXOR,
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ADIVW,
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ADIVWCC,
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ADIVWVCC,
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ADIVWV,
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ADIVWU,
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ADIVWUCC,
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ADIVWUVCC,
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ADIVWUV,
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AEQV,
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AEQVCC,
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AEXTSB,
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AEXTSBCC,
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AEXTSH,
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AEXTSHCC,
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AFABS,
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AFABSCC,
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AFADD,
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AFADDCC,
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AFADDS,
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AFADDSCC,
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AFCMPO,
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AFCMPU,
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AFCTIW,
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AFCTIWCC,
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AFCTIWZ,
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AFCTIWZCC,
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AFDIV,
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AFDIVCC,
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AFDIVS,
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AFDIVSCC,
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AFMADD,
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AFMADDCC,
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AFMADDS,
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AFMADDSCC,
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AFMOVD,
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AFMOVDCC,
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AFMOVDU,
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AFMOVS,
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AFMOVSU,
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AFMSUB,
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AFMSUBCC,
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AFMSUBS,
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AFMSUBSCC,
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AFMUL,
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AFMULCC,
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AFMULS,
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AFMULSCC,
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AFNABS,
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AFNABSCC,
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AFNEG,
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AFNEGCC,
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AFNMADD,
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AFNMADDCC,
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AFNMADDS,
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AFNMADDSCC,
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AFNMSUB,
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AFNMSUBCC,
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AFNMSUBS,
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AFNMSUBSCC,
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AFRSP,
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AFRSPCC,
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AFSUB,
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AFSUBCC,
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AFSUBS,
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AFSUBSCC,
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AMOVMW,
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ALSW,
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ALWAR,
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AMOVWBR,
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AMOVB,
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AMOVBU,
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AMOVBZ,
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AMOVBZU,
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AMOVH,
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AMOVHBR,
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AMOVHU,
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AMOVHZ,
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AMOVHZU,
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AMOVW,
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AMOVWU,
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AMOVFL,
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AMOVCRFS,
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AMTFSB0,
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AMTFSB0CC,
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AMTFSB1,
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AMTFSB1CC,
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AMULHW,
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AMULHWCC,
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AMULHWU,
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AMULHWUCC,
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AMULLW,
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AMULLWCC,
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AMULLWVCC,
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AMULLWV,
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ANAND,
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ANANDCC,
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ANEG,
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ANEGCC,
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ANEGVCC,
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ANEGV,
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ANOR,
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ANORCC,
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AOR,
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AORCC,
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AORN,
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AORNCC,
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AREM,
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AREMCC,
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AREMV,
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AREMVCC,
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AREMU,
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AREMUCC,
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AREMUV,
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AREMUVCC,
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ARFI,
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ARLWMI,
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ARLWMICC,
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ARLWNM,
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ARLWNMCC,
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ASLW,
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ASLWCC,
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ASRW,
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ASRAW,
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ASRAWCC,
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ASRWCC,
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ASTSW,
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ASTWCCC,
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ASUB,
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ASUBCC,
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ASUBVCC,
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ASUBC,
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ASUBCCC,
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ASUBCV,
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ASUBCVCC,
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ASUBME,
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ASUBMECC,
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ASUBMEVCC,
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ASUBMEV,
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ASUBV,
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ASUBE,
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ASUBECC,
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ASUBEV,
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ASUBEVCC,
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ASUBZE,
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ASUBZECC,
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ASUBZEVCC,
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ASUBZEV,
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ASYNC,
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AXOR,
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AXORCC,
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ADCBF,
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ADCBI,
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ADCBST,
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ADCBT,
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ADCBTST,
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ADCBZ,
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AECIWX,
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AECOWX,
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AEIEIO,
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AICBI,
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AISYNC,
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ATLBIE,
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ATW,
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ASYSCALL,
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ADATA,
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AGLOBL,
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AGOK,
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AHISTORY,
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ANAME,
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ANOP,
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ARETURN,
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ATEXT,
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AWORD,
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AEND,
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ADYNT,
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AINIT,
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ASIGNAME,
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/* IBM powerpc embedded; not portable */
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AMACCHW,
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AMACCHWCC,
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AMACCHWS,
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AMACCHWSCC,
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AMACCHWSU,
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AMACCHWSUCC,
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AMACCHWSUV,
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AMACCHWSUVCC,
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AMACCHWSV,
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AMACCHWSVCC,
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AMACCHWU,
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AMACCHWUCC,
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AMACCHWUV,
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AMACCHWUVCC,
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AMACCHWV,
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AMACCHWVCC,
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AMACHHW,
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AMACHHWCC,
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AMACHHWV,
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AMACHHWVCC,
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AMACHHWS,
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AMACHHWSCC,
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AMACHHWSV,
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AMACHHWSVCC,
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AMACHHWSU,
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AMACHHWSUCC,
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AMACHHWSUV,
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AMACHHWSUVCC,
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AMACHHWU,
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AMACHHWUCC,
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AMACHHWUV,
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AMACHHWUVCC,
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AMACLHW,
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AMACLHWCC,
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AMACLHWS,
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AMACLHWSCC,
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AMACLHWSU,
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AMACLHWSUCC,
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AMACLHWSUV,
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AMACLHWSUVCC,
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AMACLHWSV,
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AMACLHWSVCC,
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AMACLHWU,
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AMACLHWUCC,
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AMACLHWUV,
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AMACLHWUVCC,
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AMACLHWV,
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AMACLHWVCC,
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AMULCHW,
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AMULCHWCC,
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AMULCHWU,
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AMULCHWUCC,
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AMULHHW,
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AMULHHWCC,
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AMULHHWU,
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AMULHHWUCC,
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AMULLHW,
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AMULLHWCC,
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AMULLHWU,
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AMULLHWUCC,
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ANMACCHW,
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ANMACCHWCC,
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ANMACCHWS,
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ANMACCHWSCC,
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ANMACCHWSV,
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ANMACCHWSVCC,
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ANMACCHWV,
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ANMACCHWVCC,
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ANMACHHW,
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ANMACHHWCC,
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ANMACHHWS,
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ANMACHHWSCC,
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ANMACHHWSV,
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ANMACHHWSVCC,
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ANMACHHWV,
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ANMACHHWVCC,
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ANMACLHW,
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ANMACLHWCC,
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ANMACLHWS,
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ANMACLHWSCC,
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ANMACLHWSV,
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ANMACLHWSVCC,
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ANMACLHWV,
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ANMACLHWVCC,
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ARFCI,
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/* optional on 32-bit */
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AFRES,
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AFRESCC,
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AFRSQRTE,
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AFRSQRTECC,
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AFSEL,
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AFSELCC,
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AFSQRT,
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AFSQRTCC,
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AFSQRTS,
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AFSQRTSCC,
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/* parallel, cross, and secondary */
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AFPSEL,
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AFPMUL,
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AFXMUL,
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AFXPMUL,
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AFXSMUL,
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AFPADD,
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AFPSUB,
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AFPRE,
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AFPRSQRTE,
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AFPMADD,
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AFXMADD,
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AFXCPMADD,
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AFXCSMADD,
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AFPNMADD,
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AFXNMADD,
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AFXCPNMADD,
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AFXCSNMADD,
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AFPMSUB,
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AFXMSUB,
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AFXCPMSUB,
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AFXCSMSUB,
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AFPNMSUB,
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AFXNMSUB,
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AFXCPNMSUB,
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AFXCSNMSUB,
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AFPABS,
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AFPNEG,
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AFPRSP,
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AFPNABS,
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AFSCMP,
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AFSABS,
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AFSNEG,
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AFSNABS,
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AFPCTIW,
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AFPCTIWZ,
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AFMOVSPD,
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AFMOVPSD,
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AFXCPNPMA,
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AFXCSNPMA,
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AFXCPNSMA,
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AFXCSNSMA,
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AFXCXNPMA,
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AFXCXNSMA,
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AFXCXMA,
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AFXCXNMS,
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/* parallel, cross, and secondary load and store */
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AFSMOVS,
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AFSMOVSU,
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AFSMOVD,
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AFSMOVDU,
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AFXMOVS,
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AFXMOVSU,
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AFXMOVD,
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AFXMOVDU,
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AFPMOVS,
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AFPMOVSU,
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AFPMOVD,
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AFPMOVDU,
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AFPMOVIW,
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ALAST
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};
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/* type/name */
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enum
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{
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D_GOK = 0,
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D_NONE,
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/* name */
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D_EXTERN,
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D_STATIC,
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D_AUTO,
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D_PARAM,
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/* type */
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D_BRANCH,
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D_OREG,
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D_CONST,
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D_FCONST,
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D_SCONST,
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D_REG,
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D_FPSCR,
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D_MSR,
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D_FREG,
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D_CREG,
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D_SPR,
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D_SREG, /* segment register */
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D_OPT, /* branch/trap option */
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D_FILE,
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D_FILE1,
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D_DCR, /* device control register */
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/* reg names iff type is D_SPR */
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D_XER = 1,
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D_LR = 8,
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D_CTR = 9
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/* and many supervisor level registers */
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};
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/*
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* this is the ranlib header
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*/
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#define SYMDEF "__.SYMDEF"
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/*
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* this is the simulated IEEE floating point
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*/
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typedef struct ieee Ieee;
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struct ieee
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{
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long l; /* contains ls-man 0xffffffff */
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long h; /* contains sign 0x80000000
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exp 0x7ff00000
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ms-man 0x000fffff */
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||
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};
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