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718 lines
22 KiB
C
718 lines
22 KiB
C
/*
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* PROJECT: ReactOS Kernel
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* LICENSE: GNU GPLv2 only as published by the Free Software Foundation
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* PURPOSE: To Implement AHCI Miniport driver targeting storport NT 5.2
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* PROGRAMMERS: Aman Priyadarshi (aman.eureka@gmail.com)
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*/
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#include <ntddk.h>
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#include <ata.h>
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#include <storport.h>
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#define NDEBUG
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#include <debug.h>
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#define DEBUG 1
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#if defined(_MSC_VER)
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#pragma warning(disable:4214) // bit field types other than int
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#pragma warning(disable:4201) // nameless struct/union
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#endif
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#define MAXIMUM_AHCI_PORT_COUNT 32
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#define MAXIMUM_AHCI_PRDT_ENTRIES 32
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#define MAXIMUM_AHCI_PORT_NCS 30
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#define MAXIMUM_QUEUE_BUFFER_SIZE 255
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#define MAXIMUM_TRANSFER_LENGTH (128*1024) // 128 KB
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#define DEVICE_ATA_BLOCK_SIZE 512
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// device type (DeviceParams)
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#define AHCI_DEVICE_TYPE_ATA 1
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#define AHCI_DEVICE_TYPE_ATAPI 2
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#define AHCI_DEVICE_TYPE_NODEVICE 3
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// section 3.1.2
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#define AHCI_Global_HBA_CAP_S64A (1 << 31)
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// FIS Types : http://wiki.osdev.org/AHCI
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#define FIS_TYPE_REG_H2D 0x27 // Register FIS - host to device
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#define FIS_TYPE_REG_D2H 0x34 // Register FIS - device to host
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#define FIS_TYPE_DMA_ACT 0x39 // DMA activate FIS - device to host
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#define FIS_TYPE_DMA_SETUP 0x41 // DMA setup FIS - bidirectional
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#define FIS_TYPE_BIST 0x58 // BIST activate FIS - bidirectional
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#define FIS_TYPE_PIO_SETUP 0x5F // PIO setup FIS - device to host
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#define FIS_TYPE_DEV_BITS 0xA1 // Set device bits FIS - device to host
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#define AHCI_ATA_CFIS_FisType 0
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#define AHCI_ATA_CFIS_PMPort_C 1
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#define AHCI_ATA_CFIS_CommandReg 2
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#define AHCI_ATA_CFIS_FeaturesLow 3
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#define AHCI_ATA_CFIS_LBA0 4
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#define AHCI_ATA_CFIS_LBA1 5
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#define AHCI_ATA_CFIS_LBA2 6
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#define AHCI_ATA_CFIS_Device 7
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#define AHCI_ATA_CFIS_LBA3 8
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#define AHCI_ATA_CFIS_LBA4 9
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#define AHCI_ATA_CFIS_LBA5 10
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#define AHCI_ATA_CFIS_FeaturesHigh 11
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#define AHCI_ATA_CFIS_SectorCountLow 12
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#define AHCI_ATA_CFIS_SectorCountHigh 13
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// ATA Functions
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#define ATA_FUNCTION_ATA_COMMAND 0x100
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#define ATA_FUNCTION_ATA_IDENTIFY 0x101
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#define ATA_FUNCTION_ATA_READ 0x102
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// ATAPI Functions
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#define ATA_FUNCTION_ATAPI_COMMAND 0x200
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// ATA Flags
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#define ATA_FLAGS_DATA_IN (1 << 1)
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#define ATA_FLAGS_DATA_OUT (1 << 2)
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#define ATA_FLAGS_48BIT_COMMAND (1 << 3)
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#define ATA_FLAGS_USE_DMA (1 << 4)
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#define IsAtaCommand(AtaFunction) (AtaFunction & ATA_FUNCTION_ATA_COMMAND)
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#define IsAtapiCommand(AtaFunction) (AtaFunction & ATA_FUNCTION_ATAPI_COMMAND)
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#define IsDataTransferNeeded(SrbExtension) (SrbExtension->Flags & (ATA_FLAGS_DATA_IN | ATA_FLAGS_DATA_OUT))
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#define IsAdapterCAPS64(CAP) (CAP & AHCI_Global_HBA_CAP_S64A)
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// 3.1.1 NCS = CAP[12:08] -> Align
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#define AHCI_Global_Port_CAP_NCS(x) (((x) & 0xF00) >> 8)
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#define ROUND_UP(N, S) ((((N) + (S) - 1) / (S)) * (S))
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//#define AhciDebugPrint(format, ...) StorPortDebugPrint(0, format, __VA_ARGS__)
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#define AhciDebugPrint(format, ...) DbgPrint("(%s:%d) " format, __RELFILE__, __LINE__, ##__VA_ARGS__)
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typedef
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VOID
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(*PAHCI_COMPLETION_ROUTINE) (
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__in PVOID PortExtension,
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__in PVOID Srb
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);
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//////////////////////////////////////////////////////////////
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// ---- Support Structures --- //
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//////////////////////////////////////////////////////////////
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// section 3.3.5
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typedef union _AHCI_INTERRUPT_STATUS
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{
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struct
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{
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ULONG DHRS:1; //Device to Host Register FIS Interrupt
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ULONG PSS :1; //PIO Setup FIS Interrupt
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ULONG DSS :1; //DMA Setup FIS Interrupt
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ULONG SDBS :1; //Set Device Bits Interrupt
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ULONG UFS :1; //Unknown FIS Interrupt
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ULONG DPS :1; //Descriptor Processed
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ULONG PCS :1; //Port Connect Change Status
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ULONG DMPS :1; //Device Mechanical Presence Status (DMPS)
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ULONG Reserved :14;
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ULONG PRCS :1; //PhyRdy Change Status
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ULONG IPMS :1; //Incorrect Port Multiplier Status
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ULONG OFS :1; //Overflow Status
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ULONG Reserved2 :1;
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ULONG INFS :1; //Interface Non-fatal Error Status
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ULONG IFS :1; //Interface Fatal Error Status
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ULONG HBDS :1; //Host Bus Data Error Status
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ULONG HBFS :1; //Host Bus Fatal Error Status
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ULONG TFES :1; //Task File Error Status
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ULONG CPDS :1; //Cold Port Detect Status
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};
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ULONG Status;
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} AHCI_INTERRUPT_STATUS;
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typedef struct _AHCI_FIS_DMA_SETUP
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{
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ULONG ULONG0_1; // FIS_TYPE_DMA_SETUP
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// Port multiplier
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// Reserved
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// Data transfer direction, 1 - device to host
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// Interrupt bit
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// Auto-activate. Specifies if DMA Activate FIS is needed
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UCHAR Reserved[2]; // Reserved
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ULONG DmaBufferLow; // DMA Buffer Identifier. Used to Identify DMA buffer in host memory. SATA Spec says host specific and not in Spec. Trying AHCI spec might work.
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ULONG DmaBufferHigh;
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ULONG Reserved2; // More reserved
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ULONG DmaBufferOffset; // Byte offset into buffer. First 2 bits must be 0
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ULONG TranferCount; // Number of bytes to transfer. Bit 0 must be 0
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ULONG Reserved3; // Reserved
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} AHCI_FIS_DMA_SETUP;
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typedef struct _AHCI_PIO_SETUP_FIS
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{
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UCHAR FisType;
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UCHAR Reserved1 :5;
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UCHAR D :1;
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UCHAR I :1;
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UCHAR Reserved2 :1;
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UCHAR Status;
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UCHAR Error;
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UCHAR SectorNumber;
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UCHAR CylLow;
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UCHAR CylHigh;
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UCHAR Dev_Head;
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UCHAR SectorNumb_Exp;
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UCHAR CylLow_Exp;
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UCHAR CylHigh_Exp;
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UCHAR Reserved3;
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UCHAR SectorCount;
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UCHAR SectorCount_Exp;
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UCHAR Reserved4;
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UCHAR E_Status;
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USHORT TransferCount;
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UCHAR Reserved5[2];
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} AHCI_PIO_SETUP_FIS;
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typedef struct _AHCI_D2H_REGISTER_FIS
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{
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UCHAR FisType;
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UCHAR Reserved1 :6;
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UCHAR I:1;
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UCHAR Reserved2 :1;
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UCHAR Status;
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UCHAR Error;
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UCHAR SectorNumber;
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UCHAR CylLow;
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UCHAR CylHigh;
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UCHAR Dev_Head;
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UCHAR SectorNum_Exp;
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UCHAR CylLow_Exp;
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UCHAR CylHigh_Exp;
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UCHAR Reserved;
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UCHAR SectorCount;
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UCHAR SectorCount_Exp;
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UCHAR Reserved3[2];
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UCHAR Reserved4[4];
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} AHCI_D2H_REGISTER_FIS;
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typedef struct _AHCI_SET_DEVICE_BITS_FIS
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{
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UCHAR FisType;
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UCHAR PMPort: 4;
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UCHAR Reserved1 :2;
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UCHAR I :1;
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UCHAR N :1;
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UCHAR Status_Lo :3;
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UCHAR Reserved2 :1;
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UCHAR Status_Hi :3;
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UCHAR Reserved3 :1;
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UCHAR Error;
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UCHAR Reserved5[4];
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} AHCI_SET_DEVICE_BITS_FIS;
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typedef struct _AHCI_QUEUE
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{
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PVOID Buffer[MAXIMUM_QUEUE_BUFFER_SIZE]; // because Storahci hold Srb queue of 255 size
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ULONG Head;
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ULONG Tail;
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} AHCI_QUEUE, *PAHCI_QUEUE;
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//////////////////////////////////////////////////////////////
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// --------------------------- //
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//////////////////////////////////////////////////////////////
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typedef union _AHCI_COMMAND_HEADER_DESCRIPTION
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{
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struct
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{
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ULONG CFL : 5; // Command FIS Length
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ULONG A : 1; // IsATAPI
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ULONG W : 1; // Write
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ULONG P : 1; // Prefetchable
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ULONG R : 1; // Reset
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ULONG B : 1; // BIST
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ULONG C : 1; //Clear Busy upon R_OK
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ULONG RSV : 1;
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ULONG PMP : 4; //Port Multiplier Port
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ULONG PRDTL : 16; //Physical Region Descriptor Table Length
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};
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ULONG Status;
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} AHCI_COMMAND_HEADER_DESCRIPTION;
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typedef union _AHCI_GHC
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{
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struct
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{
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ULONG HR : 1;
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ULONG IE : 1;
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ULONG MRSM : 1;
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ULONG RSV0 : 28;
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ULONG AE : 1;
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};
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ULONG Status;
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} AHCI_GHC;
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// section 3.3.7
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typedef union _AHCI_PORT_CMD
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{
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struct
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{
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ULONG ST : 1;
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ULONG SUD : 1;
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ULONG POD : 1;
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ULONG CLO : 1;
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ULONG FRE : 1;
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ULONG RSV0 : 3;
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ULONG CCS : 5;
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ULONG MPSS : 1;
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ULONG FR : 1;
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ULONG CR : 1;
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ULONG CPS : 1;
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ULONG PMA : 1;
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ULONG HPCP : 1;
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ULONG MPSP : 1;
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ULONG CPD : 1;
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ULONG ESP : 1;
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ULONG FBSCP : 1;
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ULONG APSTE : 1;
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ULONG ATAPI : 1;
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ULONG DLAE : 1;
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ULONG ALPE : 1;
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ULONG ASP : 1;
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ULONG ICC : 4;
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};
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ULONG Status;
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} AHCI_PORT_CMD;
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typedef union _AHCI_SERIAL_ATA_CONTROL
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{
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struct
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{
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ULONG DET :4;
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ULONG SPD :4;
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ULONG IPM :4;
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ULONG SPM :4;
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ULONG PMP :4;
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ULONG DW11_Reserved :12;
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};
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ULONG Status;
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} AHCI_SERIAL_ATA_CONTROL;
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typedef union _AHCI_SERIAL_ATA_STATUS
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{
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struct
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{
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ULONG DET :4;
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ULONG SPD :4;
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ULONG IPM :4;
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ULONG RSV0 :20;
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};
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ULONG Status;
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} AHCI_SERIAL_ATA_STATUS;
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typedef union _AHCI_TASK_FILE_DATA
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{
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struct
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{
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struct _STS
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{
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UCHAR ERR : 1;
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UCHAR CS1 : 2;
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UCHAR DRQ : 1;
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UCHAR CS2 : 3;
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UCHAR BSY : 1;
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} STS;
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UCHAR ERR;
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USHORT RSV;
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};
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ULONG Status;
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} AHCI_TASK_FILE_DATA;
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typedef struct _AHCI_PRDT
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{
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ULONG DBA;
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ULONG DBAU;
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ULONG RSV0;
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ULONG DBC : 22;
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ULONG RSV1 : 9;
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ULONG I : 1;
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} AHCI_PRDT, *PAHCI_PRDT;
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// 4.2.3 Command Table
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typedef struct _AHCI_COMMAND_TABLE
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{
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// (16 * 32) + 64 + 16 + 48 = 648
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// 128 byte aligned :D
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UCHAR CFIS[64];
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UCHAR ACMD[16];
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UCHAR RSV0[48];
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AHCI_PRDT PRDT[MAXIMUM_AHCI_PRDT_ENTRIES];
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} AHCI_COMMAND_TABLE, *PAHCI_COMMAND_TABLE;
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// 4.2.2 Command Header
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typedef struct _AHCI_COMMAND_HEADER
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{
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AHCI_COMMAND_HEADER_DESCRIPTION DI; // DW 0
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ULONG PRDBC; // DW 1
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ULONG CTBA; // DW 2
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ULONG CTBA_U; // DW 3
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ULONG Reserved[4]; // DW 4-7
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} AHCI_COMMAND_HEADER, *PAHCI_COMMAND_HEADER;
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// Received FIS
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typedef struct _AHCI_RECEIVED_FIS
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{
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struct _AHCI_FIS_DMA_SETUP DmaSetupFIS; // 0x00 -- DMA Setup FIS
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ULONG pad0; // 4 BYTE padding
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struct _AHCI_PIO_SETUP_FIS PioSetupFIS; // 0x20 -- PIO Setup FIS
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ULONG pad1[3]; // 12 BYTE padding
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struct _AHCI_D2H_REGISTER_FIS RegisterFIS; // 0x40 -- Register – Device to Host FIS
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ULONG pad2; // 4 BYTE padding
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struct _AHCI_SET_DEVICE_BITS_FIS SetDeviceFIS; // 0x58 -- Set Device Bit FIS
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ULONG UnknowFIS[16]; // 0x60 -- Unknown FIS
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ULONG Reserved[24]; // 0xA0 -- Reserved
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} AHCI_RECEIVED_FIS, *PAHCI_RECEIVED_FIS;
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// Holds Port Information
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typedef struct _AHCI_PORT
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{
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ULONG CLB; // 0x00, command list base address, 1K-byte aligned
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ULONG CLBU; // 0x04, command list base address upper 32 bits
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ULONG FB; // 0x08, FIS base address, 256-byte aligned
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ULONG FBU; // 0x0C, FIS base address upper 32 bits
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ULONG IS; // 0x10, interrupt status
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ULONG IE; // 0x14, interrupt enable
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ULONG CMD; // 0x18, command and status
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ULONG RSV0; // 0x1C, Reserved
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ULONG TFD; // 0x20, task file data
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ULONG SIG; // 0x24, signature
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ULONG SSTS; // 0x28, SATA status (SCR0:SStatus)
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ULONG SCTL; // 0x2C, SATA control (SCR2:SControl)
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ULONG SERR; // 0x30, SATA error (SCR1:SError)
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ULONG SACT; // 0x34, SATA active (SCR3:SActive)
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ULONG CI; // 0x38, command issue
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ULONG SNTF; // 0x3C, SATA notification (SCR4:SNotification)
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ULONG FBS; // 0x40, FIS-based switch control
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ULONG RSV1[11]; // 0x44 ~ 0x6F, Reserved
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ULONG Vendor[4]; // 0x70 ~ 0x7F, vendor specific
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} AHCI_PORT, *PAHCI_PORT;
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typedef union _AHCI_INTERRUPT_ENABLE
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{
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struct
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{
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ULONG DHRE :1;
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ULONG PSE :1;
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ULONG DSE :1;
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ULONG SDBE :1;
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ULONG UFE :1;
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ULONG DPE :1;
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ULONG PCE :1;
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ULONG DMPE :1;
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ULONG DW5_Reserved :14;
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ULONG PRCE :1;
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ULONG IPME :1;
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ULONG OFE :1;
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ULONG DW5_Reserved2 :1;
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ULONG INFE :1;
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ULONG IFE :1;
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ULONG HBDE :1;
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ULONG HBFE :1;
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ULONG TFEE :1;
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ULONG CPDE :1;
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};
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ULONG Status;
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} AHCI_INTERRUPT_ENABLE;
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typedef struct _AHCI_MEMORY_REGISTERS
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{
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// 0x00 - 0x2B, Generic Host Control
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ULONG CAP; // 0x00, Host capability
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ULONG GHC; // 0x04, Global host control
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ULONG IS; // 0x08, Interrupt status
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ULONG PI; // 0x0C, Port implemented
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ULONG VS; // 0x10, Version
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ULONG CCC_CTL; // 0x14, Command completion coalescing control
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ULONG CCC_PTS; // 0x18, Command completion coalescing ports
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ULONG EM_LOC; // 0x1C, Enclosure management location
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ULONG EM_CTL; // 0x20, Enclosure management control
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ULONG CAP2; // 0x24, Host capabilities extended
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ULONG BOHC; // 0x28, BIOS/OS handoff control and status
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ULONG Reserved[0x1d]; // 0x2C - 0x9F, Reserved
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ULONG VendorSpecific[0x18]; // 0xA0 - 0xFF, Vendor specific registers
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AHCI_PORT PortList[MAXIMUM_AHCI_PORT_COUNT];
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} AHCI_MEMORY_REGISTERS, *PAHCI_MEMORY_REGISTERS;
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// Holds information for each attached attached port to a given adapter.
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typedef struct _AHCI_PORT_EXTENSION
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{
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ULONG PortNumber;
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ULONG QueueSlots; // slots which we have already assigned task (Slot)
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ULONG CommandIssuedSlots; // slots which has been programmed
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ULONG MaxPortQueueDepth;
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struct
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{
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UCHAR RemovableDevice;
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UCHAR Lba48BitMode;
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UCHAR AccessType;
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UCHAR DeviceType;
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UCHAR IsActive;
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LARGE_INTEGER MaxLba;
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ULONG BytesPerLogicalSector;
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ULONG BytesPerPhysicalSector;
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UCHAR VendorId[41];
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UCHAR RevisionID[9];
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UCHAR SerialNumber[21];
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} DeviceParams;
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STOR_DPC CommandCompletion;
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PAHCI_PORT Port; // AHCI Port Infomation
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AHCI_QUEUE SrbQueue; // pending Srbs
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AHCI_QUEUE CompletionQueue;
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PSCSI_REQUEST_BLOCK Slot[MAXIMUM_AHCI_PORT_NCS]; // Srbs which has been alloted a port
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PAHCI_RECEIVED_FIS ReceivedFIS;
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PAHCI_COMMAND_HEADER CommandList;
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STOR_DEVICE_POWER_STATE DevicePowerState; // Device Power State
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PIDENTIFY_DEVICE_DATA IdentifyDeviceData;
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STOR_PHYSICAL_ADDRESS IdentifyDeviceDataPhysicalAddress;
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struct _AHCI_ADAPTER_EXTENSION* AdapterExtension; // Port's Adapter Information
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} AHCI_PORT_EXTENSION, *PAHCI_PORT_EXTENSION;
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// Holds Adapter Information
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typedef struct _AHCI_ADAPTER_EXTENSION
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{
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ULONG SystemIoBusNumber;
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ULONG SlotNumber;
|
||
ULONG AhciBaseAddress;
|
||
PULONG IS;// Interrupt Status, In case of MSIM == `1`
|
||
ULONG PortImplemented;// bit-mapping of ports which are implemented
|
||
ULONG PortCount;
|
||
|
||
USHORT VendorID;
|
||
USHORT DeviceID;
|
||
USHORT RevisionID;
|
||
|
||
ULONG Version;
|
||
ULONG CAP;
|
||
ULONG CAP2;
|
||
ULONG LastInterruptPort;
|
||
ULONG CurrentCommandSlot;
|
||
|
||
PVOID NonCachedExtension; // holds virtual address to noncached buffer allocated for Port Extension
|
||
|
||
struct
|
||
{
|
||
// Message per port or shared port?
|
||
ULONG MessagePerPort : 1;
|
||
ULONG Removed : 1;
|
||
ULONG Reserved : 30; // not in use -- maintain 4 byte alignment
|
||
} StateFlags;
|
||
|
||
PAHCI_MEMORY_REGISTERS ABAR_Address;
|
||
AHCI_PORT_EXTENSION PortExtension[MAXIMUM_AHCI_PORT_COUNT];
|
||
} AHCI_ADAPTER_EXTENSION, *PAHCI_ADAPTER_EXTENSION;
|
||
|
||
typedef struct _LOCAL_SCATTER_GATHER_LIST
|
||
{
|
||
ULONG NumberOfElements;
|
||
ULONG_PTR Reserved;
|
||
STOR_SCATTER_GATHER_ELEMENT List[MAXIMUM_AHCI_PRDT_ENTRIES];
|
||
} LOCAL_SCATTER_GATHER_LIST, *PLOCAL_SCATTER_GATHER_LIST;
|
||
|
||
typedef struct _AHCI_SRB_EXTENSION
|
||
{
|
||
AHCI_COMMAND_TABLE CommandTable;
|
||
ULONG AtaFunction;
|
||
ULONG Flags;
|
||
|
||
UCHAR CommandReg;
|
||
UCHAR FeaturesLow;
|
||
UCHAR LBA0;
|
||
UCHAR LBA1;
|
||
UCHAR LBA2;
|
||
UCHAR Device;
|
||
UCHAR LBA3;
|
||
UCHAR LBA4;
|
||
UCHAR LBA5;
|
||
UCHAR FeaturesHigh;
|
||
|
||
UCHAR SectorCountLow;
|
||
UCHAR SectorCountHigh;
|
||
|
||
ULONG SlotIndex;
|
||
LOCAL_SCATTER_GATHER_LIST Sgl;
|
||
PLOCAL_SCATTER_GATHER_LIST pSgl;
|
||
PAHCI_COMPLETION_ROUTINE CompletionRoutine;
|
||
|
||
// for alignment purpose -- 128 byte alignment
|
||
// do not try to access (R/W) this field
|
||
UCHAR Reserved[128];
|
||
} AHCI_SRB_EXTENSION, *PAHCI_SRB_EXTENSION;
|
||
|
||
//////////////////////////////////////////////////////////////
|
||
// Declarations //
|
||
//////////////////////////////////////////////////////////////
|
||
|
||
VOID
|
||
AhciProcessIO (
|
||
__in PAHCI_ADAPTER_EXTENSION AdapterExtension,
|
||
__in UCHAR PathId,
|
||
__in PSCSI_REQUEST_BLOCK Srb
|
||
);
|
||
|
||
BOOLEAN
|
||
AhciAdapterReset (
|
||
__in PAHCI_ADAPTER_EXTENSION AdapterExtension
|
||
);
|
||
|
||
FORCEINLINE
|
||
VOID
|
||
AhciZeroMemory (
|
||
__out PCHAR Buffer,
|
||
__in ULONG BufferSize
|
||
);
|
||
|
||
FORCEINLINE
|
||
BOOLEAN
|
||
IsPortValid (
|
||
__in PAHCI_ADAPTER_EXTENSION AdapterExtension,
|
||
__in ULONG pathId
|
||
);
|
||
|
||
UCHAR DeviceRequestSense (
|
||
__in PAHCI_ADAPTER_EXTENSION AdapterExtension,
|
||
__in PSCSI_REQUEST_BLOCK Srb,
|
||
__in PCDB Cdb
|
||
);
|
||
|
||
UCHAR DeviceRequestReadWrite (
|
||
__in PAHCI_ADAPTER_EXTENSION AdapterExtension,
|
||
__in PSCSI_REQUEST_BLOCK Srb,
|
||
__in PCDB Cdb
|
||
);
|
||
|
||
UCHAR DeviceRequestCapacity (
|
||
__in PAHCI_ADAPTER_EXTENSION AdapterExtension,
|
||
__in PSCSI_REQUEST_BLOCK Srb,
|
||
__in PCDB Cdb
|
||
);
|
||
|
||
UCHAR
|
||
DeviceInquiryRequest (
|
||
__in PAHCI_ADAPTER_EXTENSION AdapterExtension,
|
||
__in PSCSI_REQUEST_BLOCK Srb,
|
||
__in PCDB Cdb
|
||
);
|
||
|
||
UCHAR DeviceRequestComplete (
|
||
__in PAHCI_ADAPTER_EXTENSION AdapterExtension,
|
||
__in PSCSI_REQUEST_BLOCK Srb,
|
||
__in PCDB Cdb
|
||
);
|
||
|
||
UCHAR DeviceReportLuns (
|
||
__in PAHCI_ADAPTER_EXTENSION AdapterExtension,
|
||
__in PSCSI_REQUEST_BLOCK Srb,
|
||
__in PCDB Cdb
|
||
);
|
||
|
||
FORCEINLINE
|
||
BOOLEAN
|
||
AddQueue (
|
||
__inout PAHCI_QUEUE Queue,
|
||
__in PVOID Srb
|
||
);
|
||
|
||
FORCEINLINE
|
||
PVOID
|
||
RemoveQueue (
|
||
__inout PAHCI_QUEUE Queue
|
||
);
|
||
|
||
FORCEINLINE
|
||
PAHCI_SRB_EXTENSION
|
||
GetSrbExtension(
|
||
__in PSCSI_REQUEST_BLOCK Srb
|
||
);
|
||
|
||
FORCEINLINE
|
||
ULONG64
|
||
AhciGetLba (
|
||
__in PCDB Cdb,
|
||
__in ULONG CdbLength
|
||
);
|
||
|
||
//////////////////////////////////////////////////////////////
|
||
// Assertions //
|
||
//////////////////////////////////////////////////////////////
|
||
|
||
// I assert every silly mistake I can do while coding
|
||
// because god never help me debugging the code
|
||
// but these asserts do :')
|
||
|
||
C_ASSERT(FIELD_OFFSET(AHCI_MEMORY_REGISTERS, CAP) == 0x00);
|
||
C_ASSERT(FIELD_OFFSET(AHCI_MEMORY_REGISTERS, GHC) == 0x04);
|
||
C_ASSERT(FIELD_OFFSET(AHCI_MEMORY_REGISTERS, IS) == 0x08);
|
||
C_ASSERT(FIELD_OFFSET(AHCI_MEMORY_REGISTERS, PI) == 0x0C);
|
||
C_ASSERT(FIELD_OFFSET(AHCI_MEMORY_REGISTERS, VS) == 0x10);
|
||
C_ASSERT(FIELD_OFFSET(AHCI_MEMORY_REGISTERS, CCC_CTL) == 0x14);
|
||
C_ASSERT(FIELD_OFFSET(AHCI_MEMORY_REGISTERS, CCC_PTS) == 0x18);
|
||
C_ASSERT(FIELD_OFFSET(AHCI_MEMORY_REGISTERS, EM_LOC) == 0x1C);
|
||
C_ASSERT(FIELD_OFFSET(AHCI_MEMORY_REGISTERS, EM_CTL) == 0x20);
|
||
C_ASSERT(FIELD_OFFSET(AHCI_MEMORY_REGISTERS, CAP2) == 0x24);
|
||
C_ASSERT(FIELD_OFFSET(AHCI_MEMORY_REGISTERS, BOHC) == 0x28);
|
||
C_ASSERT(FIELD_OFFSET(AHCI_MEMORY_REGISTERS, Reserved) == 0x2C);
|
||
C_ASSERT(FIELD_OFFSET(AHCI_MEMORY_REGISTERS, VendorSpecific) == 0xA0);
|
||
C_ASSERT(FIELD_OFFSET(AHCI_MEMORY_REGISTERS, PortList) == 0x100);
|
||
|
||
C_ASSERT(FIELD_OFFSET(AHCI_PORT, CLB) == 0x00);
|
||
C_ASSERT(FIELD_OFFSET(AHCI_PORT, CLBU) == 0x04);
|
||
C_ASSERT(FIELD_OFFSET(AHCI_PORT, FB) == 0x08);
|
||
C_ASSERT(FIELD_OFFSET(AHCI_PORT, FBU) == 0x0C);
|
||
C_ASSERT(FIELD_OFFSET(AHCI_PORT, IS) == 0x10);
|
||
C_ASSERT(FIELD_OFFSET(AHCI_PORT, IE) == 0x14);
|
||
C_ASSERT(FIELD_OFFSET(AHCI_PORT, CMD) == 0x18);
|
||
C_ASSERT(FIELD_OFFSET(AHCI_PORT, RSV0) == 0x1C);
|
||
C_ASSERT(FIELD_OFFSET(AHCI_PORT, TFD) == 0x20);
|
||
C_ASSERT(FIELD_OFFSET(AHCI_PORT, SIG) == 0x24);
|
||
C_ASSERT(FIELD_OFFSET(AHCI_PORT, SSTS) == 0x28);
|
||
C_ASSERT(FIELD_OFFSET(AHCI_PORT, SCTL) == 0x2C);
|
||
C_ASSERT(FIELD_OFFSET(AHCI_PORT, SERR) == 0x30);
|
||
C_ASSERT(FIELD_OFFSET(AHCI_PORT, SACT) == 0x34);
|
||
C_ASSERT(FIELD_OFFSET(AHCI_PORT, CI) == 0x38);
|
||
C_ASSERT(FIELD_OFFSET(AHCI_PORT, SNTF) == 0x3C);
|
||
C_ASSERT(FIELD_OFFSET(AHCI_PORT, FBS) == 0x40);
|
||
C_ASSERT(FIELD_OFFSET(AHCI_PORT, RSV1) == 0x44);
|
||
C_ASSERT(FIELD_OFFSET(AHCI_PORT, Vendor) == 0x70);
|
||
|
||
C_ASSERT((sizeof(AHCI_COMMAND_TABLE) % 128) == 0);
|
||
|
||
C_ASSERT(sizeof(AHCI_GHC) == sizeof(ULONG));
|
||
C_ASSERT(sizeof(AHCI_PORT_CMD) == sizeof(ULONG));
|
||
C_ASSERT(sizeof(AHCI_TASK_FILE_DATA) == sizeof(ULONG));
|
||
C_ASSERT(sizeof(AHCI_INTERRUPT_ENABLE) == sizeof(ULONG));
|
||
C_ASSERT(sizeof(AHCI_SERIAL_ATA_STATUS) == sizeof(ULONG));
|
||
C_ASSERT(sizeof(AHCI_SERIAL_ATA_CONTROL) == sizeof(ULONG));
|
||
C_ASSERT(sizeof(AHCI_COMMAND_HEADER_DESCRIPTION) == sizeof(ULONG));
|
||
|
||
C_ASSERT(FIELD_OFFSET(AHCI_COMMAND_TABLE, CFIS) == 0x00);
|
||
C_ASSERT(FIELD_OFFSET(AHCI_COMMAND_TABLE, ACMD) == 0x40);
|
||
C_ASSERT(FIELD_OFFSET(AHCI_COMMAND_TABLE, RSV0) == 0x50);
|
||
C_ASSERT(FIELD_OFFSET(AHCI_COMMAND_TABLE, PRDT) == 0x80);
|