mirror of
https://github.com/reactos/reactos.git
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227 lines
4.1 KiB
C
227 lines
4.1 KiB
C
/*
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* PROJECT: ReactOS Kernel
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* LICENSE: BSD - See COPYING.ARM in the top level directory
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* FILE: ntoskrnl/ke/arm/cpu.c
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* PURPOSE: Implements routines for ARM CPU support
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* PROGRAMMERS: ReactOS Portable Systems Group
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*/
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/* INCLUDES *******************************************************************/
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#include <ntoskrnl.h>
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#define NDEBUG
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#include <debug.h>
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/* GLOBALS ********************************************************************/
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ULONG KeFixedTbEntries;
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ULONG KiDmaIoCoherency;
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ULONG KeIcacheFlushCount = 0;
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ULONG KeDcacheFlushCount;
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ULONG KeLargestCacheLine = 64; // FIXME: It depends
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/* FUNCTIONS ******************************************************************/
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VOID
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KiFlushSingleTb(IN BOOLEAN Invalid,
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IN PVOID Virtual)
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{
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//
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// Just invalidate it
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//
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KeArmInvalidateTlbEntry(Virtual);
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}
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VOID
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KeFlushTb(VOID)
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{
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//
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// Flush the entire TLB
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//
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KeArmFlushTlb();
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}
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VOID
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NTAPI
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KeFlushCurrentTb(VOID)
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{
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//
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// Rename?
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//
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KeFlushTb();
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}
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VOID
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FASTCALL
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KeZeroPages(IN PVOID Address,
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IN ULONG Size)
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{
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/* Not using XMMI in this routine */
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RtlZeroMemory(Address, Size);
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}
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VOID
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NTAPI
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KiSaveProcessorControlState(OUT PKPROCESSOR_STATE ProcessorState)
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{
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//
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// Save some critical stuff we use
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//
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__debugbreak();
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#if 0
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ProcessorState->SpecialRegisters.ControlRegister = KeArmControlRegisterGet();
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ProcessorState->SpecialRegisters.LockdownRegister = KeArmLockdownRegisterGet();
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ProcessorState->SpecialRegisters.CacheRegister = KeArmCacheRegisterGet();
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ProcessorState->SpecialRegisters.StatusRegister = KeArmStatusRegisterGet();
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#endif
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}
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VOID
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NTAPI
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KiRestoreProcessorControlState(PKPROCESSOR_STATE ProcessorState)
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{
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__debugbreak();
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#if 0
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KeArmControlRegisterSet(ProcessorState->SpecialRegisters.ControlRegister);
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KeArmLockdownRegisterSet(ProcessorState->SpecialRegisters.LockdownRegister);
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KeArmCacheRegisterSet(ProcessorState->SpecialRegisters.CacheRegister);
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KeArmStatusRegisterSet(ProcessorState->SpecialRegisters.StatusRegister);
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#endif
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}
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BOOLEAN
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NTAPI
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KeInvalidateAllCaches(VOID)
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{
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//
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// Invalidate D cache and I cache
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//
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KeArmInvalidateAllCaches();
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return TRUE;
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}
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/* PUBLIC FUNCTIONS ***********************************************************/
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/*
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* @implemented
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*/
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ULONG
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NTAPI
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KeGetRecommendedSharedDataAlignment(VOID)
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{
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/* Return the global variable */
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return KeLargestCacheLine;
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}
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/*
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* @implemented
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*/
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VOID
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NTAPI
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KeFlushEntireTb(IN BOOLEAN Invalid,
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IN BOOLEAN AllProcessors)
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{
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KIRQL OldIrql;
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//
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// Raise the IRQL for the TB Flush
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//
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OldIrql = KeRaiseIrqlToSynchLevel();
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//
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// Flush the TB for the Current CPU
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//
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KeFlushCurrentTb();
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//
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// Return to Original IRQL
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//
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KeLowerIrql(OldIrql);
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}
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/*
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* @implemented
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*/
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VOID
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NTAPI
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KeSetDmaIoCoherency(IN ULONG Coherency)
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{
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//
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// Save the coherency globally
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//
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KiDmaIoCoherency = Coherency;
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}
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/*
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* @implemented
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*/
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KAFFINITY
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NTAPI
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KeQueryActiveProcessors(VOID)
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{
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PAGED_CODE();
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//
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// Simply return the number of active processors
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//
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return KeActiveProcessors;
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}
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/*
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* @implemented
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*/
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VOID
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__cdecl
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KeSaveStateForHibernate(IN PKPROCESSOR_STATE State)
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{
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//
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// Capture the context
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//
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RtlCaptureContext(&State->ContextFrame);
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//
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// Capture the control state
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//
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KiSaveProcessorControlState(State);
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}
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VOID
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NTAPI
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KeFlushIoBuffers(
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_In_ PMDL Mdl,
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_In_ BOOLEAN ReadOperation,
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_In_ BOOLEAN DmaOperation)
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{
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DbgBreakPoint();
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}
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/* SYSTEM CALLS NOT VALID ON THIS CPU *****************************************/
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/*
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* @implemented
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*/
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NTSTATUS
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NTAPI
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NtVdmControl(IN ULONG ControlCode,
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IN PVOID ControlData)
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{
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//
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// Does not exist on ARM
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//
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return STATUS_NOT_IMPLEMENTED;
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}
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NTSTATUS
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NTAPI
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NtSetLdtEntries(IN ULONG Selector1,
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IN LDT_ENTRY LdtEntry1,
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IN ULONG Selector2,
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IN LDT_ENTRY LdtEntry2)
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{
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//
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// Does not exist on ARM
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//
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return STATUS_NOT_IMPLEMENTED;
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}
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