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97 lines
3.1 KiB
C
97 lines
3.1 KiB
C
/*
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* Lowlevel memory managment definitions
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*/
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#pragma once
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struct _EPROCESS;
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PULONG MmGetPageDirectory(VOID);
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#ifdef _PAE_
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#define _MI_PAGING_LEVELS 3
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#else
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#define _MI_PAGING_LEVELS 2
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#endif
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#define PAGE_MASK(x) ((x)&(~0xfff))
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#define PAE_PAGE_MASK(x) ((x)&(~0xfffLL))
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/* Base addresses of PTE and PDE */
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#define PAGETABLE_MAP (0xc0000000)
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#define PAGEDIRECTORY_MAP (0xc0000000 + (PAGETABLE_MAP / (1024)))
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/* FIXME: These are different for PAE */
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#define PTE_BASE 0xC0000000
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#define PDE_BASE 0xC0300000
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#define PDE_TOP 0xC0300FFF
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#define PTE_TOP 0xC03FFFFF
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#define HYPER_SPACE 0xC0400000
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/* Converting address to a corresponding PDE or PTE entry */
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#define MiAddressToPde(x) \
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((PMMPTE)(((((ULONG)(x)) >> 22) << 2) + PAGEDIRECTORY_MAP))
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#define MiAddressToPte(x) \
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((PMMPTE)(((((ULONG)(x)) >> 12) << 2) + PAGETABLE_MAP))
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#define MiAddressToPteOffset(x) \
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((((ULONG)(x)) << 10) >> 22)
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//
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// Convert a PTE into a corresponding address
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//
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#define MiPteToAddress(PTE) ((PVOID)((ULONG)(PTE) << 10))
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#define ADDR_TO_PAGE_TABLE(v) (((ULONG)(v)) / (1024 * PAGE_SIZE))
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#define ADDR_TO_PDE_OFFSET(v) ((((ULONG)(v)) / (1024 * PAGE_SIZE)))
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#define ADDR_TO_PTE_OFFSET(v) ((((ULONG)(v)) % (1024 * PAGE_SIZE)) / PAGE_SIZE)
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#define MiGetPdeOffset ADDR_TO_PDE_OFFSET
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/* Easy accessing PFN in PTE */
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#define PFN_FROM_PTE(v) ((v)->u.Hard.PageFrameNumber)
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#define MI_MAKE_LOCAL_PAGE(x) ((x)->u.Hard.Global = 0)
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#define MI_MAKE_DIRTY_PAGE(x) ((x)->u.Hard.Dirty = 1)
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#define MI_PAGE_DISABLE_CACHE(x) ((x)->u.Hard.CacheDisable = 1)
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#define MI_PAGE_WRITE_THROUGH(x) ((x)->u.Hard.WriteThrough = 1)
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#define MI_PAGE_WRITE_COMBINED(x) ((x)->u.Hard.WriteThrough = 0)
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#if !defined(CONFIG_SMP)
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#define MI_IS_PAGE_WRITEABLE(x) ((x)->u.Hard.Write == 1)
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#else
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#define MI_IS_PAGE_WRITEABLE(x) ((x)->u.Hard.Writable == 1)
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#endif
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#define MI_IS_PAGE_COPY_ON_WRITE(x)((x)->u.Hard.CopyOnWrite == 1)
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#define MI_IS_PAGE_DIRTY(x) ((x)->u.Hard.Dirty == 1)
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#define MI_MAKE_OWNER_PAGE(x) ((x)->u.Hard.Owner = 1)
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#if !defined(CONFIG_SMP)
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#define MI_MAKE_WRITE_PAGE(x) ((x)->u.Hard.Write = 1)
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#else
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#define MI_MAKE_WRITE_PAGE(x) ((x)->u.Hard.Writable = 1)
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#endif
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#define PAGE_TO_SECTION_PAGE_DIRECTORY_OFFSET(x) \
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((x) / (4*1024*1024))
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#define PAGE_TO_SECTION_PAGE_TABLE_OFFSET(x) \
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((((x)) % (4*1024*1024)) / (4*1024))
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#define NR_SECTION_PAGE_TABLES 1024
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#define NR_SECTION_PAGE_ENTRIES 1024
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#define TEB_BASE 0x7FFDE000
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#define MI_HYPERSPACE_PTES (256 - 1)
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#define MI_ZERO_PTES (32)
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#define MI_MAPPING_RANGE_START (ULONG)HYPER_SPACE
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#define MI_MAPPING_RANGE_END (MI_MAPPING_RANGE_START + \
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MI_HYPERSPACE_PTES * PAGE_SIZE)
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#define MI_ZERO_PTE (PMMPTE)(MI_MAPPING_RANGE_END + \
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PAGE_SIZE)
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/* On x86, these two are the same */
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#define MMPDE MMPTE
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#define PMMPDE PMMPTE
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/*
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* FIXME - different architectures have different cache line sizes...
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*/
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#define MM_CACHE_LINE_SIZE 32
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