mirror of
https://github.com/reactos/reactos.git
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189 lines
3.3 KiB
C
189 lines
3.3 KiB
C
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.macro TEXTAREA
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.section .text, "rx"
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.align 2
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.endm
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.macro NESTED_ENTRY Name
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.global &Name
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.align 2
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.func &Name
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&Name:
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.endm
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.macro PROLOG_END Name
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prolog_&Name:
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.endm
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.macro ENTRY_END Name
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end_&Name:
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.endfunc
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.endm
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.macro TRAP_PROLOG Abort
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//
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// Fixup lr
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//
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.if \Abort
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sub lr, lr, #8
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.else
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sub lr, lr, #4
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.endif
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//
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// Save the bottom 4 registers
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//
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stmdb sp, {r0-r3}
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//
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// Save the abort lr, sp, spsr, cpsr
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//
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mov r0, lr
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mov r1, sp
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mrs r2, cpsr
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mrs r3, spsr
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//
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// Switch to SVC mode
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//
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bic r2, r2, #CPSR_MODES
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orr r2, r2, #CPSR_SVC_MODE
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msr cpsr_c, r2
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//
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// Save the SVC sp before we modify it
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//
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mov r2, sp
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//
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// Make space for the trap frame
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//
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sub sp, sp, #TrapFrameLength
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//
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// Save abt32 state
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//
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str r0, [sp, #TrPc]
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str lr, [sp, #TrSvcLr]
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str r2, [sp, #TrSvcSp]
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//
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// Restore the saved SPSR
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//
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msr spsr_all, r3
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//
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// Restore our 4 registers
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//
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ldmdb r1, {r0-r3}
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//
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// Build trap frame
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// FIXME: Change to stmdb later
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//
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str r0, [sp, #TrR0]
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str r1, [sp, #TrR1]
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str r2, [sp, #TrR2]
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str r3, [sp, #TrR3]
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str r4, [sp, #TrR4]
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str r5, [sp, #TrR5]
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str r6, [sp, #TrR6]
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str r7, [sp, #TrR7]
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str r8, [sp, #TrR8]
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str r9, [sp, #TrR9]
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str r10, [sp, #TrR10]
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str r11, [sp, #TrR11]
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str r12, [sp, #TrR12]
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mov r12, sp
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add r12, r12, #TrUserSp
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stm r12, {sp, lr}^
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mrs r0, spsr_all
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str r0, [sp, #TrSpsr]
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ldr r0, =0xBADB0D00
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str r0, [sp, #TrDbgArgMark]
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.endm
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.macro SYSCALL_PROLOG
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//
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// Make space for the trap frame
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//
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sub sp, sp, #TrapFrameLength
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//
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// Build trap frame
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// FIXME: Change to stmdb later
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//
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str r0, [sp, #TrR0]
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str r1, [sp, #TrR1]
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str r2, [sp, #TrR2]
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str r3, [sp, #TrR3]
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str r4, [sp, #TrR4]
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str r5, [sp, #TrR5]
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str r6, [sp, #TrR6]
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str r7, [sp, #TrR7]
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str r8, [sp, #TrR8]
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str r9, [sp, #TrR9]
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str r10, [sp, #TrR10]
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str r11, [sp, #TrR11]
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str r12, [sp, #TrR12]
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mov r12, sp
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add r12, r12, #TrUserSp
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stm r12, {sp, lr}^
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str sp, [sp, #TrSvcSp]
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str lr, [sp, #TrPc]
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mrs r0, spsr_all
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str r0, [sp, #TrSpsr]
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ldr r0, =0xBADB0D00
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str r0, [sp, #TrDbgArgMark]
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.endm
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.macro TRAP_EPILOG SystemCall
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//
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// ASSERT(TrapFrame->DbgArgMark == 0xBADB0D00)
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//
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ldr r0, [sp, #TrDbgArgMark]
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ldr r1, =0xBADB0D00
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cmp r0, r1
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bne 1f
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//
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// Get the SPSR and restore it
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//
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ldr r0, [sp, #TrSpsr]
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msr spsr_all, r0
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//
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// Restore the registers
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// FIXME: Use LDMIA later
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//
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mov r0, sp
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add r0, r0, #TrUserSp
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ldm r0, {sp, lr}^
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ldr r0, [sp, #TrR0]
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ldr r1, [sp, #TrR1]
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ldr r2, [sp, #TrR2]
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ldr r3, [sp, #TrR3]
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ldr r4, [sp, #TrR4]
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ldr r5, [sp, #TrR5]
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ldr r6, [sp, #TrR6]
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ldr r7, [sp, #TrR7]
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ldr r8, [sp, #TrR8]
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ldr r9, [sp, #TrR9]
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ldr r10, [sp, #TrR10]
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ldr r11, [sp, #TrR11]
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ldr r12, [sp, #TrR12]
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//
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// Restore program execution state
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//
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.if \SystemCall
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ldr lr, [sp, #TrPc]
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add sp, sp, #TrapFrameLength
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movs pc, lr
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.else
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add sp, sp, #TrSvcSp
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ldmia sp, {sp, lr, pc}^
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.endif
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1:
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b .
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.endm
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