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https://github.com/reactos/reactos.git
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193 lines
5.9 KiB
C
193 lines
5.9 KiB
C
/*
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* PROJECT: ReactOS Intel PRO/1000 Driver
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* LICENSE: GPL-2.0+ (https://spdx.org/licenses/GPL-2.0+)
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* PURPOSE: Intel PRO/1000 driver definitions
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* COPYRIGHT: Copyright 2018 Mark Jansen (mark.jansen@reactos.org)
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*/
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#pragma once
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#define IEEE_802_ADDR_LENGTH 6
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#define HW_VENDOR_INTEL 0x8086
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#define MAX_RESET_ATTEMPTS 10
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#define MAX_PHY_REG_ADDRESS 0x1F
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#define MAX_PHY_READ_ATTEMPTS 1800
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#define MAX_EEPROM_READ_ATTEMPTS 10000
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#define MAXIMUM_MULTICAST_ADDRESSES 16
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/* Ethernet frame header */
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typedef struct _ETH_HEADER {
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UCHAR Destination[IEEE_802_ADDR_LENGTH];
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UCHAR Source[IEEE_802_ADDR_LENGTH];
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USHORT PayloadType;
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} ETH_HEADER, *PETH_HEADER;
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#include <pshpack1.h>
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/* 3.2.3 Receive Descriptor Format */
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#define E1000_RDESC_STATUS_EOP (1 << 1) /* End of Packet */
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#define E1000_RDESC_STATUS_DD (1 << 0) /* Descriptor Done */
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typedef struct _E1000_RECEIVE_DESCRIPTOR
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{
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UINT64 Address;
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USHORT Length;
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USHORT Checksum;
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UCHAR Status;
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UCHAR Errors;
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USHORT Special;
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} E1000_RECEIVE_DESCRIPTOR, *PE1000_RECEIVE_DESCRIPTOR;
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/* 3.3.3 Legacy Transmit Descriptor Format */
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#define E1000_TDESC_CMD_RS (1 << 3) /* Report Status */
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#define E1000_TDESC_CMD_IFCS (1 << 1) /* Insert FCS */
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#define E1000_TDESC_CMD_EOP (1 << 0) /* End Of Packet */
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#define E1000_TDESC_STATUS_DD (1 << 0) /* Descriptor Done */
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typedef struct _E1000_TRANSMIT_DESCRIPTOR
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{
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UINT64 Address;
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USHORT Length;
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UCHAR ChecksumOffset;
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UCHAR Command;
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UCHAR Status;
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UCHAR ChecksumStartField;
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USHORT Special;
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} E1000_TRANSMIT_DESCRIPTOR, *PE1000_TRANSMIT_DESCRIPTOR;
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#include <poppack.h>
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C_ASSERT(sizeof(E1000_RECEIVE_DESCRIPTOR) == 16);
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C_ASSERT(sizeof(E1000_TRANSMIT_DESCRIPTOR) == 16);
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/* Valid Range: 80-256 for 82542 and 82543 gigabit ethernet controllers
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Valid Range: 80-4096 for 82544 and newer */
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#define NUM_TRANSMIT_DESCRIPTORS 128
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#define NUM_RECEIVE_DESCRIPTORS 128
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/* Registers */
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#define E1000_REG_CTRL 0x0000 /* Device Control Register, R/W */
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#define E1000_REG_STATUS 0x0008 /* Device Status Register, R */
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#define E1000_REG_EERD 0x0014 /* EEPROM Read Register, R/W */
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#define E1000_REG_MDIC 0x0020 /* MDI Control Register, R/W */
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#define E1000_REG_VET 0x0038 /* VLAN Ether Type, R/W */
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#define E1000_REG_ICR 0x00C0 /* Interrupt Cause Read, R/clr */
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#define E1000_REG_IMS 0x00D0 /* Interrupt Mask Set/Read Register, R/W */
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#define E1000_REG_IMC 0x00D8 /* Interrupt Mask Clear, W */
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#define E1000_REG_RCTL 0x0100 /* Receive Control Register, R/W */
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#define E1000_REG_TCTL 0x0400 /* Transmit Control Register, R/W */
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#define E1000_REG_TDBAL 0x3800 /* Transmit Descriptor Base Address Low, R/W */
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#define E1000_REG_TDBAH 0x3804 /* Transmit Descriptor Base Address High, R/W */
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#define E1000_REG_TDLEN 0x3808 /* Transmit Descriptor Length, R/W */
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#define E1000_REG_TDH 0x3810 /* Transmit Descriptor Head, R/W */
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#define E1000_REG_TDT 0x3818 /* Transmit Descriptor Tail, R/W */
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#define E1000_REG_RAL 0x5400 /* Receive Address Low, R/W */
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#define E1000_REG_RAH 0x5404 /* Receive Address High, R/W */
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/* E1000_REG_CTRL */
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#define E1000_CTRL_RST (1 << 26) /* Device Reset, Self clearing */
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/* E1000_REG_STATUS */
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#define E1000_STATUS_LU (1 << 0) /* Link Up Indication */
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#define E1000_STATUS_SPEEDSHIFT 6 /* Link speed setting */
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#define E1000_STATUS_SPEEDMASK (3 << E1000_STATUS_SPEEDSHIFT)
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/* E1000_REG_EERD */
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#define E1000_EERD_START (1 << 0) /* Start Read*/
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#define E1000_EERD_DONE (1 << 4) /* Read Done */
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#define E1000_EERD_ADDR_SHIFT 8
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#define E1000_EERD_DATA_SHIFT 16
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/* E1000_REG_MDIC */
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#define E1000_MDIC_REGADD_SHIFT 16 /* PHY Register Address */
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#define E1000_MDIC_PHYADD_SHIFT 21 /* PHY Address (1=Gigabit, 2=PCIe) */
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#define E1000_MDIC_PHYADD_GIGABIT 1
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#define E1000_MDIC_OP_READ (2 << 26) /* Opcode */
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#define E1000_MDIC_R (1 << 28) /* Ready Bit */
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#define E1000_MDIC_E (1 << 30) /* Error */
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/* E1000_REG_IMS */
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#define E1000_IMS_TXDW (1 << 0) /* Transmit Descriptor Written Back */
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#define E1000_IMS_LSC (1 << 2) /* Sets mask for Link Status Change */
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/* E1000_REG_RCTL */
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#define E1000_RCTL_EN (1 << 1) /* Receiver Enable */
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#define E1000_RCTL_SBP (1 << 2) /* Store Bad Packets */
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#define E1000_RCTL_UPE (1 << 3) /* Unicast Promiscuous Enabled */
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#define E1000_RCTL_MPE (1 << 4) /* Multicast Promiscuous Enabled */
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#define E1000_RCTL_BAM (1 << 15) /* Broadcast Accept Mode */
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#define E1000_RCTL_PMCF (1 << 23) /* Pass MAC Control Frames */
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#define E1000_RCTL_FILTER_BITS (E1000_RCTL_SBP | E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM | E1000_RCTL_PMCF)
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/* E1000_REG_TCTL */
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#define E1000_TCTL_EN (1 << 1) /* Transmit Enable */
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#define E1000_TCTL_PSP (1 << 3) /* Pad Short Packets */
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/* E1000_REG_RAH */
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#define E1000_RAH_AV (1 << 31) /* Address Valid */
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/* NVM */
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#define E1000_NVM_REG_CHECKSUM 0x03f
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#define NVM_MAGIC_SUM 0xBABA
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/* PHY (Read with MDIC) */
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#define E1000_PHY_STATUS 0x01
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#define E1000_PHY_SPECIFIC_STATUS 0x11
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/* E1000_PHY_STATUS */
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#define E1000_PS_LINK_STATUS (1 << 2)
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/* E1000_PHY_SPECIFIC_STATUS */
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#define E1000_PSS_SPEED_AND_DUPLEX (1 << 11) /* Speed and Duplex Resolved */
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#define E1000_PSS_SPEEDSHIFT 14
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#define E1000_PSS_SPEEDMASK (3 << E1000_PSS_SPEEDSHIFT)
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