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495 lines
14 KiB
C
495 lines
14 KiB
C
/*++
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Copyright (C) Microsoft Corporation, 1999 - 1999
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Module Name:
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ide.h
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Abstract:
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These are the structures and defines that are used in the
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PCI IDE mini drivers.
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Revision History:
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--*/
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#if !defined (___ide_h___)
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#define ___ide_h___
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#include "ideuser.h"
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#define MAX_IDE_DEVICE 2
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#define MAX_IDE_LINE 2
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#define MAX_IDE_CHANNEL 2
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//
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// Some miniports need this structure.
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// IdentifyData is passed to the miniport in
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// the XfermodeSelect structure
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//
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//
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// IDENTIFY data
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//
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#pragma pack (1)
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typedef struct _IDENTIFY_DATA {
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USHORT GeneralConfiguration; // 00 00
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USHORT NumCylinders; // 02 1
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USHORT Reserved1; // 04 2
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USHORT NumHeads; // 06 3
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USHORT UnformattedBytesPerTrack; // 08 4
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USHORT UnformattedBytesPerSector; // 0A 5
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USHORT NumSectorsPerTrack; // 0C 6
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USHORT VendorUnique1[3]; // 0E 7-9
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UCHAR SerialNumber[20]; // 14 10-19
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USHORT BufferType; // 28 20
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USHORT BufferSectorSize; // 2A 21
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USHORT NumberOfEccBytes; // 2C 22
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UCHAR FirmwareRevision[8]; // 2E 23-26
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UCHAR ModelNumber[40]; // 36 27-46
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UCHAR MaximumBlockTransfer; // 5E 47
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UCHAR VendorUnique2; // 5F
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USHORT DoubleWordIo; // 60 48
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USHORT Capabilities; // 62 49
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USHORT Reserved2; // 64 50
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UCHAR VendorUnique3; // 66 51
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UCHAR PioCycleTimingMode; // 67
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UCHAR VendorUnique4; // 68 52
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UCHAR DmaCycleTimingMode; // 69
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USHORT TranslationFieldsValid:3; // 6A 53
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USHORT Reserved3:13;
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USHORT NumberOfCurrentCylinders; // 6C 54
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USHORT NumberOfCurrentHeads; // 6E 55
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USHORT CurrentSectorsPerTrack; // 70 56
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ULONG CurrentSectorCapacity; // 72 57-58
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USHORT CurrentMultiSectorSetting; // 59
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ULONG UserAddressableSectors; // 60-61
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USHORT SingleWordDMASupport : 8; // 62
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USHORT SingleWordDMAActive : 8;
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USHORT MultiWordDMASupport : 8; // 63
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USHORT MultiWordDMAActive : 8;
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USHORT AdvancedPIOModes : 8; // 64
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USHORT Reserved4 : 8;
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USHORT MinimumMWXferCycleTime; // 65
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USHORT RecommendedMWXferCycleTime; // 66
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USHORT MinimumPIOCycleTime; // 67
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USHORT MinimumPIOCycleTimeIORDY; // 68
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USHORT Reserved5[11]; // 69-79
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USHORT MajorRevision; // 80
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USHORT MinorRevision; // 81
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USHORT Reserved6; // 82
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USHORT CommandSetSupport; // 83
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USHORT Reserved6a[2]; // 84-85
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USHORT CommandSetActive; // 86
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USHORT Reserved6b; // 87
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USHORT UltraDMASupport : 8; // 88
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USHORT UltraDMAActive : 8; //
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USHORT Reserved7[11]; // 89-99
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ULONG Max48BitLBA[2]; // 100-103
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USHORT Reserved7a[22]; // 104-125
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USHORT LastLun:3; // 126
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USHORT Reserved8:13;
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USHORT MediaStatusNotification:2; // 127
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USHORT Reserved9:6;
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USHORT DeviceWriteProtect:1;
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USHORT Reserved10:7;
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USHORT Reserved11[128]; // 128-255
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} IDENTIFY_DATA, *PIDENTIFY_DATA;
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//
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// Identify data without the Reserved4.
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//
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//typedef struct _IDENTIFY_DATA2 {
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// USHORT GeneralConfiguration; // 00 00
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// USHORT NumCylinders; // 02 1
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// USHORT Reserved1; // 04 2
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// USHORT NumHeads; // 06 3
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// USHORT UnformattedBytesPerTrack; // 08 4
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// USHORT UnformattedBytesPerSector; // 0A 5
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// USHORT NumSectorsPerTrack; // 0C 6
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// USHORT VendorUnique1[3]; // 0E 7-9
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// UCHAR SerialNumber[20]; // 14 10-19
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// USHORT BufferType; // 28 20
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// USHORT BufferSectorSize; // 2A 21
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// USHORT NumberOfEccBytes; // 2C 22
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// UCHAR FirmwareRevision[8]; // 2E 23-26
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// UCHAR ModelNumber[40]; // 36 27-46
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// UCHAR MaximumBlockTransfer; // 5E 47
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// UCHAR VendorUnique2; // 5F
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// USHORT DoubleWordIo; // 60 48
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// USHORT Capabilities; // 62 49
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// USHORT Reserved2; // 64 50
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// UCHAR VendorUnique3; // 66 51
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// UCHAR PioCycleTimingMode; // 67
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// UCHAR VendorUnique4; // 68 52
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// UCHAR DmaCycleTimingMode; // 69
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// USHORT TranslationFieldsValid:3; // 6A 53
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// USHORT Reserved3:13;
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// USHORT NumberOfCurrentCylinders; // 6C 54
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// USHORT NumberOfCurrentHeads; // 6E 55
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// USHORT CurrentSectorsPerTrack; // 70 56
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// ULONG CurrentSectorCapacity; // 72 57-58
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// USHORT CurrentMultiSectorSetting; // 59
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// ULONG UserAddressableSectors; // 60-61
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// USHORT SingleWordDMASupport : 8; // 62
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// USHORT SingleWordDMAActive : 8;
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// USHORT MultiWordDMASupport : 8; // 63
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// USHORT MultiWordDMAActive : 8;
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// USHORT AdvancedPIOModes : 8; // 64
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// USHORT Reserved4 : 8;
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// USHORT MinimumMWXferCycleTime; // 65
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// USHORT RecommendedMWXferCycleTime; // 66
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// USHORT MinimumPIOCycleTime; // 67
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// USHORT MinimumPIOCycleTimeIORDY; // 68
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// USHORT Reserved5[11]; // 69-79
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// USHORT MajorRevision; // 80
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// USHORT MinorRevision; // 81
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// USHORT Reserved6[6]; // 82-87
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// USHORT UltraDMASupport : 8; // 88
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// USHORT UltraDMAActive : 8; //
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// USHORT Reserved7[37]; // 89-125
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// USHORT LastLun:3; // 126
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// USHORT Reserved8:13;
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// USHORT MediaStatusNotification:2; // 127
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// USHORT Reserved9:6;
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// USHORT DeviceWriteProtect:1;
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// USHORT Reserved10:7;
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//} IDENTIFY_DATA2, *PIDENTIFY_DATA2;
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#pragma pack ()
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#define IDENTIFY_DATA_SIZE sizeof(IDENTIFY_DATA)
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//
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// The structure is passed to pci ide mini driver
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// TransferModeSelect callback for selecting
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// proper transfer mode the the devices connected
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// to the given IDE channel
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//
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typedef struct _PCIIDE_TRANSFER_MODE_SELECT {
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//
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// Input Parameters
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//
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//
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// IDE Channel Number. 0 or 1
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//
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ULONG Channel;
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//
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// Indicate whether devices are present
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//
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BOOLEAN DevicePresent[MAX_IDE_DEVICE * MAX_IDE_LINE];
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//
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// Indicate whether devices are ATA harddisk
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//
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BOOLEAN FixedDisk[MAX_IDE_DEVICE * MAX_IDE_LINE];
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//
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// Indicate whether devices support IO Ready Line
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//
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BOOLEAN IoReadySupported[MAX_IDE_DEVICE * MAX_IDE_LINE];
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//
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// Indicate the data transfer modes devices support
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//
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ULONG DeviceTransferModeSupported[MAX_IDE_DEVICE * MAX_IDE_LINE];
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//
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// Indicate devices' best timings for PIO, single word DMA,
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// multiword DMA, and Ultra DMA modes
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//
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ULONG BestPioCycleTime[MAX_IDE_DEVICE * MAX_IDE_LINE];
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ULONG BestSwDmaCycleTime[MAX_IDE_DEVICE * MAX_IDE_LINE];
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ULONG BestMwDmaCycleTime[MAX_IDE_DEVICE * MAX_IDE_LINE];
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ULONG BestUDmaCycleTime[MAX_IDE_DEVICE * MAX_IDE_LINE];
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//
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// Indicate devices' current data transfer modes
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//
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ULONG DeviceTransferModeCurrent[MAX_IDE_DEVICE * MAX_IDE_LINE];
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//
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// The user's choice. This will allow pciidex to
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// default to a transfer mode indicated by the mini driver
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//
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ULONG UserChoiceTransferMode[MAX_IDE_DEVICE * MAX_IDE_LINE];
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//
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// This enables UDMA66 on the intel chipsets
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//
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ULONG EnableUDMA66;
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//
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//Some miniports need this
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// The miniport will save this data in their deviceExtension
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//
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IDENTIFY_DATA IdentifyData[MAX_IDE_DEVICE];
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//
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// Output Parameters
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//
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//
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// Indicate devices' data transfer modes chosen by
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// the pcii ide mini drive
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//
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ULONG DeviceTransferModeSelected[MAX_IDE_DEVICE * MAX_IDE_LINE];
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//
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// Transfermode timings
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//
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PULONG TransferModeTimingTable;
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ULONG TransferModeTableLength;
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} PCIIDE_TRANSFER_MODE_SELECT, *PPCIIDE_TRANSFER_MODE_SELECT;
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//
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// possible ide channel state
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//
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typedef enum {
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ChannelDisabled = 0,
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ChannelEnabled,
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ChannelStateUnknown
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} IDE_CHANNEL_STATE;
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//
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// Prototype for different PCI IDE mini driver
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// callbacks
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//
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typedef IDE_CHANNEL_STATE
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(*PCIIDE_CHANNEL_ENABLED) (
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IN PVOID DeviceExtension,
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IN ULONG Channel
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);
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typedef BOOLEAN
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(*PCIIDE_SYNC_ACCESS_REQUIRED) (
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IN PVOID DeviceExtension
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);
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typedef NTSTATUS
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(*PCIIDE_TRANSFER_MODE_SELECT_FUNC) (
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IN PVOID DeviceExtension,
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IN OUT PPCIIDE_TRANSFER_MODE_SELECT TransferModeSelect
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);
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typedef ULONG
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(*PCIIDE_USEDMA_FUNC)(
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IN PVOID deviceExtension,
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IN PVOID cdbCmd,
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IN UCHAR targetID
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);
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typedef NTSTATUS
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(*PCIIDE_UDMA_MODES_SUPPORTED) (
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IDENTIFY_DATA IdentifyData,
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PULONG BestXferMode,
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PULONG CurrentMode
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);
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//
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// This structure is for the PCI IDE mini driver to
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// return its properties
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//
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typedef struct _IDE_CONTROLLER_PROPERTIES {
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//
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// sizeof (IDE_CONTROLLER_PROPERTIES)
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//
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ULONG Size;
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//
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// Indicate the amount of memory PCI IDE mini driver
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// needs for its private data
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//
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ULONG ExtensionSize;
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//
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// Indicate all the data transfer modes the PCI IDE
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// controller supports
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//
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ULONG SupportedTransferMode[MAX_IDE_CHANNEL][MAX_IDE_DEVICE];
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//
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// callback to query whether a IDE channel is enabled
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//
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PCIIDE_CHANNEL_ENABLED PciIdeChannelEnabled;
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//
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// callback to query whether both IDE channels requires
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// synchronized access. (one channel at a time)
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//
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PCIIDE_SYNC_ACCESS_REQUIRED PciIdeSyncAccessRequired;
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//
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// callback to select proper transfer modes for the
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// given devices
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//
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PCIIDE_TRANSFER_MODE_SELECT_FUNC PciIdeTransferModeSelect;
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//
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// at the end of a ATA data transfer, ignores busmaster
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// status active bit. Normally, it should be FALSE
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//
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BOOLEAN IgnoreActiveBitForAtaDevice;
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//
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// always clear the busmaster interrupt on every interrupt
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// generated by the device. Normnally, it should be FALSE
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//
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BOOLEAN AlwaysClearBusMasterInterrupt;
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//
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// callback to determine whether DMA should be used or not
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// called for every IO
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//
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PCIIDE_USEDMA_FUNC PciIdeUseDma;
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//
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// if the miniport needs a different alignment
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//
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ULONG AlignmentRequirement;
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ULONG DefaultPIO;
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//
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// retrieves the supported udma modes from the Identify data
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//
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PCIIDE_UDMA_MODES_SUPPORTED PciIdeUdmaModesSupported;
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} IDE_CONTROLLER_PROPERTIES, *PIDE_CONTROLLER_PROPERTIES;
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//
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// callback to query PCI IDE controller properties
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//
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typedef
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NTSTATUS (*PCONTROLLER_PROPERTIES) (
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IN PVOID DeviceExtension,
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IN PIDE_CONTROLLER_PROPERTIES ControllerProperties
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);
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//
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// To initailize PCI IDE mini driver
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//
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NTSTATUS
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PciIdeXInitialize(
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IN PDRIVER_OBJECT DriverObject,
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IN PUNICODE_STRING RegistryPath,
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IN PCONTROLLER_PROPERTIES PciIdeGetControllerProperties,
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IN ULONG ExtensionSize
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);
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//
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// To query PCI IDE config space data
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//
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NTSTATUS
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PciIdeXGetBusData(
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IN PVOID DeviceExtension,
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IN PVOID Buffer,
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IN ULONG ConfigDataOffset,
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IN ULONG BufferLength
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);
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//
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// To save PCI IDE config space data
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//
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NTSTATUS
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PciIdeXSetBusData(
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IN PVOID DeviceExtension,
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IN PVOID Buffer,
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IN PVOID DataMask,
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IN ULONG ConfigDataOffset,
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IN ULONG BufferLength
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);
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#pragma pack(1)
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typedef struct _PCIIDE_CONFIG_HEADER {
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USHORT VendorID; // (ro)
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USHORT DeviceID; // (ro)
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//
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// Command
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//
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union {
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struct {
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USHORT IoAccessEnable:1; // Device control
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USHORT MemAccessEnable:1;
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USHORT MasterEnable:1;
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USHORT SpecialCycle:1;
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USHORT MemWriteInvalidateEnable:1;
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USHORT VgaPaletteSnoopEnable:1;
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USHORT ParityErrorResponse:1;
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USHORT WaitCycleEnable:1;
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USHORT SystemErrorEnable:1;
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USHORT FastBackToBackEnable:1;
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USHORT CommandReserved:6;
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} b;
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USHORT w;
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} Command;
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USHORT Status;
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UCHAR RevisionID; // (ro)
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//
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// Program Interface
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//
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UCHAR Chan0OpMode:1;
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UCHAR Chan0Programmable:1;
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UCHAR Chan1OpMode:1;
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UCHAR Chan1Programmable:1;
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UCHAR ProgIfReserved:3;
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UCHAR MasterIde:1;
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UCHAR SubClass; // (ro)
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UCHAR BaseClass; // (ro)
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UCHAR CacheLineSize; // (ro+)
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UCHAR LatencyTimer; // (ro+)
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UCHAR HeaderType; // (ro)
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UCHAR BIST; // Built in self test
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struct _PCI_HEADER_TYPE_0 type0;
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} PCIIDE_CONFIG_HEADER, *PPCIIDE_CONFIG_HEADER;
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#pragma pack()
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//
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// Debug Print
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//
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#if DBG
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VOID
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PciIdeXDebugPrint(
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ULONG DebugPrintLevel,
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PCCHAR DebugMessage,
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...
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);
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#define PciIdeXDebugPrint(x) PciIdeXDebugPrint x
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#else
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#define PciIdeXDebugPrint(x)
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#endif // DBG
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#endif // ___ide_h___
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