mirror of
https://github.com/reactos/reactos.git
synced 2025-08-06 15:43:19 +00:00
e4007ae73a
- Move NtFlushInstructionCache from sysinfo.c to virtual.c where it fits better. Likewise, move it from kefuncs to mmfuncs in NDK, and fix function arguments (ULONG -> SIZE_T). - Re-enable TRAP_DEBUG, adding back critical checks in the trap code. Checks can be improved but it is better than potentially silently messing up system state. - Move remaining RtlPrefetchMemoryNonTemporal code into kernel. Stubbed for non-x86. - By Hermes suggestion, override ASSERT to NT_ASSERT only for MSVC builds as that is where the main benefit is. svn path=/trunk/; revision=68907
368 lines
10 KiB
C
368 lines
10 KiB
C
#ifndef __NTOSKRNL_INCLUDE_INTERNAL_AMD64_KE_H
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#define __NTOSKRNL_INCLUDE_INTERNAL_AMD64_KE_H
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#define X86_EFLAGS_TF 0x00000100 /* Trap flag */
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#define X86_EFLAGS_IF 0x00000200 /* Interrupt Enable flag */
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#define X86_EFLAGS_IOPL 0x00003000 /* I/O Privilege Level bits */
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#define X86_EFLAGS_NT 0x00004000 /* Nested Task flag */
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#define X86_EFLAGS_RF 0x00010000 /* Resume flag */
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#define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */
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#define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */
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#define X86_CR0_PE 0x00000001 /* enable Protected Mode */
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#define X86_CR0_NE 0x00000020 /* enable native FPU error reporting */
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#define X86_CR0_TS 0x00000008 /* enable exception on FPU instruction for task switch */
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#define X86_CR0_EM 0x00000004 /* enable FPU emulation (disable FPU) */
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#define X86_CR0_MP 0x00000002 /* enable FPU monitoring */
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#define X86_CR0_WP 0x00010000 /* enable Write Protect (copy on write) */
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#define X86_CR0_PG 0x80000000 /* enable Paging */
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#define X86_CR4_PAE 0x00000020 /* enable physical address extensions */
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#define X86_CR4_PGE 0x00000080 /* enable global pages */
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#define X86_CR4_OSFXSR 0x00000200 /* enable FXSAVE/FXRSTOR instructions */
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#define X86_CR4_OSXMMEXCPT 0x00000400 /* enable #XF exception */
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#define X86_FEATURE_VME 0x00000002 /* Virtual 8086 Extensions are present */
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#define X86_FEATURE_TSC 0x00000010 /* time stamp counters are present */
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#define X86_FEATURE_PAE 0x00000040 /* physical address extension is present */
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#define X86_FEATURE_CX8 0x00000100 /* CMPXCHG8B instruction present */
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#define X86_FEATURE_SYSCALL 0x00000800 /* SYSCALL/SYSRET support present */
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#define X86_FEATURE_PGE 0x00002000 /* Page Global Enable */
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#define X86_FEATURE_MMX 0x00800000 /* MMX extension present */
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#define X86_FEATURE_FXSR 0x01000000 /* FXSAVE/FXRSTOR instructions present */
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#define X86_FEATURE_SSE 0x02000000 /* SSE extension present */
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#define X86_FEATURE_SSE2 0x04000000 /* SSE2 extension present */
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#define X86_FEATURE_HT 0x10000000 /* Hyper-Threading present */
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#define X86_EXT_FEATURE_SSE3 0x00000001 /* SSE3 extension present */
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#define X86_EXT_FEATURE_3DNOW 0x40000000 /* 3DNOW! extension present */
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#define FRAME_EDITED 0xFFF8
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#define X86_MSR_GSBASE 0xC0000101
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#define X86_MSR_KERNEL_GSBASE 0xC0000102
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#define X86_MSR_EFER 0xC0000080
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#define X86_MSR_STAR 0xC0000081
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#define X86_MSR_LSTAR 0xC0000082
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#define X86_MSR_CSTAR 0xC0000083
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#define X86_MSR_SFMASK 0xC0000084
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#define EFER_SCE 0x01
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#define EFER_LME 0x10
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#define EFER_LMA 0x40
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#define EFER_NXE 0x80
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#define EFER_SVME 0x100
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#define EFER_FFXSR 0x400
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#define AMD64_TSS 9
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#define APIC_EOI_REGISTER 0xFFFFFFFFFFFE00B0ULL
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#ifndef __ASM__
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#include "intrin_i.h"
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typedef struct _KIDT_INIT
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{
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UCHAR InterruptId;
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UCHAR Dpl;
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UCHAR IstIndex;
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PVOID ServiceRoutine;
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} KIDT_INIT, *PKIDT_INIT;
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#include <pshpack1.h>
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typedef struct _KI_INTERRUPT_DISPATCH_ENTRY
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{
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UCHAR _Op_nop;
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UCHAR _Op_push;
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UCHAR _Vector;
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UCHAR _Op_jmp;
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ULONG RelativeAddress;
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} KI_INTERRUPT_DISPATCH_ENTRY, *PKI_INTERRUPT_DISPATCH_ENTRY;
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#include <poppack.h>
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extern ULONG KeI386NpxPresent;
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extern ULONG KeI386XMMIPresent;
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extern ULONG KeI386FxsrPresent;
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extern ULONG KeI386CpuType;
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extern ULONG KeI386CpuStep;
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//
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// INT3 is 1 byte long
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//
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#define KD_BREAKPOINT_TYPE UCHAR
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#define KD_BREAKPOINT_SIZE sizeof(UCHAR)
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#define KD_BREAKPOINT_VALUE 0xCC
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//
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// Macros for getting and setting special purpose registers in portable code
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//
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#define KeGetContextPc(Context) \
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((Context)->Rip)
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#define KeSetContextPc(Context, ProgramCounter) \
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((Context)->Rip = (ProgramCounter))
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#define KeGetTrapFramePc(TrapFrame) \
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((TrapFrame)->Rip)
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#define KiGetLinkedTrapFrame(x) \
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(PKTRAP_FRAME)((x)->TrapFrame)
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#define KeGetContextReturnRegister(Context) \
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((Context)->Rax)
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#define KeSetContextReturnRegister(Context, ReturnValue) \
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((Context)->Rax = (ReturnValue))
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//
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// Macro to get trap and exception frame from a thread stack
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//
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#define KeGetTrapFrame(Thread) \
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(PKTRAP_FRAME)((ULONG_PTR)((Thread)->InitialStack) - \
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sizeof(KTRAP_FRAME))
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//
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// Macro to get context switches from the PRCB
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// All architectures but x86 have it in the PRCB's KeContextSwitches
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//
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#define KeGetContextSwitches(Prcb) \
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(Prcb->KeContextSwitches)
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//
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// Macro to get the second level cache size field name which differs between
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// CISC and RISC architectures, as the former has unified I/D cache
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//
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#define KiGetSecondLevelDCacheSize() ((PKIPCR)KeGetPcr())->SecondLevelCacheSize
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#define KeGetExceptionFrame(Thread) \
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(PKEXCEPTION_FRAME)((ULONG_PTR)KeGetTrapFrame(Thread) - \
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sizeof(KEXCEPTION_FRAME))
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//
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// Returns the Interrupt State from a Trap Frame.
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// ON = TRUE, OFF = FALSE
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//
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#define KeGetTrapFrameInterruptState(TrapFrame) \
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BooleanFlagOn((TrapFrame)->EFlags, EFLAGS_INTERRUPT_MASK)
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/* Diable interrupts and return whether they were enabled before */
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FORCEINLINE
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BOOLEAN
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KeDisableInterrupts(VOID)
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{
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ULONG_PTR Flags;
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/* Get EFLAGS and check if the interrupt bit is set */
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Flags = __readeflags();
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/* Disable interrupts */
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_disable();
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return (Flags & EFLAGS_INTERRUPT_MASK) ? TRUE : FALSE;
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}
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/* Restore previous interrupt state */
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FORCEINLINE
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VOID
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KeRestoreInterrupts(BOOLEAN WereEnabled)
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{
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if (WereEnabled) _enable();
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}
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//
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// Invalidates the TLB entry for a specified address
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//
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FORCEINLINE
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VOID
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KeInvalidateTlbEntry(IN PVOID Address)
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{
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/* Invalidate the TLB entry for this address */
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__invlpg(Address);
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}
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FORCEINLINE
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VOID
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KeFlushProcessTb(VOID)
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{
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/* Flush the TLB by resetting CR3 */
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__writecr3(__readcr3());
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}
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FORCEINLINE
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VOID
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KeSweepICache(IN PVOID BaseAddress,
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IN SIZE_T FlushSize)
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{
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//
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// Always sweep the whole cache
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//
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UNREFERENCED_PARAMETER(BaseAddress);
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UNREFERENCED_PARAMETER(FlushSize);
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__wbinvd();
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}
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FORCEINLINE
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VOID
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KiRundownThread(IN PKTHREAD Thread)
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{
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#ifndef CONFIG_SMP
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DbgPrint("KiRundownThread is unimplemented\n");
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#else
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/* Nothing to do */
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#endif
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}
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/* Registers an interrupt handler with an IDT vector */
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FORCEINLINE
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VOID
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KeRegisterInterruptHandler(IN ULONG Vector,
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IN PVOID Handler)
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{
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UCHAR Entry;
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PKIDTENTRY64 Idt;
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/* Get the entry from the HAL */
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Entry = HalVectorToIDTEntry(Vector);
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/* Now set the data */
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Idt = &KeGetPcr()->IdtBase[Entry];
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Idt->OffsetLow = (ULONG_PTR)Handler & 0xffff;
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Idt->OffsetMiddle = ((ULONG_PTR)Handler >> 16) & 0xffff;
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Idt->OffsetHigh = (ULONG_PTR)Handler >> 32;
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Idt->Selector = KGDT64_R0_CODE;
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Idt->IstIndex = 0;
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Idt->Type = 0x0e;
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Idt->Dpl = 0;
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Idt->Present = 1;
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Idt->Reserved0 = 0;
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Idt->Reserved1 = 0;
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}
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/* Returns the registered interrupt handler for a given IDT vector */
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FORCEINLINE
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PVOID
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KeQueryInterruptHandler(IN ULONG Vector)
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{
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UCHAR Entry;
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PKIDTENTRY64 Idt;
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/* Get the entry from the HAL */
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Entry = HalVectorToIDTEntry(Vector);
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/* Get the IDT entry */
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Idt = &KeGetPcr()->IdtBase[Entry];
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/* Return the address */
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return (PVOID)((ULONG64)Idt->OffsetHigh << 32 |
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(ULONG64)Idt->OffsetMiddle << 16 |
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(ULONG64)Idt->OffsetLow);
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}
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VOID
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FORCEINLINE
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KiSendEOI()
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{
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/* Write 0 to the apic EOI register */
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*((volatile ULONG*)APIC_EOI_REGISTER) = 0;
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}
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VOID
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FORCEINLINE
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KiEndInterrupt(IN KIRQL Irql,
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IN PKTRAP_FRAME TrapFrame)
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{
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/* Make sure this is from the clock handler */
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ASSERT(TrapFrame->ErrorCode == 0xc10c4);
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//KeLowerIrql(Irql);
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}
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BOOLEAN
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FORCEINLINE
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KiUserTrap(IN PKTRAP_FRAME TrapFrame)
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{
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/* Anything else but Ring 0 is Ring 3 */
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return !!(TrapFrame->SegCs & MODE_MASK);
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}
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#define Ki386PerfEnd()
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struct _KPCR;
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//VOID KiInitializeTss(IN PKTSS Tss, IN UINT64 Stack);
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VOID KiSwitchToBootStack(IN ULONG_PTR InitialStack);
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VOID KiDivideErrorFault(VOID);
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VOID KiDebugTrapOrFault(VOID);
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VOID KiNmiInterrupt(VOID);
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VOID KiBreakpointTrap(VOID);
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VOID KiOverflowTrap(VOID);
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VOID KiBoundFault(VOID);
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VOID KiInvalidOpcodeFault(VOID);
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VOID KiNpxNotAvailableFault(VOID);
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VOID KiDoubleFaultAbort(VOID);
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VOID KiNpxSegmentOverrunAbort(VOID);
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VOID KiInvalidTssFault(VOID);
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VOID KiSegmentNotPresentFault(VOID);
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VOID KiStackFault(VOID);
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VOID KiGeneralProtectionFault(VOID);
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VOID KiPageFault(VOID);
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VOID KiFloatingErrorFault(VOID);
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VOID KiAlignmentFault(VOID);
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VOID KiMcheckAbort(VOID);
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VOID KiXmmException(VOID);
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VOID KiApcInterrupt(VOID);
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VOID KiRaiseAssertion(VOID);
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VOID KiDebugServiceTrap(VOID);
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VOID KiDpcInterrupt(VOID);
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VOID KiIpiInterrupt(VOID);
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VOID KiGdtPrepareForApplicationProcessorInit(ULONG Id);
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VOID Ki386InitializeLdt(VOID);
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VOID Ki386SetProcessorFeatures(VOID);
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VOID KiGetCacheInformation(VOID);
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VOID KiSetProcessorType(VOID);
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ULONG KiGetFeatureBits(VOID);
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VOID KiInitializeCpuFeatures(VOID);
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ULONG KeAllocateGdtSelector(ULONG Desc[2]);
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VOID KeFreeGdtSelector(ULONG Entry);
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VOID NtEarlyInitVdm(VOID);
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VOID KeApplicationProcessorInitDispatcher(VOID);
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VOID KeCreateApplicationProcessorIdleThread(ULONG Id);
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VOID
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Ke386InitThreadWithContext(PKTHREAD Thread,
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PKSYSTEM_ROUTINE SystemRoutine,
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PKSTART_ROUTINE StartRoutine,
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PVOID StartContext,
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PCONTEXT Context);
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#define KeArchInitThreadWithContext(Thread,SystemRoutine,StartRoutine,StartContext,Context) \
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Ke386InitThreadWithContext(Thread,SystemRoutine,StartRoutine,StartContext,Context)
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#ifdef _NTOSKRNL_ /* FIXME: Move flags above to NDK instead of here */
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VOID
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KiThreadStartup(PKSYSTEM_ROUTINE SystemRoutine,
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PKSTART_ROUTINE StartRoutine,
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PVOID StartContext,
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BOOLEAN UserThread,
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KTRAP_FRAME TrapFrame);
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#endif
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#endif /* __ASM__ */
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// HACK
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extern NTKERNELAPI volatile KSYSTEM_TIME KeTickCount;
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// win64 uses DMA macros, this one is not defined
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NTHALAPI
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NTSTATUS
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NTAPI
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HalAllocateAdapterChannel(
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IN PADAPTER_OBJECT AdapterObject,
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IN PWAIT_CONTEXT_BLOCK Wcb,
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IN ULONG NumberOfMapRegisters,
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IN PDRIVER_CONTROL ExecutionRoutine);
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#endif /* __NTOSKRNL_INCLUDE_INTERNAL_AMD64_KE_H */
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/* EOF */
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