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1134 lines
26 KiB
C
1134 lines
26 KiB
C
/*
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* ReactOS kernel
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* Copyright (C) 2004, 2005 ReactOS Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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/*
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* COPYRIGHT: See COPYING in the top level directory
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* PROJECT: ReactOS kernel
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* FILE: hal/halx86/mp/apic.c
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* PURPOSE:
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* PROGRAMMER:
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*/
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/* INCLUDE ***********************************************************************/
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#include <hal.h>
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#include <halfuncs.h> /* Not in PCH because only used for MP HAL */
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#include <rtlfuncs.h> /* Not in PCH because only used for MP HAL */
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#define NDEBUG
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#include <debug.h>
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/* GLOBALS ***********************************************************************/
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ULONG CPUCount; /* Total number of CPUs */
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ULONG BootCPU; /* Bootstrap processor */
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ULONG OnlineCPUs; /* Bitmask of online CPUs */
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CPU_INFO CPUMap[MAX_CPU]; /* Map of all CPUs in the system */
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#ifdef CONFIG_SMP
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PULONG BIOSBase; /* Virtual address of BIOS data segment */
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PULONG CommonBase; /* Virtual address of common area */
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#endif
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PULONG APICBase = (PULONG)APIC_DEFAULT_BASE; /* Virtual address of local APIC */
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ULONG APICMode; /* APIC mode at startup */
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/* For debugging */
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ULONG lastregr[MAX_CPU];
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ULONG lastvalr[MAX_CPU];
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ULONG lastregw[MAX_CPU];
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ULONG lastvalw[MAX_CPU];
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#ifdef CONFIG_SMP
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#include <pshpack1.h>
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typedef struct _COMMON_AREA_INFO
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{
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ULONG Stack; /* Location of AP stack */
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ULONG PageDirectory; /* Page directory for an AP */
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ULONG NtProcessStartup; /* Kernel entry point for an AP */
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ULONG PaeModeEnabled; /* PAE mode is enabled */
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ULONG Debug[16]; /* For debugging */
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} COMMON_AREA_INFO, *PCOMMON_AREA_INFO;
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#include <poppack.h>
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#endif
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extern CHAR *APstart, *APend;
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#define BIOS_AREA 0x0
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#define COMMON_AREA 0x2000
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#define HZ (100)
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#define APIC_DIVISOR (16)
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#define CMOS_READ(address) { \
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WRITE_PORT_UCHAR((PUCHAR)0x70, address)); \
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READ_PORT_UCHAR((PUCHAR)0x71)); \
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}
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#define CMOS_WRITE(address, value) { \
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WRITE_PORT_UCHAR((PUCHAR)0x70, address); \
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WRITE_PORT_UCHAR((PUCHAR)0x71, value); \
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}
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extern ULONG_PTR KernelBase;
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/* FUNCTIONS *********************************************************************/
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extern ULONG Read8254Timer(VOID);
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extern VOID WaitFor8254Wraparound(VOID);
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extern VOID MpsTimerInterrupt(VOID);
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extern VOID MpsErrorInterrupt(VOID);
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extern VOID MpsSpuriousInterrupt(VOID);
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extern VOID MpsIpiInterrupt(VOID);
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ULONG APICGetMaxLVT(VOID)
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{
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ULONG tmp, ver, maxlvt;
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tmp = APICRead(APIC_VER);
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ver = GET_APIC_VERSION(tmp);
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/* 82489DXs do not report # of LVT entries. */
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maxlvt = APIC_INTEGRATED(ver) ? GET_APIC_MAXLVT(tmp) : 2;
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return maxlvt;
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}
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VOID APICClear(VOID)
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{
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ULONG tmp, maxlvt;
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maxlvt = APICGetMaxLVT();
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/*
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* Careful: we have to set masks only first to deassert
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* any level-triggered sources.
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*/
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if (maxlvt >= 3)
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{
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tmp = ERROR_VECTOR;
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APICWrite(APIC_LVT3, tmp | APIC_LVT3_MASKED);
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}
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tmp = APICRead(APIC_LVTT);
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APICWrite(APIC_LVTT, tmp | APIC_LVT_MASKED);
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tmp = APICRead(APIC_LINT0);
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APICWrite(APIC_LINT0, tmp | APIC_LVT_MASKED);
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tmp = APICRead(APIC_LINT1);
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APICWrite(APIC_LINT1, tmp | APIC_LVT_MASKED);
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if (maxlvt >= 4)
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{
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tmp = APICRead(APIC_LVTPC);
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APICWrite(APIC_LVTPC, tmp | APIC_LVT_MASKED);
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}
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#if 0
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if (maxlvt >= 5)
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{
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tmp = APICRead(APIC_LVTTHMR);
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APICWrite(APIC_LVTTHMR, tmp | APIC_LVT_MASKED);
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}
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#endif
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/*
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* Clean APIC state for other OSs:
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*/
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APICWrite(APIC_LVTT, APIC_LVT_MASKED);
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APICWrite(APIC_LINT0, APIC_LVT_MASKED);
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APICWrite(APIC_LINT1, APIC_LVT_MASKED);
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if (maxlvt >= 3)
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{
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APICWrite(APIC_LVT3, APIC_LVT3_MASKED);
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}
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if (maxlvt >= 4)
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{
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APICWrite(APIC_LVTPC, APIC_LVT_MASKED);
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}
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#if 0
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if (maxlvt >= 5)
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{
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APICWrite(APIC_LVTTHMR, APIC_LVT_MASKED);
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}
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#endif
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}
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/* Enable symetric I/O mode ie. connect the BSP's local APIC to INT and NMI lines */
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VOID EnableApicMode(VOID)
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{
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/*
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* Do not trust the local APIC being empty at bootup.
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*/
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APICClear();
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WRITE_PORT_UCHAR((PUCHAR)0x22, 0x70);
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WRITE_PORT_UCHAR((PUCHAR)0x23, 0x01);
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}
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/* Disable symetric I/O mode ie. go to PIC mode */
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__inline VOID DisableSMPMode(VOID)
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{
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/*
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* Put the board back into PIC mode (has an effect
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* only on certain older boards). Note that APIC
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* interrupts, including IPIs, won't work beyond
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* this point! The only exception are INIT IPIs.
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*/
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WRITE_PORT_UCHAR((PUCHAR)0x22, 0x70);
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WRITE_PORT_UCHAR((PUCHAR)0x23, 0x00);
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}
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VOID DumpESR(VOID)
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{
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ULONG tmp;
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if (APICGetMaxLVT() > 3)
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{
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APICWrite(APIC_ESR, 0);
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}
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tmp = APICRead(APIC_ESR);
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DbgPrint("ESR %08x\n", tmp);
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}
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VOID APICDisable(VOID)
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{
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ULONG tmp;
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APICClear();
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/*
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* Disable APIC (implies clearing of registers for 82489DX!).
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*/
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tmp = APICRead(APIC_SIVR);
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tmp &= ~APIC_SIVR_ENABLE;
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APICWrite(APIC_SIVR, tmp);
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}
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static VOID APICDumpBit(ULONG base)
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{
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ULONG v, i, j;
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DbgPrint("0123456789abcdef0123456789abcdef\n");
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for (i = 0; i < 8; i++)
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{
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v = APICRead(base + i*0x10);
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for (j = 0; j < 32; j++)
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{
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if (v & (1<<j))
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DbgPrint("1");
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else
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DbgPrint("0");
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}
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DbgPrint("\n");
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}
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}
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VOID APICDump(VOID)
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/*
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* Dump the contents of the local APIC registers
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*/
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{
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ULONG v, ver, maxlvt;
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ULONG r1, r2, w1, w2;
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ULONG CPU = ThisCPU();
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r1 = lastregr[CPU];
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r2 = lastvalr[CPU];
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w1 = lastregw[CPU];
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w2 = lastvalw[CPU];
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DbgPrint("\nPrinting local APIC contents on CPU(%d):\n", ThisCPU());
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v = APICRead(APIC_ID);
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DbgPrint("... ID : %08x (%01x) ", v, GET_APIC_ID(v));
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v = APICRead(APIC_VER);
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DbgPrint("... VERSION: %08x\n", v);
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ver = GET_APIC_VERSION(v);
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maxlvt = APICGetMaxLVT();
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v = APICRead(APIC_TPR);
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DbgPrint("... TPR : %08x (%02x)", v, v & ~0);
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if (APIC_INTEGRATED(ver))
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{
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/* !82489DX */
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v = APICRead(APIC_APR);
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DbgPrint("... APR : %08x (%02x)\n", v, v & ~0);
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v = APICRead(APIC_PPR);
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DbgPrint("... PPR : %08x\n", v);
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}
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v = APICRead(APIC_EOI);
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DbgPrint("... EOI : %08x ! ", v);
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v = APICRead(APIC_LDR);
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DbgPrint("... LDR : %08x\n", v);
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v = APICRead(APIC_DFR);
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DbgPrint("... DFR : %08x ! ", v);
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v = APICRead(APIC_SIVR);
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DbgPrint("... SIVR : %08x\n", v);
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if (0)
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{
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DbgPrint("... ISR field:\n");
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APICDumpBit(APIC_ISR);
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DbgPrint("... TMR field:\n");
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APICDumpBit(APIC_TMR);
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DbgPrint("... IRR field:\n");
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APICDumpBit(APIC_IRR);
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}
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if (APIC_INTEGRATED(ver))
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{
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/* !82489DX */
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if (maxlvt > 3)
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{
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/* Due to the Pentium erratum 3AP. */
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APICWrite(APIC_ESR, 0);
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}
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v = APICRead(APIC_ESR);
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DbgPrint("... ESR : %08x\n", v);
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}
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v = APICRead(APIC_ICR0);
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DbgPrint("... ICR0 : %08x ! ", v);
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v = APICRead(APIC_ICR1);
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DbgPrint("... ICR1 : %08x ! ", v);
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v = APICRead(APIC_LVTT);
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DbgPrint("... LVTT : %08x\n", v);
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if (maxlvt > 3)
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{
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/* PC is LVT#4. */
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v = APICRead(APIC_LVTPC);
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DbgPrint("... LVTPC : %08x ! ", v);
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}
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v = APICRead(APIC_LINT0);
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DbgPrint("... LINT0 : %08x ! ", v);
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v = APICRead(APIC_LINT1);
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DbgPrint("... LINT1 : %08x\n", v);
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if (maxlvt > 2)
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{
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v = APICRead(APIC_LVT3);
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DbgPrint("... LVT3 : %08x\n", v);
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}
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v = APICRead(APIC_ICRT);
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DbgPrint("... ICRT : %08x ! ", v);
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v = APICRead(APIC_CCRT);
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DbgPrint("... CCCT : %08x ! ", v);
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v = APICRead(APIC_TDCR);
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DbgPrint("... TDCR : %08x\n", v);
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DbgPrint("\n");
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DbgPrint("Last register read (offset): 0x%08X\n", r1);
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DbgPrint("Last register read (value): 0x%08X\n", r2);
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DbgPrint("Last register written (offset): 0x%08X\n", w1);
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DbgPrint("Last register written (value): 0x%08X\n", w2);
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DbgPrint("\n");
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}
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BOOLEAN VerifyLocalAPIC(VOID)
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{
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SIZE_T reg0, reg1;
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LARGE_INTEGER MsrValue;
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/* The version register is read-only in a real APIC */
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reg0 = APICRead(APIC_VER);
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DPRINT1("Getting VERSION: %x\n", reg0);
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APICWrite(APIC_VER, reg0 ^ APIC_VER_MASK);
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reg1 = APICRead(APIC_VER);
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DPRINT1("Getting VERSION: %x\n", reg1);
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/*
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* The two version reads above should print the same
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* numbers. If the second one is different, then we
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* poke at a non-APIC.
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*/
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if (reg1 != reg0)
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{
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return FALSE;
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}
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/*
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* Check if the version looks reasonably.
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*/
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reg1 = GET_APIC_VERSION(reg0);
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if (reg1 == 0x00 || reg1 == 0xff)
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{
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return FALSE;
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}
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reg1 = APICGetMaxLVT();
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if (reg1 < 0x02 || reg1 == 0xff)
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{
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return FALSE;
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}
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/*
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* The ID register is read/write in a real APIC.
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*/
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reg0 = APICRead(APIC_ID);
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DPRINT1("Getting ID: %x\n", reg0);
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APICWrite(APIC_ID, reg0 ^ APIC_ID_MASK);
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reg1 = APICRead(APIC_ID);
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DPRINT1("Getting ID: %x\n", reg1);
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APICWrite(APIC_ID, reg0);
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if (reg1 != (reg0 ^ APIC_ID_MASK))
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{
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return FALSE;
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}
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MsrValue.QuadPart = __readmsr(0x1B /*MSR_IA32_APICBASE*/);
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if (!(MsrValue.LowPart & /*MSR_IA32_APICBASE_ENABLE*/(1<<11)))
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{
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DPRINT1("Local APIC disabled by BIOS -- reenabling.\n");
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MsrValue.LowPart &= ~/*MSR_IA32_APICBASE_BASE*/(1<<11);
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MsrValue.LowPart |= /*MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE*/(1<<11)|0xfee00000;
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__writemsr(0x1B /*MSR_IA32_APICBASE*/, MsrValue.HighPart);
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}
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return TRUE;
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}
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#ifdef CONFIG_SMP
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VOID APICSendIPI(ULONG Target, ULONG Mode)
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{
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ULONG tmp, i, flags;
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/* save flags and disable interrupts */
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flags = __readeflags();
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_disable();
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/* Wait up to 100ms for the APIC to become ready */
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for (i = 0; i < 10000; i++)
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{
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tmp = APICRead(APIC_ICR0);
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/* Check Delivery Status */
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if ((tmp & APIC_ICR0_DS) == 0)
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break;
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KeStallExecutionProcessor(10);
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}
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if (i == 10000)
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{
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DPRINT1("CPU(%d) Previous IPI was not delivered after 100ms.\n", ThisCPU());
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}
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/* Setup the APIC to deliver the IPI */
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DPRINT("%08x %x\n", SET_APIC_DEST_FIELD(Target), Target);
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APICWrite(APIC_ICR1, SET_APIC_DEST_FIELD(Target));
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if (Target == APIC_TARGET_SELF)
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{
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Mode |= APIC_ICR0_DESTS_SELF;
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}
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else if (Target == APIC_TARGET_ALL)
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{
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Mode |= APIC_ICR0_DESTS_ALL;
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}
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else if (Target == APIC_TARGET_ALL_BUT_SELF)
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{
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Mode |= APIC_ICR0_DESTS_ALL_BUT_SELF;
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}
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else
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{
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Mode |= APIC_ICR0_DESTS_FIELD;
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}
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/* Now, fire off the IPI */
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APICWrite(APIC_ICR0, Mode);
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/* Wait up to 100ms for the APIC to become ready */
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for (i = 0; i < 10000; i++)
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{
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tmp = APICRead(APIC_ICR0);
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/* Check Delivery Status */
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if ((tmp & APIC_ICR0_DS) == 0)
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break;
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KeStallExecutionProcessor(10);
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}
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if (i == 10000)
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{
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DPRINT1("CPU(%d) Current IPI was not delivered after 100ms.\n", ThisCPU());
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}
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__writeeflags(flags);
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}
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#endif
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VOID APICSetup(VOID)
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{
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ULONG CPU, tmp;
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CPU = ThisCPU();
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// APICDump();
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DPRINT1("CPU%d:\n", CPU);
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DPRINT1(" Physical APIC id: %d\n", GET_APIC_ID(APICRead(APIC_ID)));
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DPRINT1(" Logical APIC id: %d\n", GET_APIC_LOGICAL_ID(APICRead(APIC_LDR)));
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DPRINT1("%08x %08x %08x\n", APICRead(APIC_ID), APICRead(APIC_LDR), APICRead(APIC_DFR));
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/*
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* Intel recommends to set DFR, LDR and TPR before enabling
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* an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
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* document number 292116). So here it goes...
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*/
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/*
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* Put the APIC into flat delivery mode.
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* Must be "all ones" explicitly for 82489DX.
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*/
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APICWrite(APIC_DFR, 0xFFFFFFFF);
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/*
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* Set up the logical destination ID.
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*/
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tmp = APICRead(APIC_LDR);
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tmp &= ~APIC_LDR_MASK;
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/*
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* FIXME:
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* This works only up to 8 CPU's
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*/
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tmp |= (1 << (KeGetCurrentProcessorNumber() + 24));
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APICWrite(APIC_LDR, tmp);
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|
|
|
|
DPRINT1("CPU%d:\n", CPU);
|
|
DPRINT1(" Physical APIC id: %d\n", GET_APIC_ID(APICRead(APIC_ID)));
|
|
DPRINT1(" Logical APIC id: %d\n", GET_APIC_LOGICAL_ID(APICRead(APIC_LDR)));
|
|
DPRINT1("%08x %08x %08x\n", APICRead(APIC_ID), APICRead(APIC_LDR), APICRead(APIC_DFR));
|
|
DPRINT1("%d\n", CPUMap[CPU].APICId);
|
|
|
|
/* Accept only higher interrupts */
|
|
APICWrite(APIC_TPR, 0xef);
|
|
|
|
/* Enable local APIC */
|
|
tmp = APICRead(APIC_SIVR);
|
|
tmp &= ~0xff;
|
|
tmp |= APIC_SIVR_ENABLE;
|
|
|
|
#if 0
|
|
tmp &= ~APIC_SIVR_FOCUS;
|
|
#else
|
|
tmp |= APIC_SIVR_FOCUS;
|
|
#endif
|
|
|
|
/* Set spurious interrupt vector */
|
|
tmp |= SPURIOUS_VECTOR;
|
|
APICWrite(APIC_SIVR, tmp);
|
|
|
|
/*
|
|
* Set up LVT0, LVT1:
|
|
*
|
|
* set up through-local-APIC on the BP's LINT0. This is not
|
|
* strictly necessery in pure symmetric-IO mode, but sometimes
|
|
* we delegate interrupts to the 8259A.
|
|
*/
|
|
tmp = APICRead(APIC_LINT0) & APIC_LVT_MASKED;
|
|
if (CPU == BootCPU && (APICMode == amPIC || !tmp))
|
|
{
|
|
tmp = APIC_DM_EXTINT;
|
|
DPRINT1("enabled ExtINT on CPU#%d\n", CPU);
|
|
}
|
|
else
|
|
{
|
|
tmp = APIC_DM_EXTINT | APIC_LVT_MASKED;
|
|
DPRINT1("masked ExtINT on CPU#%d\n", CPU);
|
|
}
|
|
APICWrite(APIC_LINT0, tmp);
|
|
|
|
/*
|
|
* Only the BSP should see the LINT1 NMI signal, obviously.
|
|
*/
|
|
if (CPU == BootCPU)
|
|
{
|
|
tmp = APIC_DM_NMI;
|
|
}
|
|
else
|
|
{
|
|
tmp = APIC_DM_NMI | APIC_LVT_MASKED;
|
|
}
|
|
if (!APIC_INTEGRATED(CPUMap[CPU].APICVersion))
|
|
{
|
|
/* 82489DX */
|
|
tmp |= APIC_LVT_LEVEL_TRIGGER;
|
|
}
|
|
APICWrite(APIC_LINT1, tmp);
|
|
|
|
if (APIC_INTEGRATED(CPUMap[CPU].APICVersion))
|
|
{
|
|
/* !82489DX */
|
|
if (APICGetMaxLVT() > 3)
|
|
{
|
|
/* Due to the Pentium erratum 3AP */
|
|
APICWrite(APIC_ESR, 0);
|
|
}
|
|
|
|
tmp = APICRead(APIC_ESR);
|
|
DPRINT("ESR value before enabling vector: 0x%X\n", tmp);
|
|
|
|
/* Enable sending errors */
|
|
tmp = ERROR_VECTOR;
|
|
APICWrite(APIC_LVT3, tmp);
|
|
|
|
/*
|
|
* Spec says clear errors after enabling vector
|
|
*/
|
|
if (APICGetMaxLVT() > 3)
|
|
{
|
|
APICWrite(APIC_ESR, 0);
|
|
}
|
|
tmp = APICRead(APIC_ESR);
|
|
DPRINT("ESR value after enabling vector: 0x%X\n", tmp);
|
|
}
|
|
}
|
|
#ifdef CONFIG_SMP
|
|
VOID APICSyncArbIDs(VOID)
|
|
{
|
|
ULONG i, tmp;
|
|
|
|
/* Wait up to 100ms for the APIC to become ready */
|
|
for (i = 0; i < 10000; i++)
|
|
{
|
|
tmp = APICRead(APIC_ICR0);
|
|
/* Check Delivery Status */
|
|
if ((tmp & APIC_ICR0_DS) == 0)
|
|
break;
|
|
KeStallExecutionProcessor(10);
|
|
}
|
|
|
|
if (i == 10000)
|
|
{
|
|
DPRINT("CPU(%d) APIC busy for 100ms.\n", ThisCPU());
|
|
}
|
|
|
|
DPRINT("Synchronizing Arb IDs.\n");
|
|
APICWrite(APIC_ICR0, APIC_ICR0_DESTS_ALL | APIC_ICR0_LEVEL | APIC_DM_INIT);
|
|
}
|
|
#endif
|
|
|
|
VOID MpsErrorHandler(VOID)
|
|
{
|
|
ULONG tmp1, tmp2;
|
|
|
|
APICDump();
|
|
|
|
tmp1 = APICRead(APIC_ESR);
|
|
APICWrite(APIC_ESR, 0);
|
|
tmp2 = APICRead(APIC_ESR);
|
|
DPRINT1("APIC error on CPU(%d) ESR(%x)(%x)\n", ThisCPU(), tmp1, tmp2);
|
|
|
|
/*
|
|
* Acknowledge the interrupt
|
|
*/
|
|
APICSendEOI();
|
|
|
|
/* Here is what the APIC error bits mean:
|
|
* 0: Send CS error
|
|
* 1: Receive CS error
|
|
* 2: Send accept error
|
|
* 3: Receive accept error
|
|
* 4: Reserved
|
|
* 5: Send illegal vector
|
|
* 6: Received illegal vector
|
|
* 7: Illegal register address
|
|
*/
|
|
DPRINT1("APIC error on CPU(%d) ESR(%x)(%x)\n", ThisCPU(), tmp1, tmp2);
|
|
for (;;);
|
|
}
|
|
|
|
VOID MpsSpuriousHandler(VOID)
|
|
{
|
|
ULONG tmp;
|
|
|
|
DPRINT("Spurious interrupt on CPU(%d)\n", ThisCPU());
|
|
|
|
tmp = APICRead(APIC_ISR + ((SPURIOUS_VECTOR & ~0x1f) >> 1));
|
|
if (tmp & (1 << (SPURIOUS_VECTOR & 0x1f)))
|
|
{
|
|
APICSendEOI();
|
|
return;
|
|
}
|
|
#if 0
|
|
/* No need to send EOI here */
|
|
APICDump();
|
|
#endif
|
|
}
|
|
|
|
#ifdef CONFIG_SMP
|
|
VOID MpsIpiHandler(VOID)
|
|
{
|
|
KIRQL oldIrql;
|
|
|
|
HalBeginSystemInterrupt(IPI_LEVEL,
|
|
IPI_VECTOR,
|
|
&oldIrql);
|
|
_enable();
|
|
#if 0
|
|
DbgPrint("(%s:%d) MpsIpiHandler on CPU%d, current irql is %d\n",
|
|
__FILE__,__LINE__, KeGetCurrentProcessorNumber(), KeGetCurrentIrql());
|
|
#endif
|
|
|
|
KiIpiServiceRoutine(NULL, NULL);
|
|
|
|
#if 0
|
|
DbgPrint("(%s:%d) MpsIpiHandler on CPU%d done\n", __FILE__,__LINE__, KeGetCurrentProcessorNumber());
|
|
#endif
|
|
|
|
_disable();
|
|
HalEndSystemInterrupt(oldIrql, 0);
|
|
}
|
|
#endif
|
|
|
|
VOID
|
|
MpsIRQTrapFrameToTrapFrame(PKIRQ_TRAPFRAME IrqTrapFrame,
|
|
PKTRAP_FRAME TrapFrame)
|
|
{
|
|
#ifdef _M_AMD64
|
|
UNIMPLEMENTED;
|
|
#else
|
|
TrapFrame->SegGs = (USHORT)IrqTrapFrame->Gs;
|
|
TrapFrame->SegFs = (USHORT)IrqTrapFrame->Fs;
|
|
TrapFrame->SegEs = (USHORT)IrqTrapFrame->Es;
|
|
TrapFrame->SegDs = (USHORT)IrqTrapFrame->Ds;
|
|
TrapFrame->Eax = IrqTrapFrame->Eax;
|
|
TrapFrame->Ecx = IrqTrapFrame->Ecx;
|
|
TrapFrame->Edx = IrqTrapFrame->Edx;
|
|
TrapFrame->Ebx = IrqTrapFrame->Ebx;
|
|
TrapFrame->HardwareEsp = IrqTrapFrame->Esp;
|
|
TrapFrame->Ebp = IrqTrapFrame->Ebp;
|
|
TrapFrame->Esi = IrqTrapFrame->Esi;
|
|
TrapFrame->Edi = IrqTrapFrame->Edi;
|
|
TrapFrame->Eip = IrqTrapFrame->Eip;
|
|
TrapFrame->SegCs = IrqTrapFrame->Cs;
|
|
TrapFrame->EFlags = IrqTrapFrame->Eflags;
|
|
#endif
|
|
}
|
|
|
|
VOID
|
|
MpsTimerHandler(ULONG Vector, PKIRQ_TRAPFRAME Trapframe)
|
|
{
|
|
KIRQL oldIrql;
|
|
KTRAP_FRAME KernelTrapFrame;
|
|
#if 0
|
|
ULONG CPU;
|
|
static ULONG Count[MAX_CPU] = {0,};
|
|
#endif
|
|
HalBeginSystemInterrupt(LOCAL_TIMER_VECTOR,
|
|
PROFILE_LEVEL,
|
|
&oldIrql);
|
|
_enable();
|
|
|
|
#if 0
|
|
CPU = ThisCPU();
|
|
if ((Count[CPU] % 100) == 0)
|
|
{
|
|
DbgPrint("(%s:%d) MpsTimerHandler on CPU%d, irql = %d, epi = %x, KPCR = %x\n", __FILE__, __LINE__, CPU, oldIrql,Trapframe->Eip, KeGetPcr());
|
|
}
|
|
Count[CPU]++;
|
|
#endif
|
|
|
|
/* FIXME: SMP is totally broken */
|
|
MpsIRQTrapFrameToTrapFrame(Trapframe, &KernelTrapFrame);
|
|
if (KeGetCurrentProcessorNumber() == 0)
|
|
{
|
|
//KeUpdateSystemTime(&KernelTrapFrame, oldIrql);
|
|
}
|
|
else
|
|
{
|
|
//KeUpdateRunTime(&KernelTrapFrame, oldIrql);
|
|
}
|
|
|
|
_disable();
|
|
HalEndSystemInterrupt (oldIrql, 0);
|
|
}
|
|
|
|
VOID APICSetupLVTT(ULONG ClockTicks)
|
|
{
|
|
ULONG tmp;
|
|
|
|
tmp = GET_APIC_VERSION(APICRead(APIC_VER));
|
|
if (!APIC_INTEGRATED(tmp))
|
|
{
|
|
tmp = SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV) | APIC_LVT_PERIODIC | LOCAL_TIMER_VECTOR;
|
|
}
|
|
else
|
|
{
|
|
/* Periodic timer */
|
|
tmp = APIC_LVT_PERIODIC | LOCAL_TIMER_VECTOR;
|
|
}
|
|
APICWrite(APIC_LVTT, tmp);
|
|
|
|
tmp = APICRead(APIC_TDCR);
|
|
tmp &= ~(APIC_TDCR_1 | APIC_TIMER_BASE_DIV);
|
|
tmp |= APIC_TDCR_16;
|
|
APICWrite(APIC_TDCR, tmp);
|
|
APICWrite(APIC_ICRT, ClockTicks / APIC_DIVISOR);
|
|
}
|
|
|
|
VOID
|
|
APICCalibrateTimer(ULONG CPU)
|
|
{
|
|
ULARGE_INTEGER t1, t2;
|
|
LONG tt1, tt2;
|
|
BOOLEAN TSCPresent;
|
|
|
|
DPRINT("Calibrating APIC timer for CPU %d\n", CPU);
|
|
|
|
APICSetupLVTT(1000000000);
|
|
|
|
TSCPresent = KeGetCurrentPrcb()->FeatureBits & KF_RDTSC ? TRUE : FALSE;
|
|
|
|
/*
|
|
* The timer chip counts down to zero. Let's wait
|
|
* for a wraparound to start exact measurement:
|
|
* (the current tick might have been already half done)
|
|
*/
|
|
//WaitFor8254Wraparound();
|
|
|
|
/*
|
|
* We wrapped around just now. Let's start
|
|
*/
|
|
if (TSCPresent)
|
|
{
|
|
t1.QuadPart = (LONGLONG)__rdtsc();
|
|
}
|
|
tt1 = APICRead(APIC_CCRT);
|
|
|
|
//WaitFor8254Wraparound();
|
|
|
|
|
|
tt2 = APICRead(APIC_CCRT);
|
|
if (TSCPresent)
|
|
{
|
|
t2.QuadPart = (LONGLONG)__rdtsc();
|
|
CPUMap[CPU].CoreSpeed = (HZ * (ULONG)(t2.QuadPart - t1.QuadPart));
|
|
DPRINT("CPU clock speed is %ld.%04ld MHz.\n",
|
|
CPUMap[CPU].CoreSpeed/1000000,
|
|
CPUMap[CPU].CoreSpeed%1000000);
|
|
KeGetCurrentPrcb()->MHz = CPUMap[CPU].CoreSpeed/1000000;
|
|
}
|
|
|
|
CPUMap[CPU].BusSpeed = (HZ * (long)(tt1 - tt2) * APIC_DIVISOR);
|
|
|
|
/* Setup timer for normal operation */
|
|
// APICSetupLVTT((CPUMap[CPU].BusSpeed / 1000000) * 100); // 100ns
|
|
APICSetupLVTT((CPUMap[CPU].BusSpeed / 1000000) * 10000); // 10ms
|
|
// APICSetupLVTT((CPUMap[CPU].BusSpeed / 1000000) * 100000); // 100ms
|
|
|
|
DPRINT("Host bus clock speed is %ld.%04ld MHz.\n",
|
|
CPUMap[CPU].BusSpeed/1000000,
|
|
CPUMap[CPU].BusSpeed%1000000);
|
|
}
|
|
|
|
VOID
|
|
SetInterruptGate(ULONG index, ULONG_PTR address)
|
|
{
|
|
#ifdef _M_AMD64
|
|
KIDTENTRY64 *idt;
|
|
|
|
idt = &KeGetPcr()->IdtBase[index];
|
|
|
|
idt->OffsetLow = address & 0xffff;
|
|
idt->Selector = KGDT_64_R0_CODE;
|
|
idt->IstIndex = 0;
|
|
idt->Reserved0 = 0;
|
|
idt->Type = 0x0e;
|
|
idt->Dpl = 0;
|
|
idt->Present = 1;
|
|
idt->OffsetMiddle = (address >> 16) & 0xffff;
|
|
idt->OffsetHigh = address >> 32;
|
|
idt->Reserved1 = 0;
|
|
idt->Alignment = 0;
|
|
#else
|
|
KIDTENTRY *idt;
|
|
KIDT_ACCESS Access;
|
|
|
|
/* Set the IDT Access Bits */
|
|
Access.Reserved = 0;
|
|
Access.Present = 1;
|
|
Access.Dpl = 0; /* Kernel-Mode */
|
|
Access.SystemSegmentFlag = 0;
|
|
Access.SegmentType = I386_INTERRUPT_GATE;
|
|
|
|
idt = (KIDTENTRY*)((ULONG)KeGetPcr()->IDT + index * sizeof(KIDTENTRY));
|
|
idt->Offset = (USHORT)(address & 0xffff);
|
|
idt->Selector = KGDT_R0_CODE;
|
|
idt->Access = Access.Value;
|
|
idt->ExtendedOffset = (USHORT)(address >> 16);
|
|
#endif
|
|
}
|
|
|
|
VOID HaliInitBSP(VOID)
|
|
{
|
|
#ifdef CONFIG_SMP
|
|
PUSHORT ps;
|
|
#endif
|
|
|
|
static BOOLEAN BSPInitialized = FALSE;
|
|
|
|
/* Only initialize the BSP once */
|
|
if (BSPInitialized)
|
|
{
|
|
ASSERT(FALSE);
|
|
return;
|
|
}
|
|
|
|
BSPInitialized = TRUE;
|
|
|
|
/* Setup interrupt handlers */
|
|
SetInterruptGate(LOCAL_TIMER_VECTOR, (ULONG_PTR)MpsTimerInterrupt);
|
|
SetInterruptGate(ERROR_VECTOR, (ULONG_PTR)MpsErrorInterrupt);
|
|
SetInterruptGate(SPURIOUS_VECTOR, (ULONG_PTR)MpsSpuriousInterrupt);
|
|
#ifdef CONFIG_SMP
|
|
SetInterruptGate(IPI_VECTOR, (ULONG_PTR)MpsIpiInterrupt);
|
|
#endif
|
|
DPRINT("APIC is mapped at 0x%X\n", APICBase);
|
|
|
|
if (VerifyLocalAPIC())
|
|
{
|
|
DPRINT("APIC found\n");
|
|
}
|
|
else
|
|
{
|
|
DPRINT("No APIC found\n");
|
|
ASSERT(FALSE);
|
|
}
|
|
|
|
if (APICMode == amPIC)
|
|
{
|
|
EnableApicMode();
|
|
}
|
|
|
|
APICSetup();
|
|
|
|
#ifdef CONFIG_SMP
|
|
/* BIOS data segment */
|
|
BIOSBase = (PULONG)BIOS_AREA;
|
|
|
|
/* Area for communicating with the APs */
|
|
CommonBase = (PULONG)COMMON_AREA;
|
|
|
|
/* Copy bootstrap code to common area */
|
|
memcpy((PVOID)((ULONG_PTR)CommonBase + PAGE_SIZE),
|
|
&APstart,
|
|
(ULONG_PTR)&APend - (ULONG_PTR)&APstart + 1);
|
|
|
|
/* Set shutdown code */
|
|
CMOS_WRITE(0xF, 0xA);
|
|
|
|
/* Set warm reset vector */
|
|
ps = (PUSHORT)((ULONG_PTR)BIOSBase + 0x467);
|
|
*ps = (COMMON_AREA + PAGE_SIZE) & 0xF;
|
|
|
|
ps = (PUSHORT)((ULONG_PTR)BIOSBase + 0x469);
|
|
*ps = (COMMON_AREA + PAGE_SIZE) >> 4;
|
|
#endif
|
|
|
|
/* Calibrate APIC timer */
|
|
APICCalibrateTimer(BootCPU);
|
|
}
|
|
|
|
#ifdef CONFIG_SMP
|
|
VOID
|
|
HaliStartApplicationProcessor(ULONG Cpu, ULONG Stack)
|
|
{
|
|
ULONG tmp, maxlvt;
|
|
PCOMMON_AREA_INFO Common;
|
|
ULONG StartupCount;
|
|
ULONG i, j;
|
|
ULONG DeliveryStatus = 0;
|
|
ULONG AcceptStatus = 0;
|
|
|
|
if (Cpu >= MAX_CPU ||
|
|
Cpu >= CPUCount ||
|
|
OnlineCPUs & (1 << Cpu))
|
|
{
|
|
ASSERT(FALSE);
|
|
}
|
|
DPRINT1("Attempting to boot CPU %d\n", Cpu);
|
|
|
|
/* Send INIT IPI */
|
|
|
|
APICSendIPI(Cpu, APIC_DM_INIT|APIC_ICR0_LEVEL_ASSERT);
|
|
|
|
KeStallExecutionProcessor(200);
|
|
|
|
/* Deassert INIT */
|
|
|
|
APICSendIPI(Cpu, APIC_DM_INIT|APIC_ICR0_LEVEL_DEASSERT);
|
|
|
|
if (APIC_INTEGRATED(CPUMap[Cpu].APICVersion))
|
|
{
|
|
/* Clear APIC errors */
|
|
APICWrite(APIC_ESR, 0);
|
|
tmp = (APICRead(APIC_ESR) & APIC_ESR_MASK);
|
|
}
|
|
|
|
Common = (PCOMMON_AREA_INFO)CommonBase;
|
|
|
|
/* Write the location of the AP stack */
|
|
Common->Stack = (ULONG)Stack;
|
|
/* Write the page directory page */
|
|
Common->PageDirectory = __readcr3();
|
|
/* Write the kernel entry point */
|
|
Common->NtProcessStartup = (ULONG_PTR)RtlImageNtHeader((PVOID)KernelBase)->OptionalHeader.AddressOfEntryPoint + KernelBase;
|
|
/* Write the state of the mae mode */
|
|
Common->PaeModeEnabled = __readcr4() & CR4_PAE ? 1 : 0;
|
|
|
|
DPRINT1("%x %x %x %x\n", Common->Stack, Common->PageDirectory, Common->NtProcessStartup, Common->PaeModeEnabled);
|
|
|
|
DPRINT("Cpu %d got stack at 0x%X\n", Cpu, Common->Stack);
|
|
#if 0
|
|
for (j = 0; j < 16; j++)
|
|
{
|
|
Common->Debug[j] = 0;
|
|
}
|
|
#endif
|
|
|
|
maxlvt = APICGetMaxLVT();
|
|
|
|
/* Is this a local APIC or an 82489DX? */
|
|
StartupCount = (APIC_INTEGRATED(CPUMap[Cpu].APICVersion)) ? 2 : 0;
|
|
|
|
for (i = 1; i <= StartupCount; i++)
|
|
{
|
|
/* It's a local APIC, so send STARTUP IPI */
|
|
DPRINT("Sending startup signal %d\n", i);
|
|
/* Clear errors */
|
|
APICWrite(APIC_ESR, 0);
|
|
APICRead(APIC_ESR);
|
|
|
|
APICSendIPI(Cpu, APIC_DM_STARTUP | ((COMMON_AREA + PAGE_SIZE) >> 12)|APIC_ICR0_LEVEL_DEASSERT);
|
|
|
|
/* Wait up to 10ms for IPI to be delivered */
|
|
j = 0;
|
|
do
|
|
{
|
|
KeStallExecutionProcessor(10);
|
|
|
|
/* Check Delivery Status */
|
|
DeliveryStatus = APICRead(APIC_ICR0) & APIC_ICR0_DS;
|
|
|
|
j++;
|
|
} while ((DeliveryStatus) && (j < 1000));
|
|
|
|
KeStallExecutionProcessor(200);
|
|
|
|
/*
|
|
* Due to the Pentium erratum 3AP.
|
|
*/
|
|
if (maxlvt > 3)
|
|
{
|
|
APICRead(APIC_SIVR);
|
|
APICWrite(APIC_ESR, 0);
|
|
}
|
|
|
|
AcceptStatus = APICRead(APIC_ESR) & APIC_ESR_MASK;
|
|
|
|
if (DeliveryStatus || AcceptStatus)
|
|
{
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (DeliveryStatus)
|
|
{
|
|
DPRINT("STARTUP IPI for CPU %d was never delivered.\n", Cpu);
|
|
}
|
|
|
|
if (AcceptStatus)
|
|
{
|
|
DPRINT("STARTUP IPI for CPU %d was never accepted.\n", Cpu);
|
|
}
|
|
|
|
if (!(DeliveryStatus || AcceptStatus))
|
|
{
|
|
|
|
/* Wait no more than 5 seconds for processor to boot */
|
|
DPRINT("Waiting for 5 seconds for CPU %d to boot\n", Cpu);
|
|
|
|
/* Wait no more than 5 seconds */
|
|
for (j = 0; j < 50000; j++)
|
|
{
|
|
if (CPUMap[Cpu].Flags & CPU_ENABLED)
|
|
{
|
|
break;
|
|
}
|
|
KeStallExecutionProcessor(100);
|
|
}
|
|
}
|
|
|
|
if (CPUMap[Cpu].Flags & CPU_ENABLED)
|
|
{
|
|
DbgPrint("CPU %d is now running\n", Cpu);
|
|
}
|
|
else
|
|
{
|
|
DbgPrint("Initialization of CPU %d failed\n", Cpu);
|
|
}
|
|
|
|
#if 0
|
|
DPRINT("Debug bytes are:\n");
|
|
|
|
for (j = 0; j < 4; j++)
|
|
{
|
|
DPRINT("0x%08X 0x%08X 0x%08X 0x%08X.\n",
|
|
Common->Debug[j*4+0],
|
|
Common->Debug[j*4+1],
|
|
Common->Debug[j*4+2],
|
|
Common->Debug[j*4+3]);
|
|
}
|
|
|
|
#endif
|
|
}
|
|
|
|
#endif
|
|
|
|
VOID
|
|
FASTCALL
|
|
DECLSPEC_NORETURN
|
|
HalpApcInterruptHandler(IN PKTRAP_FRAME TrapFrame)
|
|
{
|
|
/* Set up a fake INT Stack */
|
|
TrapFrame->EFlags = __readeflags();
|
|
TrapFrame->SegCs = KGDT_R0_CODE;
|
|
TrapFrame->Eip = TrapFrame->Eax;
|
|
|
|
/* Build the trap frame */
|
|
KiEnterInterruptTrap(TrapFrame);
|
|
|
|
/* unimplemented */
|
|
UNIMPLEMENTED;
|
|
|
|
/* Exit the interrupt */
|
|
KiEoiHelper(TrapFrame);
|
|
|
|
}
|
|
|
|
/* EOF */
|