mirror of
https://github.com/reactos/reactos.git
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292 lines
7.4 KiB
C
292 lines
7.4 KiB
C
#pragma once
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//
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// Helper Macros
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//
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#define PASTE2(x,y) x ## y
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#define POINTER_TO_(x) PASTE2(P,x)
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#define READ_FROM(x) PASTE2(READ_PORT_, x)
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#define WRITE_TO(x) PASTE2(WRITE_PORT_, x)
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//
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// Declares a PCI Register Read/Write Routine
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//
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#define TYPE_DEFINE(x, y) \
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ULONG \
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NTAPI \
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x( \
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IN PPCIPBUSDATA BusData, \
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IN y PciCfg, \
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IN PUCHAR Buffer, \
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IN ULONG Offset \
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)
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#define TYPE1_DEFINE(x) TYPE_DEFINE(x, PPCI_TYPE1_CFG_BITS);
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#define TYPE2_DEFINE(x) TYPE_DEFINE(x, PPCI_TYPE2_ADDRESS_BITS);
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//
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// Defines a PCI Register Read/Write Type 1 Routine Prologue and Epilogue
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//
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#define TYPE1_START(x, y) \
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TYPE_DEFINE(x, PPCI_TYPE1_CFG_BITS) \
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{ \
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ULONG i = Offset % sizeof(ULONG); \
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PciCfg->u.bits.RegisterNumber = Offset / sizeof(ULONG); \
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WRITE_PORT_ULONG(BusData->Config.Type1.Address, PciCfg->u.AsULONG);
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#define TYPE1_END(y) \
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return sizeof(y); }
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#define TYPE2_END TYPE1_END
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//
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// PCI Register Read Type 1 Routine
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//
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#define TYPE1_READ(x, y) \
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TYPE1_START(x, y) \
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*((POINTER_TO_(y))Buffer) = \
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READ_FROM(y)((POINTER_TO_(y))(BusData->Config.Type1.Data + i)); \
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TYPE1_END(y)
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//
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// PCI Register Write Type 1 Routine
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//
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#define TYPE1_WRITE(x, y) \
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TYPE1_START(x, y) \
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WRITE_TO(y)((POINTER_TO_(y))(BusData->Config.Type1.Data + i), \
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*((POINTER_TO_(y))Buffer)); \
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TYPE1_END(y)
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//
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// Defines a PCI Register Read/Write Type 2 Routine Prologue and Epilogue
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//
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#define TYPE2_START(x, y) \
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TYPE_DEFINE(x, PPCI_TYPE2_ADDRESS_BITS) \
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{ \
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PciCfg->u.bits.RegisterNumber = (USHORT)Offset;
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//
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// PCI Register Read Type 2 Routine
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//
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#define TYPE2_READ(x, y) \
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TYPE2_START(x, y) \
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*((POINTER_TO_(y))Buffer) = \
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READ_FROM(y)((POINTER_TO_(y))(ULONG)PciCfg->u.AsUSHORT); \
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TYPE2_END(y)
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//
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// PCI Register Write Type 2 Routine
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//
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#define TYPE2_WRITE(x, y) \
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TYPE2_START(x, y) \
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WRITE_TO(y)((POINTER_TO_(y))(ULONG)PciCfg->u.AsUSHORT, \
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*((POINTER_TO_(y))Buffer)); \
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TYPE2_END(y)
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typedef struct _PCIPBUSDATA
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{
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PCIBUSDATA CommonData;
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union
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{
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struct
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{
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PULONG Address;
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ULONG Data;
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} Type1;
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struct
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{
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PUCHAR CSE;
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PUCHAR Forward;
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ULONG Base;
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} Type2;
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} Config;
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ULONG MaxDevice;
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} PCIPBUSDATA, *PPCIPBUSDATA;
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typedef ULONG
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(NTAPI *FncConfigIO)(
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IN PPCIPBUSDATA BusData,
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IN PVOID State,
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IN PUCHAR Buffer,
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IN ULONG Offset
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);
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typedef VOID
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(NTAPI *FncSync)(
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IN PBUS_HANDLER BusHandler,
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IN PCI_SLOT_NUMBER Slot,
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IN PKIRQL Irql,
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IN PVOID State
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);
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typedef VOID
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(NTAPI *FncReleaseSync)(
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IN PBUS_HANDLER BusHandler,
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IN KIRQL Irql
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);
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typedef struct _PCI_CONFIG_HANDLER
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{
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FncSync Synchronize;
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FncReleaseSync ReleaseSynchronzation;
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FncConfigIO ConfigRead[3];
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FncConfigIO ConfigWrite[3];
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} PCI_CONFIG_HANDLER, *PPCI_CONFIG_HANDLER;
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typedef struct _PCI_REGISTRY_INFO_INTERNAL
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{
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UCHAR MajorRevision;
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UCHAR MinorRevision;
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UCHAR NoBuses;
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UCHAR HardwareMechanism;
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ULONG ElementCount;
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PCI_CARD_DESCRIPTOR CardList[ANYSIZE_ARRAY];
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} PCI_REGISTRY_INFO_INTERNAL, *PPCI_REGISTRY_INFO_INTERNAL;
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/* FUNCTIONS *****************************************************************/
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VOID
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NTAPI
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HalpPCISynchronizeType1(
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IN PBUS_HANDLER BusHandler,
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IN PCI_SLOT_NUMBER Slot,
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IN PKIRQL Irql,
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IN PPCI_TYPE1_CFG_BITS PciCfg
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);
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VOID
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NTAPI
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HalpPCIReleaseSynchronzationType1(
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IN PBUS_HANDLER BusHandler,
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IN KIRQL Irql
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);
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VOID
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NTAPI
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HalpPCISynchronizeType2(
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IN PBUS_HANDLER BusHandler,
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IN PCI_SLOT_NUMBER Slot,
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IN PKIRQL Irql,
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IN PPCI_TYPE2_ADDRESS_BITS PciCfg
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);
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VOID
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NTAPI
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HalpPCIReleaseSynchronzationType2(
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IN PBUS_HANDLER BusHandler,
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IN KIRQL Irql
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);
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TYPE1_DEFINE(HalpPCIReadUcharType1);
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TYPE1_DEFINE(HalpPCIReadUshortType1);
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TYPE1_DEFINE(HalpPCIReadUlongType1);
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TYPE2_DEFINE(HalpPCIReadUcharType2);
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TYPE2_DEFINE(HalpPCIReadUshortType2);
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TYPE2_DEFINE(HalpPCIReadUlongType2);
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TYPE1_DEFINE(HalpPCIWriteUcharType1);
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TYPE1_DEFINE(HalpPCIWriteUshortType1);
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TYPE1_DEFINE(HalpPCIWriteUlongType1);
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TYPE2_DEFINE(HalpPCIWriteUcharType2);
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TYPE2_DEFINE(HalpPCIWriteUshortType2);
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TYPE2_DEFINE(HalpPCIWriteUlongType2);
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BOOLEAN
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NTAPI
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HalpValidPCISlot(
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IN PBUS_HANDLER BusHandler,
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IN PCI_SLOT_NUMBER Slot
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);
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VOID
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NTAPI
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HalpReadPCIConfig(
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IN PBUS_HANDLER BusHandler,
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IN PCI_SLOT_NUMBER Slot,
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IN PVOID Buffer,
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IN ULONG Offset,
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IN ULONG Length
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);
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VOID
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NTAPI
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HalpWritePCIConfig(
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IN PBUS_HANDLER BusHandler,
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IN PCI_SLOT_NUMBER Slot,
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IN PVOID Buffer,
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IN ULONG Offset,
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IN ULONG Length
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);
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ULONG
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NTAPI
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HalpGetSystemInterruptVector(
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ULONG BusNumber,
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ULONG BusInterruptLevel,
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ULONG BusInterruptVector,
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PKIRQL Irql,
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PKAFFINITY Affinity
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);
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ULONG
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NTAPI
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HalpGetCmosData(
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IN ULONG BusNumber,
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IN ULONG SlotNumber,
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IN PVOID Buffer,
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IN ULONG Length
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);
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ULONG
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NTAPI
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HalpSetCmosData(
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IN ULONG BusNumber,
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IN ULONG SlotNumber,
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IN PVOID Buffer,
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IN ULONG Length
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);
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ULONG
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NTAPI
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HalpGetPCIData(
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IN PBUS_HANDLER BusHandler,
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IN PBUS_HANDLER RootBusHandler,
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IN PCI_SLOT_NUMBER SlotNumber,
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IN PUCHAR Buffer,
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IN ULONG Offset,
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IN ULONG Length
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);
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ULONG
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NTAPI
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HalpSetPCIData(
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IN PBUS_HANDLER BusHandler,
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IN PBUS_HANDLER RootBusHandler,
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IN PCI_SLOT_NUMBER SlotNumber,
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IN PUCHAR Buffer,
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IN ULONG Offset,
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IN ULONG Length
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);
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NTSTATUS
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NTAPI
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HalpAssignPCISlotResources(
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IN PBUS_HANDLER BusHandler,
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IN PBUS_HANDLER RootHandler,
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IN PUNICODE_STRING RegistryPath,
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IN PUNICODE_STRING DriverClassName OPTIONAL,
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IN PDRIVER_OBJECT DriverObject,
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IN PDEVICE_OBJECT DeviceObject OPTIONAL,
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IN ULONG Slot,
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IN OUT PCM_RESOURCE_LIST *pAllocatedResources
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);
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VOID
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NTAPI
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HalpInitializePciBus(
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VOID
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);
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extern ULONG HalpBusType;
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extern BOOLEAN HalpPCIConfigInitialized;
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extern BUS_HANDLER HalpFakePciBusHandler;
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extern ULONG HalpMinPciBus, HalpMaxPciBus;
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/* EOF */
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