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![]() - Fix I/O APIC register access - set APIC logical id based on Cpu (currently flat model with up to 8 cpus supported) - In HalpInitializeTsc, setup the RTC clock, since the timer is initialized later - in the TSC calibration ISR, send EOI and read RTC register C to get the next interrupt svn path=/trunk/; revision=53634 |
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.. | ||
acpi | ||
amd64 | ||
apic | ||
generic | ||
include | ||
legacy | ||
mp | ||
up | ||
xbox | ||
CMakeLists.txt | ||
directory.rbuild | ||
hal.rbuild | ||
hal_generic.rbuild | ||
hal_generic_acpi.rbuild | ||
hal_generic_mp.rbuild | ||
hal_generic_pcat.rbuild | ||
hal_generic_up.rbuild | ||
hal_mini.rbuild | ||
halacpi.rbuild | ||
halamd64.rbuild | ||
halmps.rbuild | ||
halxbox.rbuild |