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527f2f9057
* Create a branch for some evul shell experiments. svn path=/branches/shell-experiments/; revision=61927
271 lines
5.3 KiB
ArmAsm
271 lines
5.3 KiB
ArmAsm
/*
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synth_arm: ARM optimized synth
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copyright 1995-2009 by the mpg123 project - free software under the terms of the LGPL 2.1
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see COPYING and AUTHORS files in distribution or http://mpg123.org
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initially written by Taihei Monma
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*/
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#include "mangle.h"
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#define WINDOW r0
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#define B0 r1
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#define SAMPLES r2
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#define REG_CLIP r4
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#define REG_MAX r12
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/*
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int synth_1to1_arm_asm(real *window, real *b0, short *samples, int bo1);
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return value: number of clipped samples
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*/
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.text
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ALIGN4
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.globl ASM_NAME(synth_1to1_arm_asm)
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ASM_NAME(synth_1to1_arm_asm):
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stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, lr}
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add WINDOW, WINDOW, #64
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sub WINDOW, WINDOW, r3, lsl #2
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eor REG_CLIP, REG_CLIP, REG_CLIP
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mov REG_MAX, #1073741824
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sub REG_MAX, REG_MAX, #32768
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mov r3, #16
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ldr r5, [WINDOW], #4
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ldr r6, [B0], #4
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.Loop_start_1:
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ldr r8, [WINDOW], #4
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ldr r9, [B0], #4
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mul r7, r5, r6
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ldr r5, [WINDOW], #4
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ldr r6, [B0], #4
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mul r10, r8, r9
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ldr r8, [WINDOW], #4
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ldr r9, [B0], #4
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mla r7, r5, r6, r7
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ldr r5, [WINDOW], #4
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ldr r6, [B0], #4
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mla r10, r8, r9, r10
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ldr r8, [WINDOW], #4
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ldr r9, [B0], #4
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mla r7, r5, r6, r7
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ldr r5, [WINDOW], #4
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ldr r6, [B0], #4
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mla r10, r8, r9, r10
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ldr r8, [WINDOW], #4
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ldr r9, [B0], #4
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mla r7, r5, r6, r7
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ldr r5, [WINDOW], #4
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ldr r6, [B0], #4
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mla r10, r8, r9, r10
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ldr r8, [WINDOW], #4
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ldr r9, [B0], #4
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mla r7, r5, r6, r7
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ldr r5, [WINDOW], #4
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ldr r6, [B0], #4
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mla r10, r8, r9, r10
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ldr r8, [WINDOW], #4
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ldr r9, [B0], #4
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mla r7, r5, r6, r7
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ldr r5, [WINDOW], #4
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ldr r6, [B0], #4
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mla r10, r8, r9, r10
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ldr r8, [WINDOW], #4
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ldr r9, [B0], #4
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mla r7, r5, r6, r7
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ldr r5, [WINDOW], #4
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ldr r6, [B0], #4
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mla r10, r8, r9, r10
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ldr r8, [WINDOW], #68
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ldr r9, [B0], #4
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mla r7, r5, r6, r7
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ldr r5, [WINDOW], #4
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ldr r6, [B0], #4
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mla r10, r8, r9, r10
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sub r7, r7, r10
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cmp r7, REG_MAX
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movgt r7, REG_MAX
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addgt REG_CLIP, REG_CLIP, #1
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cmp r7, #-1073741824
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movlt r7, #-1073741824
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addlt REG_CLIP, REG_CLIP, #1
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movs r7, r7, asr #15
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adc r7, r7, #0
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strh r7, [SAMPLES], #4
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subs r3, r3, #1
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bne .Loop_start_1
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add WINDOW, WINDOW, #4
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add B0, B0, #4
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ldr r8, [WINDOW], #8
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ldr r9, [B0], #8
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mul r7, r5, r6
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ldr r5, [WINDOW], #8
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ldr r6, [B0], #8
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mul r10, r8, r9
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ldr r8, [WINDOW], #8
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ldr r9, [B0], #8
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mla r7, r5, r6, r7
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ldr r5, [WINDOW], #8
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ldr r6, [B0], #8
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mla r10, r8, r9, r10
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ldr r8, [WINDOW], #8
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ldr r9, [B0], #8
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mla r7, r5, r6, r7
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ldr r5, [WINDOW], #8
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ldr r6, [B0], #8
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mla r10, r8, r9, r10
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ldr r8, [WINDOW], #72
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ldr r9, [B0], #-120
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mla r7, r5, r6, r7
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ldr r5, [WINDOW], #4
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ldr r6, [B0], #4
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mla r10, r8, r9, r10
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add r7, r7, r10
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cmp r7, REG_MAX
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movgt r7, REG_MAX
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addgt REG_CLIP, REG_CLIP, #1
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cmp r7, #-1073741824
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movlt r7, #-1073741824
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addlt REG_CLIP, REG_CLIP, #1
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movs r7, r7, asr #15
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adc r7, r7, #0
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strh r7, [SAMPLES], #4
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mov r3, #14
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.Loop_start_2:
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ldr r8, [WINDOW], #4
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ldr r9, [B0], #4
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mul r7, r5, r6
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ldr r5, [WINDOW], #4
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ldr r6, [B0], #4
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mul r10, r8, r9
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ldr r8, [WINDOW], #4
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ldr r9, [B0], #4
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mla r7, r5, r6, r7
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ldr r5, [WINDOW], #4
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ldr r6, [B0], #4
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mla r10, r8, r9, r10
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ldr r8, [WINDOW], #4
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ldr r9, [B0], #4
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mla r7, r5, r6, r7
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ldr r5, [WINDOW], #4
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ldr r6, [B0], #4
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mla r10, r8, r9, r10
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ldr r8, [WINDOW], #4
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ldr r9, [B0], #4
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mla r7, r5, r6, r7
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ldr r5, [WINDOW], #4
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ldr r6, [B0], #4
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mla r10, r8, r9, r10
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ldr r8, [WINDOW], #4
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ldr r9, [B0], #4
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mla r7, r5, r6, r7
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ldr r5, [WINDOW], #4
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ldr r6, [B0], #4
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mla r10, r8, r9, r10
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ldr r8, [WINDOW], #4
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ldr r9, [B0], #4
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mla r7, r5, r6, r7
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ldr r5, [WINDOW], #4
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ldr r6, [B0], #4
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mla r10, r8, r9, r10
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ldr r8, [WINDOW], #4
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ldr r9, [B0], #4
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mla r7, r5, r6, r7
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ldr r5, [WINDOW], #4
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ldr r6, [B0], #4
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mla r10, r8, r9, r10
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ldr r8, [WINDOW], #68
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ldr r9, [B0], #-124
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mla r7, r5, r6, r7
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ldr r5, [WINDOW], #4
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ldr r6, [B0], #4
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mla r10, r8, r9, r10
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add r7, r7, r10
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cmp r7, REG_MAX
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movgt r7, REG_MAX
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addgt REG_CLIP, REG_CLIP, #1
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cmp r7, #-1073741824
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movlt r7, #-1073741824
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addlt REG_CLIP, REG_CLIP, #1
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movs r7, r7, asr #15
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adc r7, r7, #0
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strh r7, [SAMPLES], #4
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subs r3, r3, #1
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bne .Loop_start_2
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ldr r8, [WINDOW], #4
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ldr r9, [B0], #4
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mul r7, r5, r6
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ldr r5, [WINDOW], #4
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ldr r6, [B0], #4
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mul r10, r8, r9
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ldr r8, [WINDOW], #4
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ldr r9, [B0], #4
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mla r7, r5, r6, r7
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ldr r5, [WINDOW], #4
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ldr r6, [B0], #4
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mla r10, r8, r9, r10
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ldr r8, [WINDOW], #4
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ldr r9, [B0], #4
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mla r7, r5, r6, r7
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ldr r5, [WINDOW], #4
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ldr r6, [B0], #4
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mla r10, r8, r9, r10
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ldr r8, [WINDOW], #4
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ldr r9, [B0], #4
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mla r7, r5, r6, r7
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ldr r5, [WINDOW], #4
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ldr r6, [B0], #4
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mla r10, r8, r9, r10
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ldr r8, [WINDOW], #4
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ldr r9, [B0], #4
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mla r7, r5, r6, r7
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ldr r5, [WINDOW], #4
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ldr r6, [B0], #4
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mla r10, r8, r9, r10
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ldr r8, [WINDOW], #4
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ldr r9, [B0], #4
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mla r7, r5, r6, r7
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ldr r5, [WINDOW], #4
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ldr r6, [B0], #4
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mla r10, r8, r9, r10
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ldr r8, [WINDOW], #4
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ldr r9, [B0], #4
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mla r7, r5, r6, r7
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ldr r5, [WINDOW], #4
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ldr r6, [B0], #4
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mla r10, r8, r9, r10
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ldr r8, [WINDOW]
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ldr r9, [B0]
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mla r7, r5, r6, r7
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mla r10, r8, r9, r10
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add r7, r7, r10
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cmp r7, REG_MAX
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movgt r7, REG_MAX
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addgt REG_CLIP, REG_CLIP, #1
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cmp r7, #-1073741824
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movlt r7, #-1073741824
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addlt REG_CLIP, REG_CLIP, #1
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movs r7, r7, asr #15
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adc r7, r7, #0
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strh r7, [SAMPLES]
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mov r0, REG_CLIP
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ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, pc}
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