Sir Richard d7372c2dc4 [NTOS]: Enable usage of ARM3 paged pool, up until Mm Phase 2. ... [NTOS]: Re-arrange some of the init code, now that we have access to ARM3 paged pool early-on. Move more code to ARM3::INIT in its right place. [NTOS]: Enable using the ARM3 PFN Database, getting rid of the old ReactOS PFN database. Should reduce physical memory usage now that we don't have two copies anymore. [NTOS]: Fix the ARM3 PFN Datbase initialization code. [NTOS]: Get rid of MiInitializePageList, use MiGetPfnEntryOffset instead of hard-coded pointer math in freelist.c. This is the last big low-level Mm/ARM3 patch for a long, long time. svn path=/trunk/; revision=47627		2010-06-06 15:59:42 +00:00
..
arm	[NTOS]: MmSystemPageDirectory is an array of page directories, not just a value. On x86 there's just one page directory, but that's not the case on other architectures/PAE, so fix this bug.	2010-05-12 18:33:18 +00:00
i386	[NTOS]: Enable usage of ARM3 paged pool, up until Mm Phase 2.	2010-06-06 15:59:42 +00:00
.gitignore	Sync to trunk head (r42241)	2009-07-26 23:21:27 +00:00
contmem.c	[NTOS]: Fix a loop off-by-one when saving the page table index in contigious memory allocation PFNs. Spotted by Stefan100.	2010-06-06 13:42:19 +00:00
drvmgmt.c	[NTOS]: Read almost all the Memory Management variables into the system configuration vector. These includes pool limits, percentages, debugging flags, behavioral changes, and others.	2010-04-20 22:47:51 +00:00
dynamic.c	- Actually it seems MmGetPhysicalMemoryRanges uses the MmPhysicalMemoryBlock, so go ahead and implement that function.	2009-06-27 22:39:03 +00:00
expool.c	[NTOS]: Enable usage of ARM3 paged pool, up until Mm Phase 2.	2010-06-06 15:59:42 +00:00
hypermap.c	Do not crash, use valid kernel PTE.	2010-02-10 13:56:54 +00:00
iosup.c	[NTOS]: A PFN entry is not necessarily physical only if it is higher than MmHighestPhysicalPage. It can also be physical if it lies in a memory hole within the min-max physical page range. We can detect this by using our PFN Bitmap. So replace all "Is this an I/O mapping?" checks with a check on whether or not the PFN Database entry is NULL (which will check for us both of these statements). This ought to be a macro...	2010-06-06 14:15:18 +00:00
largepag.c	[NTOS]: Read almost all the Memory Management variables into the system configuration vector. These includes pool limits, percentages, debugging flags, behavioral changes, and others.	2010-04-20 22:47:51 +00:00
mdlsup.c	[NTOS]: A PFN entry is not necessarily physical only if it is higher than MmHighestPhysicalPage. It can also be physical if it lies in a memory hole within the min-max physical page range. We can detect this by using our PFN Bitmap. So replace all "Is this an I/O mapping?" checks with a check on whether or not the PFN Database entry is NULL (which will check for us both of these statements). This ought to be a macro...	2010-06-06 14:15:18 +00:00
miarm.h	[NTOS]: Don't use MmAllocPage for the first paged pool PDE, instead, use MiRemoveZeroPage.	2010-06-06 14:13:35 +00:00
mmdbg.c	- Fix a comment and remove a superfluous extern.	2010-06-06 14:42:03 +00:00
mminit.c	[NTOS]: Enable usage of ARM3 paged pool, up until Mm Phase 2.	2010-06-06 15:59:42 +00:00
mmsup.c	[NTOS]: Make MM init read MmProductType to determine what SKU of ReactOS this is, instead of assuming Server. If you want to go back to the old behavior, you need to change "WinNT" to "ServerNT" in the hivesys under Product Type.	2010-02-20 21:48:36 +00:00
ncache.c	Do not crash, use valid kernel PTE.	2010-02-10 13:56:54 +00:00
pagfault.c	[NTOS]: Silence more debug spew.	2010-06-06 04:37:53 +00:00
pfnlist.c	[NTOS]: Implement MiRemoveZeroPage and MiZeroPhysicalPage.	2010-06-06 14:12:28 +00:00
pool.c	[NTOS]: Kill some debug spew.	2010-06-06 00:49:26 +00:00
procsup.c	Testers: Please test this build.	2010-06-04 17:49:36 +00:00
sysldr.c	[NTOS]: Another one bites the dust, another one bites the dust. And another one gone and another one gone. Another one bites the dust, yeah. Out of the doorway the bullets rip, Repeating to the sound of the beat.	2010-06-06 14:24:18 +00:00
syspte.c	On amd64 the NextEntry member of MMPTE_LIST has 32 bits, but 36 would be required to cover the whole pte space. Therefore use MmSystemPtesStart[SystemPtePoolType] as base for the pfn linked list instead of MmSystemPteBase, which is set to PTE_BASE.	2009-11-16 19:35:36 +00:00
virtual.c	[NTOS]: Kill debug spew.	2010-06-05 19:17:21 +00:00