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cf7fc816a1
- start implementing HDAUDIO Bus driver - based heavily on Haiku exellent driver svn path=/trunk/; revision=68311
179 lines
5.8 KiB
C
179 lines
5.8 KiB
C
/*
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* Copyright 2007-2012, Haiku, Inc. All Rights Reserved.
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* Distributed under the terms of the MIT License.
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*
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* Authors:
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* Ithamar Adema, ithamar AT unet DOT nl
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* Axel Dörfler, axeld@pinc-software.de
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*/
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#ifndef HDAC_REGS_H
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#define HDAC_REGS_H
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#ifndef __REACTOS__
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#include <SupportDefs.h>
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#endif
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/* Controller register definitions */
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#define HDAC_GLOBAL_CAP 0x00 // 16bits, GCAP
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#define GLOBAL_CAP_OUTPUT_STREAMS(cap) (((cap) >> 12) & 15)
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#define GLOBAL_CAP_INPUT_STREAMS(cap) (((cap) >> 8) & 15)
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#define GLOBAL_CAP_BIDIR_STREAMS(cap) (((cap) >> 3) & 15)
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#define GLOBAL_CAP_NUM_SDO(cap) ((((cap) >> 1) & 3) ? (cap & 6) : 1)
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#define GLOBAL_CAP_64BIT(cap) (((cap) & 1) != 0)
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#define HDAC_VERSION_MINOR 0x02 // 8bits, VMIN
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#define HDAC_VERSION_MAJOR 0x03 // 8bits, VMAJ
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#define HDAC_GLOBAL_CONTROL 0x08 // 32bits, GCTL
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#define GLOBAL_CONTROL_UNSOLICITED (1 << 8)
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// accept unsolicited responses
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#define GLOBAL_CONTROL_FLUSH (1 << 1)
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#define GLOBAL_CONTROL_RESET (1 << 0)
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#define HDAC_WAKE_ENABLE 0x0c // 16bits, WAKEEN
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#define HDAC_WAKE_ENABLE_MASK 0x7fff
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#define HDAC_STATE_STATUS 0x0e // 16bits, STATESTS
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#define HDAC_INTR_CONTROL 0x20 // 32bits, INTCTL
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#define INTR_CONTROL_GLOBAL_ENABLE (1U << 31)
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#define INTR_CONTROL_CONTROLLER_ENABLE (1 << 30)
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#define HDAC_INTR_STATUS 0x24 // 32bits, INTSTS
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#define INTR_STATUS_GLOBAL (1U << 31)
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#define INTR_STATUS_CONTROLLER (1 << 30)
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#define INTR_STATUS_STREAM_MASK 0x3fffffff
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#define HDAC_CORB_BASE_LOWER 0x40 // 32bits, CORBLBASE
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#define HDAC_CORB_BASE_UPPER 0x44 // 32bits, CORBUBASE
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#define HDAC_CORB_WRITE_POS 0x48 // 16bits, CORBWP
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#define HDAC_CORB_WRITE_POS_MASK 0xff
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#define HDAC_CORB_READ_POS 0x4a // 16bits, CORBRP
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#define CORB_READ_POS_RESET (1 << 15)
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#define HDAC_CORB_CONTROL 0x4c // 8bits, CORBCTL
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#define HDAC_CORB_CONTROL_MASK 0x3
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#define CORB_CONTROL_RUN (1 << 1)
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#define CORB_CONTROL_MEMORY_ERROR_INTR (1 << 0)
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#define HDAC_CORB_STATUS 0x4d // 8bits, CORBSTS
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#define CORB_STATUS_MEMORY_ERROR (1 << 0)
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#define HDAC_CORB_SIZE 0x4e // 8bits, CORBSIZE
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#define HDAC_CORB_SIZE_MASK 0x3
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#define CORB_SIZE_CAP_2_ENTRIES (1 << 4)
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#define CORB_SIZE_CAP_16_ENTRIES (1 << 5)
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#define CORB_SIZE_CAP_256_ENTRIES (1 << 6)
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#define CORB_SIZE_2_ENTRIES 0x00 // 8 byte
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#define CORB_SIZE_16_ENTRIES 0x01 // 64 byte
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#define CORB_SIZE_256_ENTRIES 0x02 // 1024 byte
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#define HDAC_RIRB_BASE_LOWER 0x50 // 32bits, RIRBLBASE
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#define HDAC_RIRB_BASE_UPPER 0x54 // 32bits, RIRBUBASE
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#define HDAC_RIRB_WRITE_POS 0x58 // 16bits, RIRBWP
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#define RIRB_WRITE_POS_RESET (1 << 15)
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#define HDAC_RESPONSE_INTR_COUNT 0x5a // 16bits, RINTCNT
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#define HDAC_RESPONSE_INTR_COUNT_MASK 0xff
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#define HDAC_RIRB_CONTROL 0x5c // 8bits, RIRBCTL
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#define HDAC_RIRB_CONTROL_MASK 0x7
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#define RIRB_CONTROL_OVERRUN_INTR (1 << 2)
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#define RIRB_CONTROL_DMA_ENABLE (1 << 1)
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#define RIRB_CONTROL_RESPONSE_INTR (1 << 0)
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#define HDAC_RIRB_STATUS 0x5d // 8bits, RIRBSTS
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#define RIRB_STATUS_OVERRUN (1 << 2)
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#define RIRB_STATUS_RESPONSE (1 << 0)
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#define HDAC_RIRB_SIZE 0x5e // 8bits, RIRBSIZE
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#define HDAC_RIRB_SIZE_MASK 0x3
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#define RIRB_SIZE_CAP_2_ENTRIES (1 << 4)
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#define RIRB_SIZE_CAP_16_ENTRIES (1 << 5)
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#define RIRB_SIZE_CAP_256_ENTRIES (1 << 6)
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#define RIRB_SIZE_2_ENTRIES 0x00
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#define RIRB_SIZE_16_ENTRIES 0x01
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#define RIRB_SIZE_256_ENTRIES 0x02
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#define HDAC_DMA_POSITION_BASE_LOWER 0x70 // 32bits, DPLBASE
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#define HDAC_DMA_POSITION_BASE_UPPER 0x74 // 32bits, DPUBASE
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#define DMA_POSITION_ENABLED 1
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/* Stream Descriptor Registers */
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#define HDAC_STREAM_BASE 0x80
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#define HDAC_STREAM_SIZE 0x20
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#define HDAC_STREAM_CONTROL0 0x00 // 8bits, CTL0
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#define CONTROL0_RESET (1 << 0)
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#define CONTROL0_RUN (1 << 1)
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#define CONTROL0_BUFFER_COMPLETED_INTR (1 << 2)
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#define CONTROL0_FIFO_ERROR_INTR (1 << 3)
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#define CONTROL0_DESCRIPTOR_ERROR_INTR (1 << 4)
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#define HDAC_STREAM_CONTROL1 0x01 // 8bits, CTL1
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#define HDAC_STREAM_CONTROL2 0x02 // 8bits, CTL2
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#define CONTROL2_STREAM_MASK 0xf0
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#define CONTROL2_STREAM_SHIFT 4
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#define CONTROL2_BIDIR (1 << 3)
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#define CONTROL2_TRAFFIC_PRIORITY (1 << 2)
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#define CONTROL2_STRIPE_SDO_MASK 0x03
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#define HDAC_STREAM_STATUS 0x03 // 8bits, STS
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#define STATUS_BUFFER_COMPLETED (1 << 2)
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#define STATUS_FIFO_ERROR (1 << 3)
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#define STATUS_DESCRIPTOR_ERROR (1 << 4)
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#define STATUS_FIFO_READY (1 << 5)
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#define HDAC_STREAM_POSITION 0x04 // 32bits, LPIB
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#define HDAC_STREAM_BUFFER_SIZE 0x08 // 32bits, CBL
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#define HDAC_STREAM_LAST_VALID 0x0c // 16bits, LVI
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#define HDAC_STREAM_FIFO_SIZE 0x10 // 16bits, FIFOS
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#define HDAC_STREAM_FORMAT 0x12 // 16bits, FMT
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#define FORMAT_8BIT (0 << 4)
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#define FORMAT_16BIT (1 << 4)
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#define FORMAT_20BIT (2 << 4)
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#define FORMAT_24BIT (3 << 4)
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#define FORMAT_32BIT (4 << 4)
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#define FORMAT_44_1_BASE_RATE (1 << 14)
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#define FORMAT_MULTIPLY_RATE_SHIFT 11
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#define FORMAT_DIVIDE_RATE_SHIFT 8
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#define HDAC_STREAM_BUFFERS_BASE_LOWER 0x18 // 32bits, BDPL
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#define HDAC_STREAM_BUFFERS_BASE_UPPER 0x1c // 32bits, BDPU
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/* PCI space register definitions */
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#define PCI_HDA_TCSEL 0x44
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#define PCI_HDA_TCSEL_MASK 0xf8
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#define ATI_HDA_MISC_CNTR2 0x42
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#define ATI_HDA_MISC_CNTR2_MASK 0xf8
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#define ATI_HDA_ENABLE_SNOOP 0x02
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#define NVIDIA_HDA_OSTRM_COH 0x4c
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#define NVIDIA_HDA_ISTRM_COH 0x4d
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#define NVIDIA_HDA_ENABLE_COHBIT 0x01
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#define NVIDIA_HDA_TRANSREG 0x4e
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#define NVIDIA_HDA_TRANSREG_MASK 0xf0
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#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
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#define INTEL_SCH_HDA_DEVC 0x78
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#define INTEL_SCH_HDA_DEVC_SNOOP 0x800
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#ifndef __REACTOS__
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typedef uint32 corb_t;
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typedef struct {
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uint32 response;
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uint32 flags;
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} rirb_t;
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#endif
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#define RESPONSE_FLAGS_CODEC_MASK 0x0000000f
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#define RESPONSE_FLAGS_UNSOLICITED (1 << 4)
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#ifndef __REACTOS__
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typedef struct {
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uint32 lower;
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uint32 upper;
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uint32 length;
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uint32 ioc;
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} bdl_entry_t;
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#endif
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#endif /* HDAC_REGS_H */
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