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eae27787e5
svn path=/branches/shell-experiments/; revision=65354
816 lines
25 KiB
C
816 lines
25 KiB
C
/*
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* Fast486 386/486 CPU Emulation Library
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* common.c
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*
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* Copyright (C) 2014 Aleksandar Andrejevic <theflash AT sdf DOT lonestar DOT org>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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/* INCLUDES *******************************************************************/
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#include <windef.h>
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// #define NDEBUG
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#include <debug.h>
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#include <fast486.h>
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#include "common.h"
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/* PUBLIC FUNCTIONS ***********************************************************/
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BOOLEAN
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Fast486ReadMemory(PFAST486_STATE State,
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FAST486_SEG_REGS SegmentReg,
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ULONG Offset,
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BOOLEAN InstFetch,
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PVOID Buffer,
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ULONG Size)
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{
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ULONG LinearAddress;
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PFAST486_SEG_REG CachedDescriptor;
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ASSERT(SegmentReg < FAST486_NUM_SEG_REGS);
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/* Get the cached descriptor */
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CachedDescriptor = &State->SegmentRegs[SegmentReg];
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if ((Offset + Size - 1) > CachedDescriptor->Limit)
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{
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/* Read beyond limit */
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Fast486Exception(State, FAST486_EXCEPTION_GP);
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return FALSE;
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}
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/* Check for protected mode */
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if (State->ControlRegisters[FAST486_REG_CR0] & FAST486_CR0_PE)
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{
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/* Privilege checks */
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if (!CachedDescriptor->Present)
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{
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Fast486Exception(State, FAST486_EXCEPTION_NP);
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return FALSE;
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}
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if ((!InstFetch && (CachedDescriptor->Rpl > CachedDescriptor->Dpl))
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|| (Fast486GetCurrentPrivLevel(State) > CachedDescriptor->Dpl))
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{
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Fast486Exception(State, FAST486_EXCEPTION_GP);
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return FALSE;
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}
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if (InstFetch)
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{
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if (!CachedDescriptor->Executable)
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{
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/* Data segment not executable */
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Fast486Exception(State, FAST486_EXCEPTION_GP);
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return FALSE;
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}
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}
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else
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{
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if (CachedDescriptor->Executable && (!CachedDescriptor->ReadWrite))
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{
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/* Code segment not readable */
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Fast486Exception(State, FAST486_EXCEPTION_GP);
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return FALSE;
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}
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}
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}
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/* Find the linear address */
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LinearAddress = CachedDescriptor->Base + Offset;
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#ifndef FAST486_NO_PREFETCH
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if (InstFetch && ((Offset + FAST486_CACHE_SIZE - 1) <= CachedDescriptor->Limit))
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{
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State->PrefetchAddress = LinearAddress;
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if ((State->ControlRegisters[FAST486_REG_CR0] & FAST486_CR0_PG)
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&& (PAGE_OFFSET(State->PrefetchAddress) > (FAST486_PAGE_SIZE - FAST486_CACHE_SIZE)))
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{
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/* We mustn't prefetch across a page boundary */
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State->PrefetchAddress = PAGE_ALIGN(State->PrefetchAddress)
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| (FAST486_PAGE_SIZE - FAST486_CACHE_SIZE);
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if ((LinearAddress - State->PrefetchAddress + Size) >= FAST486_CACHE_SIZE)
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{
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/* We can't prefetch without possibly violating page permissions */
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State->PrefetchValid = FALSE;
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return Fast486ReadLinearMemory(State, LinearAddress, Buffer, Size);
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}
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}
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/* Prefetch */
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if (Fast486ReadLinearMemory(State,
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State->PrefetchAddress,
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State->PrefetchCache,
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FAST486_CACHE_SIZE))
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{
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State->PrefetchValid = TRUE;
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RtlMoveMemory(Buffer,
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&State->PrefetchCache[LinearAddress - State->PrefetchAddress],
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Size);
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return TRUE;
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}
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else
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{
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State->PrefetchValid = FALSE;
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return FALSE;
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}
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}
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else
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#endif
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{
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/* Read from the linear address */
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return Fast486ReadLinearMemory(State, LinearAddress, Buffer, Size);
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}
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}
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BOOLEAN
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Fast486WriteMemory(PFAST486_STATE State,
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FAST486_SEG_REGS SegmentReg,
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ULONG Offset,
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PVOID Buffer,
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ULONG Size)
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{
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ULONG LinearAddress;
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PFAST486_SEG_REG CachedDescriptor;
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ASSERT(SegmentReg < FAST486_NUM_SEG_REGS);
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/* Get the cached descriptor */
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CachedDescriptor = &State->SegmentRegs[SegmentReg];
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if ((Offset + Size - 1) > CachedDescriptor->Limit)
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{
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/* Write beyond limit */
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Fast486Exception(State, FAST486_EXCEPTION_GP);
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return FALSE;
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}
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/* Check for protected mode */
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if (State->ControlRegisters[FAST486_REG_CR0] & FAST486_CR0_PE)
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{
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/* Privilege checks */
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if (!CachedDescriptor->Present)
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{
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Fast486Exception(State, FAST486_EXCEPTION_NP);
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return FALSE;
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}
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if ((CachedDescriptor->Rpl > CachedDescriptor->Dpl)
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|| (Fast486GetCurrentPrivLevel(State) > CachedDescriptor->Dpl))
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{
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Fast486Exception(State, FAST486_EXCEPTION_GP);
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return FALSE;
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}
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if (CachedDescriptor->Executable)
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{
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/* Code segment not writable */
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Fast486Exception(State, FAST486_EXCEPTION_GP);
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return FALSE;
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}
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else if (!CachedDescriptor->ReadWrite)
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{
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/* Data segment not writeable */
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Fast486Exception(State, FAST486_EXCEPTION_GP);
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return FALSE;
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}
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}
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/* Find the linear address */
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LinearAddress = CachedDescriptor->Base + Offset;
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#ifndef FAST486_NO_PREFETCH
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if (State->PrefetchValid
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&& (LinearAddress >= State->PrefetchAddress)
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&& ((LinearAddress + Size) <= (State->PrefetchAddress + FAST486_CACHE_SIZE)))
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{
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/* Update the prefetch */
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RtlMoveMemory(&State->PrefetchCache[LinearAddress - State->PrefetchAddress],
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Buffer,
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min(Size, FAST486_CACHE_SIZE + State->PrefetchAddress - LinearAddress));
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}
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#endif
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/* Write to the linear address */
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return Fast486WriteLinearMemory(State, LinearAddress, Buffer, Size);
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}
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static inline BOOLEAN
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FASTCALL
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Fast486GetIntVector(PFAST486_STATE State,
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UCHAR Number,
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PFAST486_IDT_ENTRY IdtEntry)
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{
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/* Check for protected mode */
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if (State->ControlRegisters[FAST486_REG_CR0] & FAST486_CR0_PE)
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{
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/* Read from the IDT */
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if (!Fast486ReadLinearMemory(State,
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State->Idtr.Address
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+ Number * sizeof(*IdtEntry),
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IdtEntry,
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sizeof(*IdtEntry)))
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{
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/* Exception occurred */
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return FALSE;
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}
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}
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else
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{
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/* Read from the real-mode IVT */
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ULONG FarPointer;
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/* Paging is always disabled in real mode */
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State->MemReadCallback(State,
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State->Idtr.Address
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+ Number * sizeof(FarPointer),
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&FarPointer,
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sizeof(FarPointer));
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/* Fill a fake IDT entry */
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IdtEntry->Offset = LOWORD(FarPointer);
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IdtEntry->Selector = HIWORD(FarPointer);
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IdtEntry->Zero = 0;
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IdtEntry->Type = FAST486_IDT_INT_GATE;
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IdtEntry->Storage = FALSE;
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IdtEntry->Dpl = 0;
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IdtEntry->Present = TRUE;
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IdtEntry->OffsetHigh = 0;
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}
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return TRUE;
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}
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static inline BOOLEAN
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FASTCALL
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Fast486InterruptInternal(PFAST486_STATE State,
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PFAST486_IDT_ENTRY IdtEntry)
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{
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USHORT SegmentSelector = IdtEntry->Selector;
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ULONG Offset = MAKELONG(IdtEntry->Offset, IdtEntry->OffsetHigh);
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ULONG GateType = IdtEntry->Type;
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BOOLEAN GateSize = (GateType == FAST486_IDT_INT_GATE_32) ||
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(GateType == FAST486_IDT_TRAP_GATE_32);
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BOOLEAN Success = FALSE;
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ULONG OldPrefixFlags = State->PrefixFlags;
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/* Check for protected mode */
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if (State->ControlRegisters[FAST486_REG_CR0] & FAST486_CR0_PE)
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{
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FAST486_TSS Tss;
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USHORT OldSs = State->SegmentRegs[FAST486_REG_SS].Selector;
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ULONG OldEsp = State->GeneralRegs[FAST486_REG_ESP].Long;
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if (GateType == FAST486_TASK_GATE_SIGNATURE)
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{
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/* Task call */
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return Fast486TaskSwitch(State, FAST486_TASK_CALL, IdtEntry->Selector);
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}
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if (GateSize != (State->SegmentRegs[FAST486_REG_CS].Size))
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{
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/* The gate size doesn't match the current operand size, so set the OPSIZE flag. */
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State->PrefixFlags |= FAST486_PREFIX_OPSIZE;
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}
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/* Check if the interrupt handler is more privileged */
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if (Fast486GetCurrentPrivLevel(State) > GET_SEGMENT_RPL(SegmentSelector))
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{
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/* Read the TSS */
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if (!Fast486ReadLinearMemory(State,
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State->TaskReg.Base,
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&Tss,
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sizeof(Tss)))
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{
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/* Exception occurred */
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goto Cleanup;
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}
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/* Switch to the new privilege level */
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State->Cpl = GET_SEGMENT_RPL(SegmentSelector);
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/* Check the new (higher) privilege level */
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switch (State->Cpl)
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{
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case 0:
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{
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if (!Fast486LoadSegment(State, FAST486_REG_SS, Tss.Ss0))
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{
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/* Exception occurred */
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goto Cleanup;
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}
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State->GeneralRegs[FAST486_REG_ESP].Long = Tss.Esp0;
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break;
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}
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case 1:
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{
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if (!Fast486LoadSegment(State, FAST486_REG_SS, Tss.Ss1))
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{
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/* Exception occurred */
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goto Cleanup;
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}
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State->GeneralRegs[FAST486_REG_ESP].Long = Tss.Esp1;
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break;
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}
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case 2:
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{
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if (!Fast486LoadSegment(State, FAST486_REG_SS, Tss.Ss2))
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{
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/* Exception occurred */
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goto Cleanup;
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}
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State->GeneralRegs[FAST486_REG_ESP].Long = Tss.Esp2;
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break;
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}
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default:
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{
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/* Should never reach here! */
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ASSERT(FALSE);
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}
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}
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/* Push SS selector */
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if (!Fast486StackPush(State, OldSs)) goto Cleanup;
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/* Push stack pointer */
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if (!Fast486StackPush(State, OldEsp)) goto Cleanup;
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}
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}
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else
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{
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if (State->SegmentRegs[FAST486_REG_CS].Size)
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{
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/* Set OPSIZE, because INT always pushes 16-bit values in real mode */
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State->PrefixFlags |= FAST486_PREFIX_OPSIZE;
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}
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}
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/* Push EFLAGS */
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if (!Fast486StackPush(State, State->Flags.Long)) goto Cleanup;
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/* Push CS selector */
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if (!Fast486StackPush(State, State->SegmentRegs[FAST486_REG_CS].Selector)) goto Cleanup;
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/* Push the instruction pointer */
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if (!Fast486StackPush(State, State->InstPtr.Long)) goto Cleanup;
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if ((GateType == FAST486_IDT_INT_GATE) || (GateType == FAST486_IDT_INT_GATE_32))
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{
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/* Disable interrupts after a jump to an interrupt gate handler */
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State->Flags.If = FALSE;
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}
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/* Load new CS */
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if (!Fast486LoadSegment(State, FAST486_REG_CS, SegmentSelector))
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{
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/* An exception occurred during the jump */
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goto Cleanup;
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}
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if (GateSize)
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{
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/* 32-bit code segment, use EIP */
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State->InstPtr.Long = Offset;
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}
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else
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{
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/* 16-bit code segment, use IP */
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State->InstPtr.LowWord = LOWORD(Offset);
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}
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Success = TRUE;
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Cleanup:
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/* Restore the prefix flags */
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State->PrefixFlags = OldPrefixFlags;
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return Success;
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}
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BOOLEAN
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FASTCALL
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Fast486PerformInterrupt(PFAST486_STATE State,
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UCHAR Number)
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{
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FAST486_IDT_ENTRY IdtEntry;
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/* Get the interrupt vector */
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if (!Fast486GetIntVector(State, Number, &IdtEntry))
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{
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/* Exception occurred */
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return FALSE;
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}
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/* Perform the interrupt */
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if (!Fast486InterruptInternal(State, &IdtEntry))
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{
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/* Exception occurred */
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return FALSE;
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}
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return TRUE;
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}
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VOID
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FASTCALL
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Fast486ExceptionWithErrorCode(PFAST486_STATE State,
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FAST486_EXCEPTIONS ExceptionCode,
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ULONG ErrorCode)
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{
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/* Increment the exception count */
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State->ExceptionCount++;
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/* Check if the exception occurred more than once */
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if (State->ExceptionCount > 1)
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{
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/* Then this is a double fault */
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ExceptionCode = FAST486_EXCEPTION_DF;
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}
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/* Check if this is a triple fault */
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if (State->ExceptionCount == 3)
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{
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DPRINT("Fast486ExceptionWithErrorCode(%04X:%08X) -- Triple fault\n",
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State->SegmentRegs[FAST486_REG_CS].Selector,
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State->InstPtr.Long);
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/* Reset the CPU */
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Fast486Reset(State);
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return;
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}
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/* Clear the prefix flags */
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State->PrefixFlags = 0;
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/* Restore the IP to the saved IP */
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State->InstPtr = State->SavedInstPtr;
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/* Perform the interrupt */
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if (!Fast486PerformInterrupt(State, ExceptionCode))
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{
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/*
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* If this function failed, that means Fast486Exception
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* was called again, so just return in this case.
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*/
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return;
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}
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if (EXCEPTION_HAS_ERROR_CODE(ExceptionCode)
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&& (State->ControlRegisters[FAST486_REG_CR0] & FAST486_CR0_PE))
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{
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/* Push the error code */
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if (!Fast486StackPush(State, ErrorCode))
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{
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/*
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* If this function failed, that means Fast486Exception
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* was called again, so just return in this case.
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*/
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return;
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}
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}
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/* Reset the exception count */
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State->ExceptionCount = 0;
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}
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BOOLEAN
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FASTCALL
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Fast486TaskSwitch(PFAST486_STATE State, FAST486_TASK_SWITCH_TYPE Type, USHORT Selector)
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{
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ULONG NewTssAddress;
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ULONG NewTssLimit;
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FAST486_TSS OldTss;
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FAST486_TSS NewTss;
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FAST486_SYSTEM_DESCRIPTOR NewTssDescriptor;
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/* Read the old TSS */
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if (!Fast486ReadLinearMemory(State,
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State->TaskReg.Base,
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&OldTss,
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sizeof(OldTss)))
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{
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/* Exception occurred */
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return FALSE;
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}
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/* If this is a task return, use the linked previous selector */
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if (Type == FAST486_TASK_RETURN) Selector = LOWORD(OldTss.Link);
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/* Make sure the entry exists in the GDT (not LDT!) */
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if ((GET_SEGMENT_INDEX(Selector) == 0)
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|| (Selector & SEGMENT_TABLE_INDICATOR)
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|| GET_SEGMENT_INDEX(Selector) >= (State->Gdtr.Size + 1))
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{
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Fast486ExceptionWithErrorCode(State, FAST486_EXCEPTION_TS, Selector);
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return FALSE;
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}
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/* Get the TSS descriptor from the GDT */
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if (!Fast486ReadLinearMemory(State,
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State->Gdtr.Address + GET_SEGMENT_INDEX(Selector),
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&NewTssDescriptor,
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sizeof(NewTssDescriptor)))
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{
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/* Exception occurred */
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return FALSE;
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}
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|
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if (!NewTssDescriptor.Present)
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{
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/* Incoming task TSS not present */
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Fast486ExceptionWithErrorCode(State, FAST486_EXCEPTION_NP, Selector);
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return FALSE;
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}
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/* Calculate the linear address of the new TSS */
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NewTssAddress = NewTssDescriptor.Base;
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NewTssAddress |= NewTssDescriptor.BaseMid << 16;
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NewTssAddress |= NewTssDescriptor.BaseHigh << 24;
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/* Calculate the limit of the new TSS */
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NewTssLimit = NewTssDescriptor.Limit | (NewTssDescriptor.LimitHigh << 16);
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if (NewTssDescriptor.Granularity)
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{
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NewTssLimit <<= 12;
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NewTssLimit |= 0x00000FFF;
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}
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if (NewTssLimit < sizeof(FAST486_TSS))
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{
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|
/* TSS limit too small */
|
|
Fast486ExceptionWithErrorCode(State, FAST486_EXCEPTION_TS, Selector);
|
|
return FALSE;
|
|
}
|
|
|
|
/*
|
|
* The incoming task shouldn't be busy if we're executing it as a
|
|
* new task, and it should be busy if we're returning to it.
|
|
*/
|
|
if (((NewTssDescriptor.Signature != FAST486_TSS_SIGNATURE)
|
|
|| (Type == FAST486_TASK_RETURN))
|
|
&& ((NewTssDescriptor.Signature != FAST486_BUSY_TSS_SIGNATURE)
|
|
|| (Type != FAST486_TASK_RETURN)))
|
|
{
|
|
Fast486ExceptionWithErrorCode(State, FAST486_EXCEPTION_GP, Selector);
|
|
return FALSE;
|
|
}
|
|
|
|
/* Read the new TSS */
|
|
if (!Fast486ReadLinearMemory(State,
|
|
NewTssAddress,
|
|
&NewTss,
|
|
sizeof(NewTss)))
|
|
{
|
|
/* Exception occurred */
|
|
return FALSE;
|
|
}
|
|
|
|
if (Type != FAST486_TASK_CALL)
|
|
{
|
|
/* Clear the busy bit of the outgoing task */
|
|
FAST486_SYSTEM_DESCRIPTOR OldTssDescriptor;
|
|
|
|
if (!Fast486ReadLinearMemory(State,
|
|
State->Gdtr.Address
|
|
+ GET_SEGMENT_INDEX(State->TaskReg.Selector),
|
|
&OldTssDescriptor,
|
|
sizeof(OldTssDescriptor)))
|
|
{
|
|
/* Exception occurred */
|
|
return FALSE;
|
|
}
|
|
|
|
OldTssDescriptor.Signature = FAST486_TSS_SIGNATURE;
|
|
|
|
if (!Fast486WriteLinearMemory(State,
|
|
State->Gdtr.Address
|
|
+ GET_SEGMENT_INDEX(State->TaskReg.Selector),
|
|
&OldTssDescriptor,
|
|
sizeof(OldTssDescriptor)))
|
|
{
|
|
/* Exception occurred */
|
|
return FALSE;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Store the link */
|
|
NewTss.Link = State->TaskReg.Selector;
|
|
}
|
|
|
|
/* Save the current task into the TSS */
|
|
OldTss.Cr3 = State->ControlRegisters[FAST486_REG_CR3];
|
|
OldTss.Eip = State->InstPtr.Long;
|
|
OldTss.Eflags = State->Flags.Long;
|
|
OldTss.Eax = State->GeneralRegs[FAST486_REG_EAX].Long;
|
|
OldTss.Ecx = State->GeneralRegs[FAST486_REG_ECX].Long;
|
|
OldTss.Edx = State->GeneralRegs[FAST486_REG_EDX].Long;
|
|
OldTss.Ebx = State->GeneralRegs[FAST486_REG_EBX].Long;
|
|
OldTss.Esp = State->GeneralRegs[FAST486_REG_ESP].Long;
|
|
OldTss.Ebp = State->GeneralRegs[FAST486_REG_EBP].Long;
|
|
OldTss.Esi = State->GeneralRegs[FAST486_REG_ESI].Long;
|
|
OldTss.Edi = State->GeneralRegs[FAST486_REG_EDI].Long;
|
|
OldTss.Es = State->SegmentRegs[FAST486_REG_ES].Selector;
|
|
OldTss.Cs = State->SegmentRegs[FAST486_REG_CS].Selector;
|
|
OldTss.Ss = State->SegmentRegs[FAST486_REG_SS].Selector;
|
|
OldTss.Ds = State->SegmentRegs[FAST486_REG_DS].Selector;
|
|
OldTss.Fs = State->SegmentRegs[FAST486_REG_FS].Selector;
|
|
OldTss.Gs = State->SegmentRegs[FAST486_REG_GS].Selector;
|
|
OldTss.Ldtr = State->Ldtr.Selector;
|
|
|
|
/* Write back the old TSS */
|
|
if (!Fast486WriteLinearMemory(State,
|
|
State->TaskReg.Base,
|
|
&OldTss,
|
|
sizeof(OldTss)))
|
|
{
|
|
/* Exception occurred */
|
|
return FALSE;
|
|
}
|
|
|
|
/* Mark the new task as busy */
|
|
NewTssDescriptor.Signature = FAST486_BUSY_TSS_SIGNATURE;
|
|
|
|
/* Write back the new TSS descriptor */
|
|
if (!Fast486WriteLinearMemory(State,
|
|
State->Gdtr.Address + GET_SEGMENT_INDEX(Selector),
|
|
&NewTssDescriptor,
|
|
sizeof(NewTssDescriptor)))
|
|
{
|
|
/* Exception occurred */
|
|
return FALSE;
|
|
}
|
|
|
|
/* Set the task switch bit */
|
|
State->ControlRegisters[FAST486_REG_CR0] |= FAST486_CR0_TS;
|
|
|
|
/* Load the task register with the new values */
|
|
State->TaskReg.Selector = Selector;
|
|
State->TaskReg.Base = NewTssAddress;
|
|
State->TaskReg.Limit = NewTssLimit;
|
|
|
|
/* Change the page directory */
|
|
State->ControlRegisters[FAST486_REG_CR3] = NewTss.Cr3;
|
|
|
|
/* Flush the TLB */
|
|
if (State->Tlb) RtlZeroMemory(State->Tlb, NUM_TLB_ENTRIES * sizeof(ULONG));
|
|
|
|
#ifndef FAST486_NO_PREFETCH
|
|
/* Context switching invalidates the prefetch */
|
|
State->PrefetchValid = FALSE;
|
|
#endif
|
|
|
|
/* Load the registers */
|
|
State->InstPtr.Long = State->SavedInstPtr.Long = NewTss.Eip;
|
|
State->Flags.Long = NewTss.Eflags;
|
|
State->GeneralRegs[FAST486_REG_EAX].Long = NewTss.Eax;
|
|
State->GeneralRegs[FAST486_REG_ECX].Long = NewTss.Ecx;
|
|
State->GeneralRegs[FAST486_REG_EDX].Long = NewTss.Edx;
|
|
State->GeneralRegs[FAST486_REG_EBX].Long = NewTss.Ebx;
|
|
State->GeneralRegs[FAST486_REG_ESP].Long = NewTss.Esp;
|
|
State->GeneralRegs[FAST486_REG_EBP].Long = NewTss.Ebp;
|
|
State->GeneralRegs[FAST486_REG_ESI].Long = NewTss.Esi;
|
|
State->GeneralRegs[FAST486_REG_EDI].Long = NewTss.Edi;
|
|
|
|
/* Set the NT flag if nesting */
|
|
if (Type == FAST486_TASK_CALL) State->Flags.Nt = TRUE;
|
|
|
|
if (GET_SEGMENT_INDEX(NewTss.Ldtr) != 0)
|
|
{
|
|
BOOLEAN Valid;
|
|
FAST486_SYSTEM_DESCRIPTOR GdtEntry;
|
|
|
|
if (NewTss.Ldtr & SEGMENT_TABLE_INDICATOR)
|
|
{
|
|
/* This selector doesn't point to the GDT */
|
|
Fast486ExceptionWithErrorCode(State, FAST486_EXCEPTION_TS, NewTss.Ldtr);
|
|
return FALSE;
|
|
}
|
|
|
|
if (!Fast486ReadDescriptorEntry(State,
|
|
NewTss.Ldtr,
|
|
&Valid,
|
|
(PFAST486_GDT_ENTRY)&GdtEntry))
|
|
{
|
|
/* Exception occurred */
|
|
return FALSE;
|
|
}
|
|
|
|
if (!Valid)
|
|
{
|
|
/* Invalid selector */
|
|
Fast486ExceptionWithErrorCode(State, FAST486_EXCEPTION_TS, NewTss.Ldtr);
|
|
return FALSE;
|
|
}
|
|
|
|
if (GdtEntry.Signature != FAST486_LDT_SIGNATURE)
|
|
{
|
|
/* This is not an LDT descriptor */
|
|
Fast486ExceptionWithErrorCode(State, FAST486_EXCEPTION_TS, NewTss.Ldtr);
|
|
return FALSE;
|
|
}
|
|
|
|
if (!GdtEntry.Present)
|
|
{
|
|
Fast486ExceptionWithErrorCode(State, FAST486_EXCEPTION_TS, NewTss.Ldtr);
|
|
return FALSE;
|
|
}
|
|
|
|
/* Update the LDTR */
|
|
State->Ldtr.Selector = NewTss.Ldtr;
|
|
State->Ldtr.Base = GdtEntry.Base | (GdtEntry.BaseMid << 16) | (GdtEntry.BaseHigh << 24);
|
|
State->Ldtr.Limit = GdtEntry.Limit | (GdtEntry.LimitHigh << 16);
|
|
|
|
if (GdtEntry.Granularity)
|
|
{
|
|
State->Ldtr.Limit <<= 12;
|
|
State->Ldtr.Limit |= 0x00000FFF;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* The LDT of this task is empty */
|
|
RtlZeroMemory(&State->Ldtr, sizeof(State->Ldtr));
|
|
}
|
|
|
|
/* Load the new segments */
|
|
if (!Fast486LoadSegmentInternal(State,
|
|
FAST486_REG_CS,
|
|
NewTss.Cs,
|
|
FAST486_EXCEPTION_TS))
|
|
{
|
|
return FALSE;
|
|
}
|
|
|
|
if (!Fast486LoadSegmentInternal(State,
|
|
FAST486_REG_SS,
|
|
NewTss.Ss,
|
|
FAST486_EXCEPTION_TS))
|
|
{
|
|
return FALSE;
|
|
}
|
|
|
|
if (!Fast486LoadSegmentInternal(State,
|
|
FAST486_REG_ES,
|
|
NewTss.Es,
|
|
FAST486_EXCEPTION_TS))
|
|
{
|
|
return FALSE;
|
|
}
|
|
|
|
if (!Fast486LoadSegmentInternal(State,
|
|
FAST486_REG_DS,
|
|
NewTss.Ds,
|
|
FAST486_EXCEPTION_TS))
|
|
{
|
|
return FALSE;
|
|
}
|
|
|
|
if (!Fast486LoadSegmentInternal(State,
|
|
FAST486_REG_FS,
|
|
NewTss.Fs,
|
|
FAST486_EXCEPTION_TS))
|
|
{
|
|
return FALSE;
|
|
}
|
|
|
|
if (!Fast486LoadSegmentInternal(State,
|
|
FAST486_REG_GS,
|
|
NewTss.Gs,
|
|
FAST486_EXCEPTION_TS))
|
|
{
|
|
return FALSE;
|
|
}
|
|
|
|
return TRUE;
|
|
}
|
|
|
|
/* EOF */
|