mirror of
https://github.com/reactos/reactos.git
synced 2024-08-22 03:12:51 +00:00
453 lines
9 KiB
C
453 lines
9 KiB
C
/*
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* COPYRIGHT: See COPYING in the top level directory
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* PROJECT: ReactOS kernel
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* FILE: hal/halppc/generic/irql.c
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* PURPOSE: Implements IRQLs
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* PROGRAMMER: David Welch (welch@cwcom.net)
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*/
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/* INCLUDES *****************************************************************/
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#include <hal.h>
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#define NDEBUG
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#include <debug.h>
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/* GLOBALS ******************************************************************/
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/*
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* FIXME: Use EISA_CONTROL STRUCTURE INSTEAD OF HARD-CODED OFFSETS
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*/
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typedef union
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{
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USHORT both;
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struct
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{
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UCHAR master;
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UCHAR slave;
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};
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}
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PIC_MASK;
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/*
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* PURPOSE: - Mask for HalEnableSystemInterrupt and HalDisableSystemInterrupt
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* - At startup enable timer and cascade
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*/
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#if defined(__GNUC__)
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static PIC_MASK pic_mask = {.both = 0xFFFA};
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#else
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static PIC_MASK pic_mask = { 0xFFFA };
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#endif
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/*
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* PURPOSE: Mask for disabling of acknowledged interrupts
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*/
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#if defined(__GNUC__)
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static PIC_MASK pic_mask_intr = {.both = 0x0000};
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#else
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static PIC_MASK pic_mask_intr = { 0 };
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#endif
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static ULONG HalpPendingInterruptCount[NR_IRQS];
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#define DIRQL_TO_IRQ(x) (PROFILE_LEVEL - x)
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#define IRQ_TO_DIRQL(x) (PROFILE_LEVEL - x)
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#ifdef _MSC_VER
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#define KiInterruptDispatch2(x, y)
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#else
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VOID NTAPI
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KiInterruptDispatch2 (ULONG Irq, KIRQL old_level);
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#endif
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/* FUNCTIONS ****************************************************************/
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#undef KeGetCurrentIrql
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KIRQL NTAPI KeGetCurrentIrql (VOID)
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/*
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* PURPOSE: Returns the current irq level
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* RETURNS: The current irq level
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*/
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{
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return(KeGetPcr()->Irql);
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}
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VOID NTAPI HalpInitPICs(VOID)
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{
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memset(HalpPendingInterruptCount, 0, sizeof(HalpPendingInterruptCount));
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/* Initialization sequence */
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WRITE_PORT_UCHAR((PUCHAR)0x20, 0x11);
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WRITE_PORT_UCHAR((PUCHAR)0xa0, 0x11);
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/* Start of hardware irqs (0x24) */
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WRITE_PORT_UCHAR((PUCHAR)0x21, IRQ_BASE);
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WRITE_PORT_UCHAR((PUCHAR)0xa1, IRQ_BASE + 8);
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/* 8259-1 is master */
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WRITE_PORT_UCHAR((PUCHAR)0x21, 0x4);
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/* 8259-2 is slave */
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WRITE_PORT_UCHAR((PUCHAR)0xa1, 0x2);
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/* 8086 mode */
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WRITE_PORT_UCHAR((PUCHAR)0x21, 0x1);
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WRITE_PORT_UCHAR((PUCHAR)0xa1, 0x1);
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/* Enable interrupts */
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WRITE_PORT_UCHAR((PUCHAR)0x21, 0xFF);
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WRITE_PORT_UCHAR((PUCHAR)0xa1, 0xFF);
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/* We can now enable interrupts */
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_enable();
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}
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VOID HalpEndSystemInterrupt(KIRQL Irql)
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/*
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* FUNCTION: Enable all irqs with higher priority.
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*/
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{
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const USHORT mask[] =
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{
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0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
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0x0000, 0x0000, 0x0000, 0x0000, 0x8000, 0xc000, 0xe000, 0xf000,
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0xf800, 0xfc00, 0xfe00, 0xff00, 0xff80, 0xffc0, 0xffe0, 0xfff0,
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0xfff8, 0xfffc, 0xfffe, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
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};
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/* Interrupts should be disable while enabling irqs of both pics */
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_disable();
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pic_mask_intr.both &= mask[Irql];
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WRITE_PORT_UCHAR((PUCHAR)0x21, (UCHAR)(pic_mask.master|pic_mask_intr.master));
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WRITE_PORT_UCHAR((PUCHAR)0xa1, (UCHAR)(pic_mask.slave|pic_mask_intr.slave));
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/* restore ints */
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_enable();
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}
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VOID
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HalpExecuteIrqs(KIRQL NewIrql)
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{
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ULONG IrqLimit, i;
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IrqLimit = min(PROFILE_LEVEL - NewIrql, NR_IRQS);
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/*
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* For each irq if there have been any deferred interrupts then now
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* dispatch them.
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*/
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for (i = 0; i < IrqLimit; i++)
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{
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if (HalpPendingInterruptCount[i] > 0)
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{
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KeGetPcr()->Irql = (KIRQL)IRQ_TO_DIRQL(i);
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while (HalpPendingInterruptCount[i] > 0)
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{
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/*
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* For each deferred interrupt execute all the handlers at DIRQL.
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*/
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HalpPendingInterruptCount[i]--;
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//HalpHardwareInt[i]();
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}
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//KeGetPcr()->Irql--;
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//HalpEndSystemInterrupt(KeGetPcr()->Irql);
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}
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}
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}
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VOID
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HalpLowerIrql(KIRQL NewIrql)
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{
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if (NewIrql >= PROFILE_LEVEL)
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{
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KeGetPcr()->Irql = NewIrql;
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return;
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}
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HalpExecuteIrqs(NewIrql);
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if (NewIrql >= DISPATCH_LEVEL)
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{
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KeGetPcr()->Irql = NewIrql;
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return;
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}
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KeGetPcr()->Irql = DISPATCH_LEVEL;
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if (((PKIPCR)KeGetPcr())->HalReserved[HAL_DPC_REQUEST])
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{
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((PKIPCR)KeGetPcr())->HalReserved[HAL_DPC_REQUEST] = FALSE;
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KiDispatchInterrupt();
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}
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KeGetPcr()->Irql = APC_LEVEL;
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if (NewIrql == APC_LEVEL)
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{
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return;
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}
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if (KeGetCurrentThread() != NULL &&
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KeGetCurrentThread()->ApcState.KernelApcPending)
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{
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KiDeliverApc(KernelMode, NULL, NULL);
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}
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KeGetPcr()->Irql = PASSIVE_LEVEL;
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}
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/**********************************************************************
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* NAME EXPORTED
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* KfLowerIrql
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*
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* DESCRIPTION
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* Restores the irq level on the current processor
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*
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* ARGUMENTS
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* NewIrql = Irql to lower to
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*
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* RETURN VALUE
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* None
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*
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* NOTES
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* Uses fastcall convention
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*/
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VOID FASTCALL
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KfLowerIrql (KIRQL NewIrql)
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{
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DPRINT("KfLowerIrql(NewIrql %d)\n", NewIrql);
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if (NewIrql > KeGetPcr()->Irql)
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{
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DbgPrint ("(%s:%d) NewIrql %x CurrentIrql %x\n",
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__FILE__, __LINE__, NewIrql, KeGetPcr()->Irql);
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KeBugCheck(IRQL_NOT_LESS_OR_EQUAL);
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for(;;);
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}
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HalpLowerIrql(NewIrql);
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}
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/**********************************************************************
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* NAME EXPORTED
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* KfRaiseIrql
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*
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* DESCRIPTION
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* Raises the hardware priority (irql)
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*
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* ARGUMENTS
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* NewIrql = Irql to raise to
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*
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* RETURN VALUE
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* previous irq level
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*
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* NOTES
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* Uses fastcall convention
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*/
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KIRQL FASTCALL
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KfRaiseIrql (KIRQL NewIrql)
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{
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KIRQL OldIrql;
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DPRINT("KfRaiseIrql(NewIrql %d)\n", NewIrql);
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if (NewIrql < KeGetPcr()->Irql)
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{
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DbgPrint ("%s:%d CurrentIrql %x NewIrql %x\n",
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__FILE__,__LINE__,KeGetPcr()->Irql,NewIrql);
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KeBugCheck (IRQL_NOT_GREATER_OR_EQUAL);
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for(;;);
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}
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OldIrql = KeGetPcr()->Irql;
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KeGetPcr()->Irql = NewIrql;
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return OldIrql;
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}
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/**********************************************************************
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* NAME EXPORTED
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* KeRaiseIrqlToDpcLevel
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*
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* DESCRIPTION
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* Raises the hardware priority (irql) to DISPATCH level
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*
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* ARGUMENTS
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* None
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*
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* RETURN VALUE
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* Previous irq level
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*
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* NOTES
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* Calls KfRaiseIrql
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*/
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KIRQL NTAPI
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KeRaiseIrqlToDpcLevel (VOID)
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{
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return KfRaiseIrql (DISPATCH_LEVEL);
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}
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/**********************************************************************
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* NAME EXPORTED
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* KeRaiseIrqlToSynchLevel
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*
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* DESCRIPTION
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* Raises the hardware priority (irql) to CLOCK2 level
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*
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* ARGUMENTS
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* None
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*
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* RETURN VALUE
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* Previous irq level
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*
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* NOTES
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* Calls KfRaiseIrql
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*/
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KIRQL NTAPI
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KeRaiseIrqlToSynchLevel (VOID)
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{
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return KfRaiseIrql (DISPATCH_LEVEL);
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}
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BOOLEAN NTAPI
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HalBeginSystemInterrupt (KIRQL Irql,
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ULONG Vector,
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PKIRQL OldIrql)
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{
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ULONG irq;
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if (Vector < IRQ_BASE || Vector >= IRQ_BASE + NR_IRQS)
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{
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return(FALSE);
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}
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irq = Vector - IRQ_BASE;
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pic_mask_intr.both |= ((1 << irq) & 0xfffe); // do not disable the timer interrupt
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if (irq < 8)
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{
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WRITE_PORT_UCHAR((PUCHAR)0x21, (UCHAR)(pic_mask.master|pic_mask_intr.master));
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WRITE_PORT_UCHAR((PUCHAR)0x20, 0x20);
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}
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else
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{
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WRITE_PORT_UCHAR((PUCHAR)0xa1, (UCHAR)(pic_mask.slave|pic_mask_intr.slave));
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/* Send EOI to the PICs */
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WRITE_PORT_UCHAR((PUCHAR)0x20,0x20);
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WRITE_PORT_UCHAR((PUCHAR)0xa0,0x20);
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}
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#if 0
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if (KeGetPcr()->Irql >= Irql)
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{
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HalpPendingInterruptCount[irq]++;
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return(FALSE);
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}
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#endif
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*OldIrql = KeGetPcr()->Irql;
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KeGetPcr()->Irql = Irql;
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return(TRUE);
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}
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VOID NTAPI HalEndSystemInterrupt (KIRQL Irql, ULONG Unknown2)
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/*
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* FUNCTION: Finish a system interrupt and restore the specified irq level.
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*/
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{
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HalpLowerIrql(Irql);
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HalpEndSystemInterrupt(Irql);
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}
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VOID
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NTAPI
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HalDisableSystemInterrupt(
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ULONG Vector,
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KIRQL Irql)
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{
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ULONG irq;
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if (Vector < IRQ_BASE || Vector >= IRQ_BASE + NR_IRQS)
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{
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ASSERT(FALSE);
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return;
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}
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irq = Vector - IRQ_BASE;
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pic_mask.both |= (1 << irq);
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if (irq < 8)
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{
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WRITE_PORT_UCHAR((PUCHAR)0x21, (UCHAR)(pic_mask.master|pic_mask_intr.slave));
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}
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else
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{
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WRITE_PORT_UCHAR((PUCHAR)0xa1, (UCHAR)(pic_mask.slave|pic_mask_intr.slave));
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}
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return;
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}
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BOOLEAN
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NTAPI
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HalEnableSystemInterrupt(
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ULONG Vector,
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KIRQL Irql,
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KINTERRUPT_MODE InterruptMode)
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{
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ULONG irq;
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if (Vector < IRQ_BASE || Vector >= IRQ_BASE + NR_IRQS)
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return FALSE;
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irq = Vector - IRQ_BASE;
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pic_mask.both &= ~(1 << irq);
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if (irq < 8)
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{
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WRITE_PORT_UCHAR((PUCHAR)0x21, (UCHAR)(pic_mask.master|pic_mask_intr.master));
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}
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else
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{
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WRITE_PORT_UCHAR((PUCHAR)0xa1, (UCHAR)(pic_mask.slave|pic_mask_intr.slave));
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}
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return TRUE;
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}
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VOID FASTCALL
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HalRequestSoftwareInterrupt(
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IN KIRQL Request)
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{
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switch (Request)
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{
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case APC_LEVEL:
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((PKIPCR)KeGetPcr())->HalReserved[HAL_APC_REQUEST] = TRUE;
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break;
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case DISPATCH_LEVEL:
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((PKIPCR)KeGetPcr())->HalReserved[HAL_DPC_REQUEST] = TRUE;
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break;
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default:
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DbgBreakPoint();
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}
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}
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VOID FASTCALL
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HalClearSoftwareInterrupt(
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IN KIRQL Request)
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{
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switch (Request)
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{
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case APC_LEVEL:
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((PKIPCR)KeGetPcr())->HalReserved[HAL_APC_REQUEST] = FALSE;
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break;
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case DISPATCH_LEVEL:
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((PKIPCR)KeGetPcr())->HalReserved[HAL_DPC_REQUEST] = FALSE;
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break;
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default:
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DbgBreakPoint();
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}
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}
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/* EOF */
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