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527f2f9057
* Create a branch for some evul shell experiments. svn path=/branches/shell-experiments/; revision=61927
308 lines
10 KiB
C
308 lines
10 KiB
C
/*
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* kernel internal memory managment definitions for amd64
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*/
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#pragma once
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/* Memory layout base addresses */
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#define MI_LOWEST_VAD_ADDRESS (PVOID)0x000000007FF00000ULL
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#define MI_HIGHEST_USER_ADDRESS (PVOID)0x000007FFFFFEFFFFULL
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#define MI_USER_PROBE_ADDRESS (PVOID)0x000007FFFFFF0000ULL
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#define MI_DEFAULT_SYSTEM_RANGE_START (PVOID)0xFFFF080000000000ULL
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#define MI_REAL_SYSTEM_RANGE_START 0xFFFF800000000000ULL
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#define MI_PAGE_TABLE_BASE 0xFFFFF68000000000ULL
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#define HYPER_SPACE 0xFFFFF70000000000ULL
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#define HYPER_SPACE_END 0xFFFFF77FFFFFFFFFULL
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#define MI_SHARED_SYSTEM_PAGE 0xFFFFF78000000000ULL
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#define MI_SYSTEM_CACHE_WS_START 0xFFFFF78000001000ULL
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#define MI_LOADER_MAPPINGS 0xFFFFF80000000000ULL
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#define MI_PAGED_SYSTEM_START 0xFFFFF88000000000ULL
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#define MI_PAGED_POOL_START (PVOID)0xFFFFF8A000000000ULL
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#define MI_PAGED_POOL_END 0xFFFFF8BFFFFFFFFFULL
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#define MI_SESSION_SPACE_START 0xFFFFF90000000000ULL
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#define MI_SESSION_VIEW_END 0xFFFFF97FFF000000ULL
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#define MI_SESSION_SPACE_END 0xFFFFF97FFFFFFFFFULL
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#define MM_SYSTEM_SPACE_START 0xFFFFF98000000000ULL
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#define MI_PFN_DATABASE 0xFFFFFA8000000000ULL
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#define MI_HIGHEST_SYSTEM_ADDRESS (PVOID)0xFFFFFFFFFFFFFFFFULL
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/* WOW64 address definitions */
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#define MM_HIGHEST_USER_ADDRESS_WOW64 0x7FFEFFFF
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#define MM_SYSTEM_RANGE_START_WOW64 0x80000000
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#define MI_DEBUG_MAPPING (PVOID)0xFFFFFFFF80000000ULL // FIXME
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#define MI_NON_PAGED_SYSTEM_START_MIN MM_SYSTEM_SPACE_START // FIXME
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#define MI_SYSTEM_PTE_START MM_SYSTEM_SPACE_START
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#define MI_SYSTEM_PTE_END (MI_SYSTEM_PTE_START + MI_NUMBER_SYSTEM_PTES * PAGE_SIZE - 1)
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#define MI_SYSTEM_PTE_BASE (PVOID)MiAddressToPte(KSEG0_BASE)
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#define MM_HIGHEST_VAD_ADDRESS (PVOID)((ULONG_PTR)MM_HIGHEST_USER_ADDRESS - (16 * PAGE_SIZE))
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#define MI_MAPPING_RANGE_START HYPER_SPACE
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#define MI_MAPPING_RANGE_END (MI_MAPPING_RANGE_START + MI_HYPERSPACE_PTES * PAGE_SIZE)
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#define MI_DUMMY_PTE (MI_MAPPING_RANGE_END + PAGE_SIZE)
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#define MI_VAD_BITMAP (MI_DUMMY_PTE + PAGE_SIZE)
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#define MI_WORKING_SET_LIST (MI_VAD_BITMAP + PAGE_SIZE)
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#define MI_NONPAGED_POOL_END 0
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/* Memory sizes */
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#define MI_MIN_PAGES_FOR_NONPAGED_POOL_TUNING ((255*1024*1024) >> PAGE_SHIFT)
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#define MI_MIN_PAGES_FOR_SYSPTE_TUNING ((19*1024*1024) >> PAGE_SHIFT)
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#define MI_MIN_PAGES_FOR_SYSPTE_BOOST ((32*1024*1024) >> PAGE_SHIFT)
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#define MI_MIN_PAGES_FOR_SYSPTE_BOOST_BOOST ((256*1024*1024) >> PAGE_SHIFT)
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#define MI_MIN_INIT_PAGED_POOLSIZE (32 * 1024 * 1024)
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#define MI_MAX_INIT_NONPAGED_POOL_SIZE (128ULL * 1024 * 1024 * 1024)
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#define MI_MAX_NONPAGED_POOL_SIZE (128ULL * 1024 * 1024 * 1024)
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#define MI_SYSTEM_VIEW_SIZE (16 * 1024 * 1024)
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#define MI_MIN_SECONDARY_COLORS 8
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#define MI_SECONDARY_COLORS 64
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#define MI_MAX_SECONDARY_COLORS 1024
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#define MI_MIN_ALLOCATION_FRAGMENT (4 * _1KB)
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#define MI_ALLOCATION_FRAGMENT (64 * _1KB)
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#define MI_MAX_ALLOCATION_FRAGMENT (2 * _1MB)
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#define MI_SESSION_WORKING_SET_SIZE (4 * 1024 * 1024)
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#define MI_SESSION_VIEW_SIZE (20 * 1024 * 1024)
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#define MI_SESSION_POOL_SIZE (16 * 1024 * 1024)
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#define MI_SESSION_IMAGE_SIZE (8 * 1024 * 1024)
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#define MI_SESSION_SIZE (MI_SESSION_VIEW_SIZE + \
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MI_SESSION_POOL_SIZE + \
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MI_SESSION_IMAGE_SIZE + \
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MI_SESSION_WORKING_SET_SIZE)
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#define MmSystemRangeStart ((PVOID)MI_REAL_SYSTEM_RANGE_START)
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/* Misc constants */
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#define _MI_PAGING_LEVELS 4
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#define MI_NUMBER_SYSTEM_PTES 22000
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#define MI_MAX_FREE_PAGE_LISTS 4
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#define NR_SECTION_PAGE_TABLES 1024
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#define NR_SECTION_PAGE_ENTRIES 1024
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#define MI_HYPERSPACE_PTES (256 - 1)
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#define MI_ZERO_PTES (32)
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/* FIXME - different architectures have different cache line sizes... */
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#define MM_CACHE_LINE_SIZE 32
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/* Helper macros */
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#define PAGE_MASK(x) ((x)&(~0xfff))
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#define PAE_PAGE_MASK(x) ((x)&(~0xfffLL))
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#define IS_ALIGNED(addr, align) (((ULONG64)(addr) & (align - 1)) == 0)
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#define IS_PAGE_ALIGNED(addr) IS_ALIGNED(addr, PAGE_SIZE)
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#define MiIsPteOnPdeBoundary(PointerPte) \
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((((ULONG_PTR)PointerPte) & (PAGE_SIZE - 1)) == 0)
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#define MiIsPteOnPpeBoundary(PointerPte) \
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((((ULONG_PTR)PointerPte) & (PDE_PER_PAGE * PAGE_SIZE - 1)) == 0)
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#define MiIsPteOnPxeBoundary(PointerPte) \
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((((ULONG_PTR)PointerPte) & (PPE_PER_PAGE * PDE_PER_PAGE * PAGE_SIZE - 1)) == 0)
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/* MMPTE related defines */
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#define MM_EMPTY_PTE_LIST ((ULONG64)0xFFFFFFFF)
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#define MM_EMPTY_LIST ((ULONG_PTR)-1)
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#define ADDR_TO_PAGE_TABLE(v) ((ULONG)(((ULONG_PTR)(v)) / (512 * PAGE_SIZE)))
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#define ADDR_TO_PDE_OFFSET(v) ((ULONG)((((ULONG_PTR)(v)) / (512 * PAGE_SIZE))))
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#define ADDR_TO_PTE_OFFSET(v) ((ULONG)((((ULONG_PTR)(v)) % (512 * PAGE_SIZE)) / PAGE_SIZE))
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#define MiGetPdeOffset ADDR_TO_PDE_OFFSET
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#define VAtoPXI(va) ((((ULONG64)va) >> PXI_SHIFT) & 0x1FF)
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#define VAtoPPI(va) ((((ULONG64)va) >> PPI_SHIFT) & 0x1FF)
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#define VAtoPDI(va) ((((ULONG64)va) >> PDI_SHIFT) & 0x1FF)
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#define VAtoPTI(va) ((((ULONG64)va) >> PTI_SHIFT) & 0x1FF)
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/* Easy accessing PFN in PTE */
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#define PFN_FROM_PTE(v) ((v)->u.Hard.PageFrameNumber)
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#define PFN_FROM_PDE(v) ((v)->u.Hard.PageFrameNumber)
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#define PFN_FROM_PPE(v) ((v)->u.Hard.PageFrameNumber)
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#define PFN_FROM_PXE(v) ((v)->u.Hard.PageFrameNumber)
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// FIXME, only copied from x86
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#define MI_MAKE_LOCAL_PAGE(x) ((x)->u.Hard.Global = 0)
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#define MI_MAKE_DIRTY_PAGE(x) ((x)->u.Hard.Dirty = 1)
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#define MI_MAKE_ACCESSED_PAGE(x) ((x)->u.Hard.Accessed = 1)
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#define MI_PAGE_DISABLE_CACHE(x) ((x)->u.Hard.CacheDisable = 1)
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#define MI_PAGE_WRITE_THROUGH(x) ((x)->u.Hard.WriteThrough = 1)
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#define MI_PAGE_WRITE_COMBINED(x) ((x)->u.Hard.WriteThrough = 0)
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#define MI_IS_PAGE_LARGE(x) ((x)->u.Hard.LargePage == 1)
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#if !defined(CONFIG_SMP)
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#define MI_IS_PAGE_WRITEABLE(x) ((x)->u.Hard.Write == 1)
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#else
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#define MI_IS_PAGE_WRITEABLE(x) ((x)->u.Hard.Writable == 1)
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#endif
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#define MI_IS_PAGE_COPY_ON_WRITE(x)((x)->u.Hard.CopyOnWrite == 1)
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#define MI_IS_PAGE_DIRTY(x) ((x)->u.Hard.Dirty == 1)
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#define MI_MAKE_OWNER_PAGE(x) ((x)->u.Hard.Owner = 1)
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#if !defined(CONFIG_SMP)
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#define MI_MAKE_WRITE_PAGE(x) ((x)->u.Hard.Write = 1)
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#else
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#define MI_MAKE_WRITE_PAGE(x) ((x)->u.Hard.Writable = 1)
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#endif
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// FIXME!!!
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#define PAGE_TO_SECTION_PAGE_DIRECTORY_OFFSET(x) \
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((x) / (4*1024*1024))
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#define PAGE_TO_SECTION_PAGE_TABLE_OFFSET(x) \
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((((x)) % (4*1024*1024)) / (4*1024))
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//#define TEB_BASE 0x7FFDE000
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/* On x86, these two are the same */
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#define MMPDE MMPTE
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#define PMMPDE PMMPTE
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#define MMPPE MMPTE
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#define PMMPPE PMMPTE
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#define MI_WRITE_VALID_PPE MI_WRITE_VALID_PTE
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#define ValidKernelPpe ValidKernelPde
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PULONG64
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FORCEINLINE
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MmGetPageDirectory(VOID)
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{
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return (PULONG64)__readcr3();
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}
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PMMPTE
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FORCEINLINE
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MiAddressToPxe(PVOID Address)
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{
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ULONG64 Offset = (ULONG64)Address >> (PXI_SHIFT - 3);
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Offset &= PXI_MASK << 3;
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return (PMMPTE)(PXE_BASE + Offset);
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}
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PMMPTE
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FORCEINLINE
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MiAddressToPpe(PVOID Address)
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{
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ULONG64 Offset = (ULONG64)Address >> (PPI_SHIFT - 3);
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Offset &= 0x3FFFF << 3;
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return (PMMPTE)(PPE_BASE + Offset);
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}
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PMMPTE
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FORCEINLINE
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_MiAddressToPde(PVOID Address)
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{
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ULONG64 Offset = (ULONG64)Address >> (PDI_SHIFT - 3);
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Offset &= 0x7FFFFFF << 3;
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return (PMMPTE)(PDE_BASE + Offset);
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}
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#define MiAddressToPde(x) _MiAddressToPde((PVOID)(x))
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PMMPTE
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FORCEINLINE
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_MiAddressToPte(PVOID Address)
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{
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ULONG64 Offset = (ULONG64)Address >> (PTI_SHIFT - 3);
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Offset &= 0xFFFFFFFFFULL << 3;
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return (PMMPTE)(PTE_BASE + Offset);
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}
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#define MiAddressToPte(x) _MiAddressToPte((PVOID)(x))
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ULONG
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FORCEINLINE
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MiAddressToPti(PVOID Address)
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{
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return ((((ULONG64)Address) >> PTI_SHIFT) & 0x1FF);
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}
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#define MiAddressToPteOffset(x) MiAddressToPti(x) // FIXME: bad name
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ULONG
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FORCEINLINE
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MiAddressToPxi(PVOID Address)
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{
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return ((((ULONG64)Address) >> PXI_SHIFT) & 0x1FF);
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}
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/* Convert a PTE into a corresponding address */
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PVOID
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FORCEINLINE
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MiPteToAddress(PMMPTE PointerPte)
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{
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/* Use signed math */
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return (PVOID)(((LONG64)PointerPte << 25) >> 16);
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}
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PVOID
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FORCEINLINE
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MiPdeToAddress(PMMPTE PointerPde)
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{
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/* Use signed math */
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return (PVOID)(((LONG64)PointerPde << 34) >> 16);
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}
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PVOID
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FORCEINLINE
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MiPpeToAddress(PMMPTE PointerPpe)
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{
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/* Use signed math */
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return (PVOID)(((LONG64)PointerPpe << 43) >> 16);
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}
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PVOID
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FORCEINLINE
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MiPxeToAddress(PMMPTE PointerPxe)
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{
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/* Use signed math */
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return (PVOID)(((LONG64)PointerPxe << 52) >> 16);
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}
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BOOLEAN
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FORCEINLINE
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MiIsPdeForAddressValid(PVOID Address)
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{
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return ((MiAddressToPxe(Address)->u.Hard.Valid) &&
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(MiAddressToPpe(Address)->u.Hard.Valid) &&
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(MiAddressToPde(Address)->u.Hard.Valid));
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}
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#define MiPdeToPte(PDE) ((PMMPTE)MiPteToAddress(PDE))
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#define MiPteToPde(PTE) ((PMMPDE)MiAddressToPte(PTE))
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#define MiPdeToPpe(Pde) ((PMMPPE)MiAddressToPte(Pde))
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/* Sign extend 48 bits */
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#define MiProtoPteToPte(x) (PMMPTE)(((LONG64)(x)->u.Long) >> 16)
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//
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// Decodes a Prototype PTE into the underlying PTE
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//
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#define MiSubsectionPteToSubsection(x) \
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(PMMPTE)((x)->u.Subsect.SubsectionAddress >> 16)
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FORCEINLINE
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VOID
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MI_MAKE_SUBSECTION_PTE(IN PMMPTE NewPte,
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IN PVOID Segment)
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{
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ASSERT(FALSE);
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}
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FORCEINLINE
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VOID
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MI_MAKE_PROTOTYPE_PTE(IN PMMPTE NewPte,
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IN PMMPTE PointerPte)
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{
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/* Store the Address */
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NewPte->u.Long = (ULONG64)PointerPte << 16;
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/* Mark this as a prototype PTE */
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NewPte->u.Proto.Prototype = 1;
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ASSERT(MiProtoPteToPte(NewPte) == PointerPte);
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}
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FORCEINLINE
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BOOLEAN
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MI_IS_MAPPED_PTE(PMMPTE PointerPte)
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{
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/// FIXME
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__debugbreak();
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return (PointerPte->u.Long & 0xFFFFFC01 != 0);
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}
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VOID
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FORCEINLINE
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MmInitGlobalKernelPageDirectory(VOID)
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{
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/* Nothing to do */
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}
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