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173 lines
5.3 KiB
C
173 lines
5.3 KiB
C
/*++
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Copyright (c) 1998-2001 Klaus P. Gerlicher
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Module Name:
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serial_port.h
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Abstract:
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HEADER for serial.c
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serial port HW defines
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Environment:
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LINUX 2.2.X
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Kernel mode only
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Author:
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Klaus P. Gerlicher
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Revision History:
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15-Nov-2000: general cleanup of source files
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Copyright notice:
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This file may be distributed under the terms of the GNU Public License.
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--*/
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#define COM1 1
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#define COM2 2
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#define COM1BASE 0x3F8 /* Base port address for COM1 */
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#define COM2BASE 0x2F8 /* Base port address for COM2 */
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// FIX these
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#define COM3BASE 0x3F8 /* Base port address for COM3 */
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#define COM4BASE 0x2F8 /* Base port address for COM4 */
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/*
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The 8250 UART has 10 registers accessible through 7 port addresses.
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Here are their addresses relative to COM1BASE and COM2BASE. Note
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that the baud rate registers, (DLL) and (DLH) are active only when
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the Divisor-Latch Access-Bit (DLAB) is on. The (DLAB) is bit 7 of
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the (LCR).
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o TXR Output data to the serial port.
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o RXR Input data from the serial port.
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o LCR Initialize the serial port.
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o IER Controls interrupt generation.
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o IIR Identifies interrupts.
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o MCR Send contorl signals to the modem.
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o LSR Monitor the status of the serial port.
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o MSR Receive status of the modem.
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o DLL Low byte of baud rate divisor.
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o DHH High byte of baud rate divisor.
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*/
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#define TXR 0 /* Transmit register (WRITE) */
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#define RXR 0 /* Receive register (READ) */
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#define IER 1 /* Interrupt Enable */
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#define IIR 2 /* Interrupt ID */
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#define FCR 2 /* FIFO control */
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#define LCR 3 /* Line control */
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#define MCR 4 /* Modem control */
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#define LSR 5 /* Line Status */
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#define MSR 6 /* Modem Status */
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#define DLL 0 /* Divisor Latch Low */
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#define DLH 1 /* Divisor latch High */
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/*-------------------------------------------------------------------*
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Bit values held in the Line Control Register (LCR).
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bit meaning
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--- -------
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0-1 00=5 bits, 01=6 bits, 10=7 bits, 11=8 bits.
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2 Stop bits.
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3 0=parity off, 1=parity on.
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4 0=parity odd, 1=parity even.
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5 Sticky parity.
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6 Set break.
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7 Toggle port addresses.
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*-------------------------------------------------------------------*/
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#define NO_PARITY 0x00
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#define EVEN_PARITY 0x18
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#define ODD_PARITY 0x08
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/*-------------------------------------------------------------------*
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Bit values held in the Line Status Register (LSR).
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bit meaning
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--- -------
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0 Data ready.
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1 Overrun error - Data register overwritten.
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2 Parity error - bad transmission.
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3 Framing error - No stop bit was found.
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4 Break detect - End to transmission requested.
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5 Transmitter holding register is empty.
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6 Transmitter shift register is empty.
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7 Time out - off line.
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*-------------------------------------------------------------------*/
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#define RCVRDY 0x01
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#define OVRERR 0x02
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#define PRTYERR 0x04
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#define FRMERR 0x08
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#define BRKERR 0x10
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#define XMTRDY 0x20
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#define XMTRSR 0x40
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#define TIMEOUT 0x80
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/*-------------------------------------------------------------------*
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Bit values held in the Modem Output Control Register (MCR).
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bit meaning
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--- -------
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0 Data Terminal Ready. Computer ready to go.
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1 Request To Send. Computer wants to send data.
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2 auxillary output #1.
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3 auxillary output #2.(Note: This bit must be
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set to allow the communications card to send
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interrupts to the system)
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4 UART ouput looped back as input.
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5-7 not used.
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*------------------------------------------------------------------*/
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#define DTR 0x01
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#define RTS 0x02
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/*------------------------------------------------------------------*
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Bit values held in the Modem Input Status Register (MSR).
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bit meaning
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--- -------
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0 delta Clear To Send.
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1 delta Data Set Ready.
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2 delta Ring Indicator.
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3 delta Data Carrier Detect.
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4 Clear To Send.
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5 Data Set Ready.
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6 Ring Indicator.
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7 Data Carrier Detect.
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*------------------------------------------------------------------*/
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#define CTS 0x10
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#define DSR 0x20
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/*------------------------------------------------------------------*
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Bit values held in the Interrupt Enable Register (IER).
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bit meaning
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--- -------
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0 Interrupt when data received.
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1 Interrupt when transmitter holding reg. empty.
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2 Interrupt when data reception error.
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3 Interrupt when change in modem status register.
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4-7 Not used.
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*------------------------------------------------------------------*/
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#define RX_INT 0x01
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/*------------------------------------------------------------------*
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Bit values held in the Interrupt Identification Register (IIR).
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bit meaning
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--- -------
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0 Interrupt pending
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1-2 Interrupt ID code
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00=Change in modem status register,
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01=Transmitter holding register empty,
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10=Data received,
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11=reception error, or break encountered.
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3-7 Not used.
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*------------------------------------------------------------------*/
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#define RX_ID 0x04
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#define RX_MASK 0x07
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