mirror of
https://github.com/reactos/reactos.git
synced 2024-08-22 19:33:01 +00:00
779 lines
22 KiB
C
779 lines
22 KiB
C
/*
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* PROJECT: ReactOS HAL
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* LICENSE: GPL - See COPYING in the top level directory
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* FILE: hal/halppc/generic/pci.c
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* PURPOSE: PCI Bus Support (Configuration Space, Resource Allocation)
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* PROGRAMMERS: Alex Ionescu (alex.ionescu@reactos.org)
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*/
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/* INCLUDES ******************************************************************/
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#include <hal.h>
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#define NDEBUG
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#include <debug.h>
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/* GLOBALS *******************************************************************/
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BOOLEAN HalpPCIConfigInitialized;
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ULONG HalpMinPciBus, HalpMaxPciBus;
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KSPIN_LOCK HalpPCIConfigLock;
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PCI_CONFIG_HANDLER PCIConfigHandler;
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/* PCI Operation Matrix */
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UCHAR PCIDeref[4][4] =
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{
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{0, 1, 2, 2}, // ULONG-aligned offset
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{1, 1, 1, 1}, // UCHAR-aligned offset
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{2, 1, 2, 2}, // USHORT-aligned offset
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{1, 1, 1, 1} // UCHAR-aligned offset
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};
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/* Type 1 PCI Bus */
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PCI_CONFIG_HANDLER PCIConfigHandlerType1 =
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{
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/* Synchronization */
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(FncSync)HalpPCISynchronizeType1,
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(FncReleaseSync)HalpPCIReleaseSynchronzationType1,
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/* Read */
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{
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(FncConfigIO)HalpPCIReadUlongType1,
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(FncConfigIO)HalpPCIReadUcharType1,
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(FncConfigIO)HalpPCIReadUshortType1
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},
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/* Write */
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{
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(FncConfigIO)HalpPCIWriteUlongType1,
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(FncConfigIO)HalpPCIWriteUcharType1,
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(FncConfigIO)HalpPCIWriteUshortType1
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}
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};
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/* Type 2 PCI Bus */
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PCI_CONFIG_HANDLER PCIConfigHandlerType2 =
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{
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/* Synchronization */
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(FncSync)HalpPCISynchronizeType2,
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(FncReleaseSync)HalpPCIReleaseSynchronzationType2,
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/* Read */
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{
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(FncConfigIO)HalpPCIReadUlongType2,
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(FncConfigIO)HalpPCIReadUcharType2,
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(FncConfigIO)HalpPCIReadUshortType2
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},
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/* Write */
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{
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(FncConfigIO)HalpPCIWriteUlongType2,
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(FncConfigIO)HalpPCIWriteUcharType2,
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(FncConfigIO)HalpPCIWriteUshortType2
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}
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};
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PCIPBUSDATA HalpFakePciBusData =
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{
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{
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PCI_DATA_TAG,
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PCI_DATA_VERSION,
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HalpReadPCIConfig,
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HalpWritePCIConfig,
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NULL,
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NULL,
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{{{0}}},
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{0, 0, 0, 0}
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},
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{{0}},
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32,
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};
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BUS_HANDLER HalpFakePciBusHandler =
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{
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1,
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PCIBus,
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PCIConfiguration,
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0,
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NULL,
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NULL,
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&HalpFakePciBusData,
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0,
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{0, 0, 0, 0},
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HalpGetPCIData,
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HalpSetPCIData,
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NULL,
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HalpAssignPCISlotResources,
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NULL,
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NULL
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};
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/* TYPE 1 FUNCTIONS **********************************************************/
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VOID
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NTAPI
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HalpPCISynchronizeType1(IN PBUS_HANDLER BusHandler,
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IN PCI_SLOT_NUMBER Slot,
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IN PKIRQL Irql,
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IN PPCI_TYPE1_CFG_BITS PciCfg1)
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{
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/* Setup the PCI Configuration Register */
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PciCfg1->u.AsULONG = 0;
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PciCfg1->u.bits.BusNumber = BusHandler->BusNumber;
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PciCfg1->u.bits.DeviceNumber = Slot.u.bits.DeviceNumber;
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PciCfg1->u.bits.FunctionNumber = Slot.u.bits.FunctionNumber;
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PciCfg1->u.bits.Enable = TRUE;
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/* Acquire the lock */
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KeRaiseIrql(HIGH_LEVEL, Irql);
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KiAcquireSpinLock(&HalpPCIConfigLock);
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}
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VOID
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NTAPI
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HalpPCIReleaseSynchronzationType1(IN PBUS_HANDLER BusHandler,
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IN KIRQL Irql)
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{
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PCI_TYPE1_CFG_BITS PciCfg1;
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/* Clear the PCI Configuration Register */
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PciCfg1.u.AsULONG = 0;
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WRITE_PORT_ULONG(((PPCIPBUSDATA)BusHandler->BusData)->Config.Type1.Address,
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PciCfg1.u.AsULONG);
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/* Release the lock */
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KiReleaseSpinLock(&HalpPCIConfigLock);
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KeLowerIrql(Irql);
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}
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TYPE1_READ(HalpPCIReadUcharType1, UCHAR)
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TYPE1_READ(HalpPCIReadUshortType1, USHORT)
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TYPE1_READ(HalpPCIReadUlongType1, ULONG)
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TYPE1_WRITE(HalpPCIWriteUcharType1, UCHAR)
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TYPE1_WRITE(HalpPCIWriteUshortType1, USHORT)
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TYPE1_WRITE(HalpPCIWriteUlongType1, ULONG)
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/* TYPE 2 FUNCTIONS **********************************************************/
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VOID
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NTAPI
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HalpPCISynchronizeType2(IN PBUS_HANDLER BusHandler,
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IN PCI_SLOT_NUMBER Slot,
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IN PKIRQL Irql,
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IN PPCI_TYPE2_ADDRESS_BITS PciCfg)
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{
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PCI_TYPE2_CSE_BITS PciCfg2Cse;
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PPCIPBUSDATA BusData = (PPCIPBUSDATA)BusHandler->BusData;
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/* Setup the configuration register */
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PciCfg->u.AsUSHORT = 0;
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PciCfg->u.bits.Agent = (USHORT)Slot.u.bits.DeviceNumber;
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PciCfg->u.bits.AddressBase = (USHORT)BusData->Config.Type2.Base;
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/* Acquire the lock */
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KeRaiseIrql(HIGH_LEVEL, Irql);
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KiAcquireSpinLock(&HalpPCIConfigLock);
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/* Setup the CSE Register */
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PciCfg2Cse.u.AsUCHAR = 0;
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PciCfg2Cse.u.bits.Enable = TRUE;
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PciCfg2Cse.u.bits.FunctionNumber = (UCHAR)Slot.u.bits.FunctionNumber;
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PciCfg2Cse.u.bits.Key = -1;
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/* Write the bus number and CSE */
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WRITE_PORT_UCHAR(BusData->Config.Type2.Forward,
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(UCHAR)BusHandler->BusNumber);
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WRITE_PORT_UCHAR(BusData->Config.Type2.CSE, PciCfg2Cse.u.AsUCHAR);
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}
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VOID
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NTAPI
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HalpPCIReleaseSynchronzationType2(IN PBUS_HANDLER BusHandler,
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IN KIRQL Irql)
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{
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PCI_TYPE2_CSE_BITS PciCfg2Cse;
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PPCIPBUSDATA BusData = (PPCIPBUSDATA)BusHandler->BusData;
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/* Clear CSE and bus number */
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PciCfg2Cse.u.AsUCHAR = 0;
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WRITE_PORT_UCHAR(BusData->Config.Type2.CSE, PciCfg2Cse.u.AsUCHAR);
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WRITE_PORT_UCHAR(BusData->Config.Type2.Forward, 0);
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/* Release the lock */
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KiReleaseSpinLock(&HalpPCIConfigLock);
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KeLowerIrql(Irql);
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}
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TYPE2_READ(HalpPCIReadUcharType2, UCHAR)
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TYPE2_READ(HalpPCIReadUshortType2, USHORT)
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TYPE2_READ(HalpPCIReadUlongType2, ULONG)
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TYPE2_WRITE(HalpPCIWriteUcharType2, UCHAR)
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TYPE2_WRITE(HalpPCIWriteUshortType2, USHORT)
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TYPE2_WRITE(HalpPCIWriteUlongType2, ULONG)
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/* PCI CONFIGURATION SPACE ***************************************************/
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VOID
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NTAPI
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HalpPCIConfig(IN PBUS_HANDLER BusHandler,
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IN PCI_SLOT_NUMBER Slot,
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IN PUCHAR Buffer,
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IN ULONG Offset,
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IN ULONG Length,
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IN FncConfigIO *ConfigIO)
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{
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KIRQL OldIrql;
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ULONG i;
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UCHAR State[20];
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/* Synchronize the operation */
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PCIConfigHandler.Synchronize(BusHandler, Slot, &OldIrql, State);
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/* Loop every increment */
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while (Length)
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{
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/* Find out the type of read/write we need to do */
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i = PCIDeref[Offset % sizeof(ULONG)][Length % sizeof(ULONG)];
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/* Do the read/write and return the number of bytes */
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i = ConfigIO[i]((PPCIPBUSDATA)BusHandler->BusData,
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State,
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Buffer,
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Offset);
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/* Increment the buffer position and offset, and decrease the length */
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Offset += i;
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Buffer += i;
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Length -= i;
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}
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/* Release the lock and PCI bus */
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PCIConfigHandler.ReleaseSynchronzation(BusHandler, OldIrql);
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}
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VOID
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NTAPI
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HalpReadPCIConfig(IN PBUS_HANDLER BusHandler,
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IN PCI_SLOT_NUMBER Slot,
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IN PVOID Buffer,
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IN ULONG Offset,
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IN ULONG Length)
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{
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/* Validate the PCI Slot */
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if (!HalpValidPCISlot(BusHandler, Slot))
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{
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/* Fill the buffer with invalid data */
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RtlFillMemory(Buffer, Length, -1);
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}
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else
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{
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/* Send the request */
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HalpPCIConfig(BusHandler,
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Slot,
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Buffer,
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Offset,
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Length,
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PCIConfigHandler.ConfigRead);
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}
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}
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VOID
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NTAPI
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HalpWritePCIConfig(IN PBUS_HANDLER BusHandler,
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IN PCI_SLOT_NUMBER Slot,
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IN PVOID Buffer,
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IN ULONG Offset,
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IN ULONG Length)
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{
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/* Validate the PCI Slot */
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if (HalpValidPCISlot(BusHandler, Slot))
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{
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/* Send the request */
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HalpPCIConfig(BusHandler,
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Slot,
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Buffer,
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Offset,
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Length,
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PCIConfigHandler.ConfigWrite);
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}
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}
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BOOLEAN
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NTAPI
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HalpValidPCISlot(IN PBUS_HANDLER BusHandler,
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IN PCI_SLOT_NUMBER Slot)
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{
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PCI_SLOT_NUMBER MultiSlot;
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PPCIPBUSDATA BusData = (PPCIPBUSDATA)BusHandler->BusData;
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UCHAR HeaderType;
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ULONG Device;
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/* Simple validation */
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if (Slot.u.bits.Reserved) return FALSE;
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if (Slot.u.bits.DeviceNumber >= BusData->MaxDevice) return FALSE;
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/* Function 0 doesn't need checking */
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if (!Slot.u.bits.FunctionNumber) return TRUE;
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/* Functions 0+ need Multi-Function support, so check the slot */
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Device = Slot.u.bits.DeviceNumber;
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MultiSlot = Slot;
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MultiSlot.u.bits.FunctionNumber = 0;
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/* Send function 0 request to get the header back */
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HalpReadPCIConfig(BusHandler,
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MultiSlot,
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&HeaderType,
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FIELD_OFFSET(PCI_COMMON_CONFIG, HeaderType),
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sizeof(UCHAR));
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/* Now make sure the header is multi-function */
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if (!(HeaderType & PCI_MULTIFUNCTION) || (HeaderType == 0xFF)) return FALSE;
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return TRUE;
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}
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/* HAL PCI CALLBACKS *********************************************************/
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ULONG
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NTAPI
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HalpGetPCIData(IN PBUS_HANDLER BusHandler,
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IN PBUS_HANDLER RootHandler,
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IN PCI_SLOT_NUMBER Slot,
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IN PUCHAR Buffer,
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IN ULONG Offset,
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IN ULONG Length)
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{
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UCHAR PciBuffer[PCI_COMMON_HDR_LENGTH];
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PPCI_COMMON_CONFIG PciConfig = (PPCI_COMMON_CONFIG)PciBuffer;
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ULONG Len = 0;
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/* Normalize the length */
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if (Length > sizeof(PCI_COMMON_CONFIG)) Length = sizeof(PCI_COMMON_CONFIG);
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/* Check if this is a vendor-specific read */
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if (Offset >= PCI_COMMON_HDR_LENGTH)
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{
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/* Read the header */
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HalpReadPCIConfig(BusHandler, Slot, PciConfig, 0, sizeof(ULONG));
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/* Make sure the vendor is valid */
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if (PciConfig->VendorID == PCI_INVALID_VENDORID) return 0;
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}
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else
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{
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/* Read the entire header */
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Len = PCI_COMMON_HDR_LENGTH;
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HalpReadPCIConfig(BusHandler, Slot, PciConfig, 0, Len);
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/* Validate the vendor ID */
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if (PciConfig->VendorID == PCI_INVALID_VENDORID)
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{
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/* It's invalid, but we want to return this much */
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PciConfig->VendorID = PCI_INVALID_VENDORID;
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Len = sizeof(USHORT);
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}
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/* Now check if there's space left */
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if (Len < Offset) return 0;
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/* There is, so return what's after the offset and normalize */
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Len -= Offset;
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if (Len > Length) Len = Length;
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/* Copy the data into the caller's buffer */
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RtlMoveMemory(Buffer, PciBuffer + Offset, Len);
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/* Update buffer and offset, decrement total length */
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Offset += Len;
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Buffer += Len;
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Length -= Len;
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}
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/* Now we still have something to copy */
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if (Length)
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{
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/* Check if it's vendor-specific data */
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if (Offset >= PCI_COMMON_HDR_LENGTH)
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{
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/* Read it now */
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HalpReadPCIConfig(BusHandler, Slot, Buffer, Offset, Length);
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Len += Length;
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}
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}
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/* Update the total length read */
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return Len;
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}
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ULONG
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NTAPI
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HalpSetPCIData(IN PBUS_HANDLER BusHandler,
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IN PBUS_HANDLER RootHandler,
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IN PCI_SLOT_NUMBER Slot,
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IN PUCHAR Buffer,
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IN ULONG Offset,
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IN ULONG Length)
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{
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UCHAR PciBuffer[PCI_COMMON_HDR_LENGTH];
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PPCI_COMMON_CONFIG PciConfig = (PPCI_COMMON_CONFIG)PciBuffer;
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ULONG Len = 0;
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/* Normalize the length */
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if (Length > sizeof(PCI_COMMON_CONFIG)) Length = sizeof(PCI_COMMON_CONFIG);
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/* Check if this is a vendor-specific read */
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if (Offset >= PCI_COMMON_HDR_LENGTH)
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{
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/* Read the header */
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HalpReadPCIConfig(BusHandler, Slot, PciConfig, 0, sizeof(ULONG));
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/* Make sure the vendor is valid */
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if (PciConfig->VendorID == PCI_INVALID_VENDORID) return 0;
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}
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else
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{
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/* Read the entire header and validate the vendor ID */
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Len = PCI_COMMON_HDR_LENGTH;
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HalpReadPCIConfig(BusHandler, Slot, PciConfig, 0, Len);
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if (PciConfig->VendorID == PCI_INVALID_VENDORID) return 0;
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/* Return what's after the offset and normalize */
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Len -= Offset;
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if (Len > Length) Len = Length;
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/* Copy the specific caller data */
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RtlMoveMemory(PciBuffer + Offset, Buffer, Len);
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/* Write the actual configuration data */
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HalpWritePCIConfig(BusHandler, Slot, PciBuffer + Offset, Offset, Len);
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/* Update buffer and offset, decrement total length */
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Offset += Len;
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Buffer += Len;
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Length -= Len;
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}
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/* Now we still have something to copy */
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if (Length)
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{
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/* Check if it's vendor-specific data */
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if (Offset >= PCI_COMMON_HDR_LENGTH)
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{
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/* Read it now */
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HalpWritePCIConfig(BusHandler, Slot, Buffer, Offset, Length);
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Len += Length;
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}
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}
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/* Update the total length read */
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return Len;
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}
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NTSTATUS
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NTAPI
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HalpSetupPciDeviceForDebugging(IN PVOID LoaderBlock,
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IN OUT PDEBUG_DEVICE_DESCRIPTOR PciDevice)
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{
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DPRINT1("Unimplemented!\n");
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return STATUS_NOT_IMPLEMENTED;
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}
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NTSTATUS
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NTAPI
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HalpReleasePciDeviceForDebugging(IN OUT PDEBUG_DEVICE_DESCRIPTOR PciDevice)
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{
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DPRINT1("Unimplemented!\n");
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return STATUS_NOT_IMPLEMENTED;
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}
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NTSTATUS
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NTAPI
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HalpAssignPCISlotResources(IN PBUS_HANDLER BusHandler,
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IN PBUS_HANDLER RootHandler,
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IN PUNICODE_STRING RegistryPath,
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IN PUNICODE_STRING DriverClassName OPTIONAL,
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IN PDRIVER_OBJECT DriverObject,
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IN PDEVICE_OBJECT DeviceObject OPTIONAL,
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IN ULONG Slot,
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IN OUT PCM_RESOURCE_LIST *pAllocatedResources)
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{
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KeBugCheck(0);
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return STATUS_SUCCESS;
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}
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ULONG
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NTAPI
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HaliPciInterfaceReadConfig(IN PBUS_HANDLER RootBusHandler,
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IN ULONG BusNumber,
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IN PCI_SLOT_NUMBER SlotNumber,
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IN PVOID Buffer,
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IN ULONG Offset,
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IN ULONG Length)
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{
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BUS_HANDLER BusHandler;
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PPCI_COMMON_CONFIG PciData = (PPCI_COMMON_CONFIG)Buffer;
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/* Setup fake PCI Bus handler */
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RtlCopyMemory(&BusHandler, &HalpFakePciBusHandler, sizeof(BUS_HANDLER));
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BusHandler.BusNumber = BusNumber;
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/* Read configuration data */
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HalpReadPCIConfig(&BusHandler, SlotNumber, Buffer, Offset, Length);
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/* Check if caller only wanted at least Vendor ID */
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if (Length >= 2)
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{
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/* Validate it */
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if (PciData->VendorID != PCI_INVALID_VENDORID)
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{
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/* Check if this is the new maximum bus number */
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if (HalpMaxPciBus < BusHandler.BusNumber)
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{
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/* Set it */
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HalpMaxPciBus = BusHandler.BusNumber;
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}
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}
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}
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/* Return length */
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return Length;
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}
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PPCI_REGISTRY_INFO_INTERNAL
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NTAPI
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HalpQueryPciRegistryInfo(VOID)
|
|
{
|
|
WCHAR NameBuffer[8];
|
|
OBJECT_ATTRIBUTES ObjectAttributes;
|
|
UNICODE_STRING KeyName, ConfigName, IdentName;
|
|
HANDLE KeyHandle, BusKeyHandle;
|
|
NTSTATUS Status;
|
|
UCHAR KeyBuffer[sizeof(PPCI_REGISTRY_INFO) + 100];
|
|
PKEY_VALUE_FULL_INFORMATION ValueInfo = (PVOID)KeyBuffer;
|
|
ULONG ResultLength;
|
|
PWSTR Tag;
|
|
ULONG i;
|
|
PCM_FULL_RESOURCE_DESCRIPTOR FullDescriptor;
|
|
PCM_PARTIAL_RESOURCE_DESCRIPTOR PartialDescriptor;
|
|
PPCI_REGISTRY_INFO PciRegInfo;
|
|
PPCI_REGISTRY_INFO_INTERNAL PciRegistryInfo;
|
|
|
|
/* Setup the object attributes for the key */
|
|
RtlInitUnicodeString(&KeyName,
|
|
L"\\Registry\\Machine\\Hardware\\Description\\"
|
|
L"System\\MultiFunctionAdapter");
|
|
InitializeObjectAttributes(&ObjectAttributes,
|
|
&KeyName,
|
|
OBJ_CASE_INSENSITIVE,
|
|
NULL,
|
|
NULL);
|
|
|
|
/* Open the key */
|
|
Status = ZwOpenKey(&KeyHandle, KEY_READ, &ObjectAttributes);
|
|
if (!NT_SUCCESS(Status)) return NULL;
|
|
|
|
/* Setup the receiving string */
|
|
KeyName.Buffer = NameBuffer;
|
|
KeyName.MaximumLength = sizeof(NameBuffer);
|
|
|
|
/* Setup the configuration and identifier key names */
|
|
RtlInitUnicodeString(&ConfigName, L"ConfigurationData");
|
|
RtlInitUnicodeString(&IdentName, L"Identifier");
|
|
|
|
/* Keep looping for each ID */
|
|
for (i = 0; TRUE; i++)
|
|
{
|
|
/* Setup the key name */
|
|
RtlIntegerToUnicodeString(i, 10, &KeyName);
|
|
InitializeObjectAttributes(&ObjectAttributes,
|
|
&KeyName,
|
|
OBJ_CASE_INSENSITIVE,
|
|
KeyHandle,
|
|
NULL);
|
|
|
|
/* Open it */
|
|
Status = ZwOpenKey(&BusKeyHandle, KEY_READ, &ObjectAttributes);
|
|
if (!NT_SUCCESS(Status))
|
|
{
|
|
/* None left, fail */
|
|
ZwClose(KeyHandle);
|
|
return NULL;
|
|
}
|
|
|
|
/* Read the registry data */
|
|
Status = ZwQueryValueKey(BusKeyHandle,
|
|
&IdentName,
|
|
KeyValueFullInformation,
|
|
ValueInfo,
|
|
sizeof(KeyBuffer),
|
|
&ResultLength);
|
|
if (!NT_SUCCESS(Status))
|
|
{
|
|
/* Failed, try the next one */
|
|
ZwClose(BusKeyHandle);
|
|
continue;
|
|
}
|
|
|
|
/* Get the PCI Tag and validate it */
|
|
Tag = (PWSTR)((ULONG_PTR)ValueInfo + ValueInfo->DataOffset);
|
|
if ((Tag[0] != L'P') ||
|
|
(Tag[1] != L'C') ||
|
|
(Tag[2] != L'I') ||
|
|
(Tag[3]))
|
|
{
|
|
/* Not a valid PCI entry, skip it */
|
|
ZwClose(BusKeyHandle);
|
|
continue;
|
|
}
|
|
|
|
/* Now read our PCI structure */
|
|
Status = ZwQueryValueKey(BusKeyHandle,
|
|
&ConfigName,
|
|
KeyValueFullInformation,
|
|
ValueInfo,
|
|
sizeof(KeyBuffer),
|
|
&ResultLength);
|
|
ZwClose(BusKeyHandle);
|
|
if (!NT_SUCCESS(Status)) continue;
|
|
|
|
/* We read it OK! Get the actual resource descriptors */
|
|
FullDescriptor = (PCM_FULL_RESOURCE_DESCRIPTOR)
|
|
((ULONG_PTR)ValueInfo + ValueInfo->DataOffset);
|
|
PartialDescriptor = (PCM_PARTIAL_RESOURCE_DESCRIPTOR)
|
|
((ULONG_PTR)FullDescriptor->
|
|
PartialResourceList.PartialDescriptors);
|
|
|
|
/* Check if this is our PCI Registry Information */
|
|
if (PartialDescriptor->Type == CmResourceTypeDeviceSpecific)
|
|
{
|
|
/* Close the key */
|
|
ZwClose(KeyHandle);
|
|
|
|
/* FIXME: Check PnP\PCI\CardList */
|
|
|
|
/* Get the PCI information */
|
|
PciRegInfo = (PPCI_REGISTRY_INFO)(PartialDescriptor + 1);
|
|
|
|
/* Allocate the return structure */
|
|
PciRegistryInfo = ExAllocatePoolWithTag(NonPagedPool,
|
|
sizeof(PCI_REGISTRY_INFO_INTERNAL),
|
|
TAG_HAL);
|
|
if (!PciRegistryInfo) return NULL;
|
|
|
|
/* Fill it out */
|
|
PciRegistryInfo->HardwareMechanism = PciRegInfo->HardwareMechanism;
|
|
PciRegistryInfo->NoBuses = PciRegInfo->NoBuses;
|
|
PciRegistryInfo->MajorRevision = PciRegInfo->MajorRevision;
|
|
PciRegistryInfo->MinorRevision = PciRegInfo->MinorRevision;
|
|
PciRegistryInfo->ElementCount = 0;
|
|
}
|
|
}
|
|
}
|
|
|
|
VOID
|
|
NTAPI
|
|
HalpInitializePciStubs(VOID)
|
|
{
|
|
PPCI_REGISTRY_INFO_INTERNAL PciRegistryInfo;
|
|
UCHAR PciType;
|
|
PPCIPBUSDATA BusData = (PPCIPBUSDATA)HalpFakePciBusHandler.BusData;
|
|
ULONG i;
|
|
PCI_SLOT_NUMBER j;
|
|
ULONG VendorId = 0;
|
|
|
|
/* Query registry information */
|
|
PciRegistryInfo = HalpQueryPciRegistryInfo();
|
|
if (!PciRegistryInfo)
|
|
{
|
|
/* Assume type 1 */
|
|
PciType = 1;
|
|
}
|
|
else
|
|
{
|
|
/* Get the type and free the info structure */
|
|
PciType = PciRegistryInfo->HardwareMechanism & 0xF;
|
|
ExFreePool(PciRegistryInfo);
|
|
}
|
|
|
|
/* Initialize the PCI lock */
|
|
KeInitializeSpinLock(&HalpPCIConfigLock);
|
|
|
|
/* Check the type of PCI bus */
|
|
switch (PciType)
|
|
{
|
|
/* Type 1 PCI Bus */
|
|
case 1:
|
|
|
|
/* Copy the Type 1 handler data */
|
|
RtlCopyMemory(&PCIConfigHandler,
|
|
&PCIConfigHandlerType1,
|
|
sizeof(PCIConfigHandler));
|
|
|
|
/* Set correct I/O Ports */
|
|
BusData->Config.Type1.Address = PCI_TYPE1_ADDRESS_PORT;
|
|
BusData->Config.Type1.Data = PCI_TYPE1_DATA_PORT;
|
|
break;
|
|
|
|
/* Type 2 PCI Bus */
|
|
case 2:
|
|
|
|
/* Copy the Type 1 handler data */
|
|
RtlCopyMemory(&PCIConfigHandler,
|
|
&PCIConfigHandlerType2,
|
|
sizeof (PCIConfigHandler));
|
|
|
|
/* Set correct I/O Ports */
|
|
BusData->Config.Type2.CSE = PCI_TYPE2_CSE_PORT;
|
|
BusData->Config.Type2.Forward = PCI_TYPE2_FORWARD_PORT;
|
|
BusData->Config.Type2.Base = PCI_TYPE2_ADDRESS_BASE;
|
|
|
|
/* Only 16 devices supported, not 32 */
|
|
BusData->MaxDevice = 16;
|
|
break;
|
|
|
|
default:
|
|
|
|
/* Invalid type */
|
|
DbgPrint("HAL: Unnkown PCI type\n");
|
|
}
|
|
|
|
/* Loop all possible buses */
|
|
for (i = 0; i < 256; i++)
|
|
{
|
|
/* Loop all devices */
|
|
for (j.u.AsULONG = 0; j.u.AsULONG < 32; j.u.AsULONG++)
|
|
{
|
|
/* Query the interface */
|
|
if (HaliPciInterfaceReadConfig(NULL,
|
|
i,
|
|
j,
|
|
&VendorId,
|
|
0,
|
|
sizeof(ULONG)))
|
|
{
|
|
/* Validate the vendor ID */
|
|
if ((USHORT)VendorId != PCI_INVALID_VENDORID)
|
|
{
|
|
/* Set this as the maximum ID */
|
|
HalpMaxPciBus = i;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
/* We're done */
|
|
HalpPCIConfigInitialized = TRUE;
|
|
}
|
|
|
|
VOID
|
|
NTAPI
|
|
HalpInitializePciBus(VOID)
|
|
{
|
|
/* Initialize the stubs */
|
|
HalpInitializePciStubs();
|
|
|
|
/* FIXME: Initialize NMI Crash Flag */
|
|
}
|
|
|
|
/* EOF */
|