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354 lines
13 KiB
C
354 lines
13 KiB
C
/*
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* ReactOS Floppy Driver
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* Copyright (C) 2004, Vizzini (vizzini@plasmic.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* PROJECT: ReactOS Floppy Driver
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* FILE: hardware.h
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* PURPOSE: Header for FDC control routines
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* PROGRAMMER: Vizzini (vizzini@plasmic.com)
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* REVISIONS:
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* 15-Feb-2004 vizzini - Created
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*
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* NOTES:
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* - Baesd on http://www.nondot.org/sabre/os/files/Disk/FLOPPY.TXT
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* - Some information taken from Intel 82077AA data sheet (order #290166-007)
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* - Some definitions are PS/2-Specific; others include the original NEC PD765
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* - Other information gathered from the comments in the NT 3.5 floppy driver
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*
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* TODO:
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* - Convert these numbers to 100% absolute values; eliminate bit positions
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* in favor of shifts or bitfields
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*/
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#pragma once
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#define FLOPPY_DEFAULT_IRQ 0x6
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#define FDC_PORT_BYTES 0x8
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/* Register offsets from base address (usually 0x3f8) */
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#define STATUS_REGISTER_A 0x0 /* Read; PS/2 Only */
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#define STATUS_REGISTER_B 0x1 /* Read; PS/2 Only */
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#define DIGITAL_OUTPUT_REGISTER 0x2 /* Read/Write */
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#define TAPE_DRIVE_REGISTER 0x3 /* Read/Write */
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#define MAIN_STATUS_REGISTER 0x4 /* Read */
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#define DATA_RATE_SELECT_REGISTER 0x4 /* Write */
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#define FIFO 0x5 /* Read/Write */
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#define RESERVED_REGISTER 0x6 /* Reserved */
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#define DIGITAL_INPUT_REGISTER 0x7 /* Read; PS/2 Only */
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#define CONFIGURATION_CONTROL_REGISTER 0x7 /* Write; PS/2 Only */
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/* STATUS_REGISTER_A */
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#define DSRA_DIRECTION 0x1
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#define DSRA_WRITE_PROTECT 0x2
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#define DSRA_INDEX 0x4
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#define DSRA_HEAD_1_SELECT 0x8
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#define DSRA_TRACK_0 0x10
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#define DSRA_STEP 0x20
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#define DSRA_SECOND_DRIVE_INSTALLED 0x40
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#define DSRA_INTERRUPT_PENDING 0x80
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/* STATUS_REGISTER_B */
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#define DSRB_MOTOR_ENABLE_0 0x1
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#define DSRB_MOTOR_ENABLE_1 0x2
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#define DSRB_WRITE_ENABLE 0x4
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#define DSRB_READ_DATA 0x8
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#define DSRB_WRITE_DATA 0x10
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#define DSRB_DRIVE_SELECT 0x20
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/* DIGITAL_OUTPUT_REGISTER */
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#define DOR_FLOPPY_DRIVE_SELECT 0x3 /* Covers 2 bits, defined below */
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#define DOR_FDC_ENABLE 0x4 /* from the website */
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#define DOR_RESET 0x4 /* from the Intel guide; 0 = resetting, 1 = enabled */
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#define DOR_DMA_IO_INTERFACE_ENABLE 0x8 /* Reserved on PS/2 */
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#define DOR_FLOPPY_MOTOR_ON_A 0x10
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#define DOR_FLOPPY_MOTOR_ON_B 0x20
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#define DOR_FLOPPY_MOTOR_ON_C 0x40 /* Reserved on PS/2 */
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#define DOR_FLOPPY_MOTOR_ON_D 0x80 /* Reserved on PS/2 */
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/* DOR_FLOPPY_DRIVE_SELECT */
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#define DOR_FLOPPY_DRIVE_SELECT_A 0x0
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#define DOR_FLOPPY_DRIVE_SELECT_B 0x1
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#define DOR_FLOPPY_DRIVE_SELECT_C 0x2 /* Reserved on PS/2 */
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#define DOR_FLOPPY_DRIVE_SELECT_D 0x3 /* Reserved on PS/2 */
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/* MAIN_STATUS_REGISTER */
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#define MSR_FLOPPY_BUSY_0 0x1
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#define MSR_FLOPPY_BUSY_1 0x2
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#define MSR_FLOPPY_BUSY_2 0x4 /* Reserved on PS/2 */
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#define MSR_FLOPPY_BUSY_3 0x8 /* Reserved on PS/2 */
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#define MSR_READ_WRITE_IN_PROGRESS 0x10
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#define MSR_NON_DMA_MODE 0x20
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#define MSR_IO_DIRECTION 0x40 /* Determines meaning of Command Status Registers */
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#define MSR_DATA_REG_READY_FOR_IO 0x80
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/* DATA_RATE_SELECT_REGISTER */
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#define DRSR_DSEL 0x3 /* covers two bits as defined below */
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#define DRSR_PRECOMP 0x1c /* covers three bits as defined below */
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#define DRSR_MBZ 0x20
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#define DRSR_POWER_DOWN 0x40
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#define DRSR_SW_RESET 0x80
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/* DRSR_DSEL */
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#define DRSR_DSEL_500KBPS 0x0
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#define DRSR_DSEL_300KBPS 0x1
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#define DRSR_DSEL_250KBPS 0x2
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#define DRSR_DSEL_1MBPS 0x3
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/* STATUS_REGISTER_0 */
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#define SR0_UNIT_SELECTED_AT_INTERRUPT 0x3 /* Covers two bits as defined below */
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#define SR0_HEAD_NUMBER_AT_INTERRUPT 0x4 /* Values defined below */
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#define SR0_NOT_READY_ON_READ_WRITE 0x8 /* Unused in PS/2 */
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#define SR0_SS_ACCESS_TO_HEAD_1 0x8 /* Unused in PS/2 */
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#define SR0_EQUIPMENT_CHECK 0x10
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#define SR0_SEEK_COMPLETE 0x20
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#define SR0_LAST_COMMAND_STATUS 0xC0 /* Covers two bits as defined below */
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/* SR0_UNIT_SELECTED_AT_INTERRUPT */
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#define SR0_UNIT_SELECTED_A 0x0
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#define SR0_UNIT_SELECTED_B 0x1
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#define SR0_UNIT_SELECTED_C 0x2
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#define SR0_UNIT_SELECTED_D 0x3
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#define SR0_PS2_UNIT_SELECTED_A 0x1 /* PS/2 uses only two drives: A = 01b B = 10b */
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#define SR0_PST_UNIT_SELECTED_B 0x2
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/* SR0_HEAD_NUMBER_AT_INTERRUPT */
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#define SR0_HEAD_0 0x0
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#define SR0_HEAD_1 0x1
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/* SR0_LAST_COMMAND_STATUS */
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#define SR0_LCS_SUCCESS 0x0
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#define SR0_LCS_TERMINATED_ABNORMALLY 0x40
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#define SR0_LCS_INVALID_COMMAND_ISSUED 0x80
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#define SR0_LCS_READY_SIGNAL_CHANGED 0xc0 /* Reserved on PS/2; a/k/a abnormal termination due to polling */
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/* STATUS_REGISTER_1 */
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#define SR1_CANNOT_FIND_ID_ADDRESS 0x1 /* Mimics SR2_WRONG_CYLINDER_DETECTED */
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#define SR1_WRITE_PROTECT_DETECTED 0x2
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#define SR1_CANNOT_FIND_SECTOR_ID 0x4
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#define SR1_OVERRUN 0x10
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#define SR1_CRC_ERROR 0x20
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#define SR1_END_OF_CYLINDER 0x80
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/* STATUS_REGISTER_2 */
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#define SR2_MISSING_ADDRESS_MARK 0x1
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#define SR2_BAD_CYLINDER 0x2
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#define SR2_SCAN_COMMAND_FAILED 0x4
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#define SR2_SCAN_COMMAND_EQUAL 0x8
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#define SR2_WRONG_CYLINDER_DETECTED 0x10 /* Mimics SR1_CANNOT_FIND_ID_ADDRESS */
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#define SR2_CRC_ERROR_IN_SECTOR_DATA 0x20
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#define SR2_SECTOR_WITH_DELETED_DATA 0x40
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/* STATUS_REGISTER_3 */
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#define SR3_UNIT_SELECTED 0x3 /* Covers two bits; defined below */
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#define SR3_SIDE_HEAD_SELECT_STATUS 0x4 /* Values defined below */
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#define SR3_TWO_SIDED_STATUS_SIGNAL 0x8
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#define SR3_TRACK_ZERO_STATUS_SIGNAL 0x10
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#define SR3_READY_STATUS_SIGNAL 0x20
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#define SR3_WRITE_PROTECT_STATUS_SIGNAL 0x40
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#define SR3_FAULT_STATUS_SIGNAL 0x80
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/* SR3_UNIT_SELECTED */
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#define SR3_UNIT_SELECTED_A 0x0
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#define SR3_UNIT_SELECTED_B 0x1
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#define SR3_UNIT_SELECTED_C 0x2
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#define SR3_UNIT_SELECTED_D 0x3
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/* SR3_SIDE_HEAD_SELECT_STATUS */
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#define SR3_SHSS_HEAD_0 0x0
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#define SR3_SHSS_HEAD_1 0x1
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/* DIGITAL_INPUT_REGISTER */
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#define DIR_HIGH_DENSITY_SELECT 0x1
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#define DIR_DISKETTE_CHANGE 0x80
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/* CONFIGURATION_CONTROL_REGISTER */
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#define CCR_DRC 0x3 /* Covers two bits, defined below */
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#define CCR_DRC_0 0x1
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#define CCR_DRC_1 0x2
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/* CCR_DRC */
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#define CCR_DRC_500000 0x0
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#define CCR_DRC_250000 0x2
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/* Commands */
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#define COMMAND_READ_TRACK 0x2
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#define COMMAND_SPECIFY 0x3
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#define COMMAND_SENSE_DRIVE_STATUS 0x4
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#define COMMAND_WRITE_DATA 0x5
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#define COMMAND_READ_DATA 0x6
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#define COMMAND_RECALIBRATE 0x7
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#define COMMAND_SENSE_INTERRUPT_STATUS 0x8
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#define COMMAND_WRITE_DELETED_DATA 0x9
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#define COMMAND_READ_ID 0xA
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#define COMMAND_READ_DELETED_DATA 0xC
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#define COMMAND_FORMAT_TRACK 0xD
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#define COMMAND_SEEK 0xF
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#define COMMAND_VERSION 0x10
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#define COMMAND_SCAN_EQUAL 0x11
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#define COMMAND_CONFIGURE 0x13
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#define COMMAND_SCAN_LOW_OR_EQUAL 0x19
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#define COMMAND_SCAN_HIGH_OR_EQUAL 0x1D
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/* COMMAND_READ_DATA constants */
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#define READ_DATA_DS0 0x1
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#define READ_DATA_DS1 0x2
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#define READ_DATA_HDS 0x4
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#define READ_DATA_SK 0x20
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#define READ_DATA_MFM 0x40
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#define READ_DATA_MT 0x80
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/* COMMAND_READ_ID constants */
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#define READ_ID_MFM 0x40
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/* COMMAND_SPECIFY constants */
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#define SPECIFY_HLT_1M 0x10 /* 16ms; based on intel data sheet */
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#define SPECIFY_HLT_500K 0x8 /* 16ms; based on intel data sheet */
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#define SPECIFY_HLT_300K 0x6 /* 16ms; based on intel data sheet */
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#define SPECIFY_HLT_250K 0x4 /* 16ms; based on intel data sheet */
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#define SPECIFY_HUT_1M 0x0 /* Need to figure out these eight values; 0 is max */
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#define SPECIFY_HUT_500K 0x0
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#define SPECIFY_HUT_300K 0x0
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#define SPECIFY_HUT_250K 0x0
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#define SPECIFY_SRT_1M 0x0
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#define SPECIFY_SRT_500K 0x0
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#define SPECIFY_SRT_300K 0x0
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#define SPECIFY_SRT_250K 0x0
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/* Command byte 1 constants */
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#define COMMAND_UNIT_SELECT 0x3 /* Covers two bits; defined below */
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#define COMMAND_UNIT_SELECT_0 0x1
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#define COMMAND_UNIT_SELECT_1 0x2
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#define COMMAND_HEAD_NUMBER 0x4
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#define COMMAND_HEAD_NUMBER_SHIFT 0x2
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/* COMMAND_VERSION */
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#define VERSION_ENHANCED 0x90
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/* COMMAND_UNIT_SELECT */
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#define CUS_UNIT_0 0x0
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#define CUS_UNIT_1 0x1
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/* COMMAND_CONFIGURE constants */
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#define CONFIGURE_FIFOTHR 0xf
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#define CONFIGURE_POLL 0x10
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#define CONFIGURE_EFIFO 0x20
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#define CONFIGURE_EIS 0x40
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#define CONFIGURE_PRETRK 0xff
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/* Command Head Number Constants */
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#define COMMAND_HEAD_0 0x0
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#define COMMAND_HEAD_1 0x1
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/* Bytes per sector constants */
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#define HW_128_BYTES_PER_SECTOR 0x0
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#define HW_256_BYTES_PER_SECTOR 0x1
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#define HW_512_BYTES_PER_SECTOR 0x2
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#define HW_1024_BYTES_PER_SECTOR 0x3
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/*
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* FUNCTIONS
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*/
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NTSTATUS NTAPI
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HwTurnOnMotor(PDRIVE_INFO DriveInfo);
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NTSTATUS NTAPI
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HwSenseDriveStatus(PDRIVE_INFO DriveInfo);
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NTSTATUS NTAPI
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HwReadWriteData(PCONTROLLER_INFO ControllerInfo,
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BOOLEAN Read,
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UCHAR Unit,
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UCHAR Cylinder,
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UCHAR Head,
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UCHAR Sector,
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UCHAR BytesPerSector,
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UCHAR EndOfTrack,
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UCHAR Gap3Length,
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UCHAR DataLength);
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NTSTATUS NTAPI
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HwRecalibrate(PDRIVE_INFO DriveInfo);
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NTSTATUS NTAPI
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HwSenseInterruptStatus(PCONTROLLER_INFO ControllerInfo);
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NTSTATUS NTAPI
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HwReadId(PDRIVE_INFO DriveInfo, UCHAR Head);
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NTSTATUS NTAPI
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HwFormatTrack(PCONTROLLER_INFO ControllerInfo,
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UCHAR Unit,
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UCHAR Head,
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UCHAR BytesPerSector,
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UCHAR SectorsPerTrack,
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UCHAR Gap3Length,
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UCHAR FillerPattern);
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NTSTATUS NTAPI
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HwSeek(PDRIVE_INFO DriveInfo, UCHAR Cylinder);
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NTSTATUS NTAPI
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HwReadWriteResult(PCONTROLLER_INFO ControllerInfo);
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NTSTATUS NTAPI
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HwGetVersion(PCONTROLLER_INFO ControllerInfo);
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NTSTATUS NTAPI
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HwConfigure(PCONTROLLER_INFO ControllerInfo,
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BOOLEAN EIS,
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BOOLEAN EFIFO,
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BOOLEAN POLL,
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UCHAR FIFOTHR,
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UCHAR PRETRK) ;
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NTSTATUS NTAPI
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HwRecalibrateResult(PCONTROLLER_INFO ControllerInfo);
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NTSTATUS NTAPI
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HwDiskChanged(PDRIVE_INFO DriveInfo,
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PBOOLEAN DiskChanged);
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NTSTATUS NTAPI
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HwSenseDriveStatusResult(PCONTROLLER_INFO ControllerInfo,
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PUCHAR Status);
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NTSTATUS NTAPI
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HwSpecify(PCONTROLLER_INFO ControllerInfo,
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UCHAR HeadLoadTime,
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UCHAR HeadUnloadTime,
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UCHAR StepRateTime,
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BOOLEAN NonDma);
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NTSTATUS NTAPI
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HwReadIdResult(PCONTROLLER_INFO ControllerInfo,
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PUCHAR CurCylinder,
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PUCHAR CurHead);
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NTSTATUS NTAPI
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HwSetDataRate(PCONTROLLER_INFO ControllerInfo, UCHAR DataRate);
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NTSTATUS NTAPI
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HwReset(PCONTROLLER_INFO Controller);
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NTSTATUS NTAPI
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HwPowerOff(PCONTROLLER_INFO ControllerInfo);
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VOID NTAPI
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HwDumpRegisters(PCONTROLLER_INFO ControllerInfo);
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NTSTATUS NTAPI
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HwTurnOffMotor(PCONTROLLER_INFO ControllerInfo);
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