mirror of
https://github.com/reactos/reactos.git
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2e8b524c99
- Re-implement DMA buffer routines. It is now faster and consumes less memory overhead per allocated memory block. - IoGetDeviceProperty needs a PDO - Add few comments - No need to clear buffer twice in CreateQueueHead / CreateDescriptor svn path=/branches/cmake-bringup/; revision=51324
320 lines
8.2 KiB
C
320 lines
8.2 KiB
C
#pragma once
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#include <ntddk.h>
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/* USB Command Register */
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#define EHCI_USBCMD 0x00
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#define EHCI_USBSTS 0x04
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#define EHCI_USBINTR 0x08
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#define EHCI_FRINDEX 0x0C
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#define EHCI_CTRLDSSEGMENT 0x10
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#define EHCI_PERIODICLISTBASE 0x14
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#define EHCI_ASYNCLISTBASE 0x18
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#define EHCI_CONFIGFLAG 0x40
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#define EHCI_PORTSC 0x44
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/* USB Interrupt Register Flags 32 Bits */
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#define EHCI_USBINTR_INTE 0x01
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#define EHCI_USBINTR_ERR 0x02
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#define EHCI_USBINTR_PC 0x04
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#define EHCI_USBINTR_FLROVR 0x08
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#define EHCI_USBINTR_HSERR 0x10
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#define EHCI_USBINTR_ASYNC 0x20
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/* Bits 6:31 Reserved */
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/* Status Register Flags 32 Bits */
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#define EHCI_STS_INT 0x01
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#define EHCI_STS_ERR 0x02
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#define EHCI_STS_PCD 0x04
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#define EHCI_STS_FLR 0x08
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#define EHCI_STS_FATAL 0x10
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#define EHCI_STS_IAA 0x20
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/* Bits 11:6 Reserved */
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#define EHCI_STS_HALT 0x1000
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#define EHCI_STS_RECL 0x2000
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#define EHCI_STS_PSS 0x4000
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#define EHCI_STS_ASS 0x8000
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#define EHCI_ERROR_INT ( EHCI_STS_FATAL | EHCI_STS_ERR )
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/* Last bit in QUEUE ELEMENT TRANSFER DESCRIPTOR Next Pointer */
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/* Used for Queue Element Transfer Descriptor Pointers
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and Queue Head Horizontal Link Pointers */
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#define TERMINATE_POINTER 0x01
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/* QUEUE ELEMENT TRANSFER DESCRIPTOR, Token defines and structs */
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/* PIDCodes for QETD_TOKEN
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OR with QUEUE_TRANSFER_DESCRIPTOR Token.PIDCode*/
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#define PID_CODE_OUT_TOKEN 0x00
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#define PID_CODE_IN_TOKEN 0x01
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#define PID_CODE_SETUP_TOKEN 0x02
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/* Split Transaction States
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OR with QUEUE_TRANSFER_DESCRIPTOR Token.SplitTransactionState */
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#define DO_START_SPLIT 0x00
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#define DO_COMPLETE_SPLIT 0x01
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/* Ping States, OR with QUEUE_TRANSFER_DESCRIPTOR Token. */
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#define PING_STATE_DO_OUT 0x00
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#define PING_STATE_DO_PING 0x01
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typedef struct _PERIODICFRAMELIST
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{
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PULONG VirtualAddr;
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PHYSICAL_ADDRESS PhysicalAddr;
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ULONG Size;
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} PERIODICFRAMELIST, *PPERIODICFRAMELIST;
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/* QUEUE ELEMENT TRANSFER DESCRIPTOR TOKEN */
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typedef struct _QETD_TOKEN_BITS
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{
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ULONG PingState:1;
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ULONG SplitTransactionState:1;
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ULONG MissedMicroFrame:1;
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ULONG TransactionError:1;
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ULONG BabbleDetected:1;
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ULONG DataBufferError:1;
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ULONG Halted:1;
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ULONG Active:1;
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ULONG PIDCode:2;
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ULONG ErrorCounter:2;
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ULONG CurrentPage:3;
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ULONG InterruptOnComplete:1;
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ULONG TotalBytesToTransfer:15;
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ULONG DataToggle:1;
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} QETD_TOKEN_BITS, *PQETD_TOKEN_BITS;
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/* QUEUE ELEMENT TRANSFER DESCRIPTOR */
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typedef struct _QUEUE_TRANSFER_DESCRIPTOR
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{
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//Hardware
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ULONG NextPointer;
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ULONG AlternateNextPointer;
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union
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{
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QETD_TOKEN_BITS Bits;
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ULONG DWord;
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} Token;
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ULONG BufferPointer[5];
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//Software
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ULONG PhysicalAddr;
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struct _QUEUE_TRANSFER_DESCRIPTOR *PreviousDescriptor;
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struct _QUEUE_TRANSFER_DESCRIPTOR *NextDescriptor;
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} QUEUE_TRANSFER_DESCRIPTOR, *PQUEUE_TRANSFER_DESCRIPTOR;
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/* EndPointSpeeds of END_POINT_CHARACTERISTICS */
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#define QH_ENDPOINT_FULLSPEED 0x00
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#define QH_ENDPOINT_LOWSPEED 0x01
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#define QH_ENDPOINT_HIGHSPEED 0x02
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typedef struct _END_POINT_CHARACTERISTICS
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{
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ULONG DeviceAddress:7;
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ULONG InactiveOnNextTransaction:1;
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ULONG EndPointNumber:4;
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ULONG EndPointSpeed:2;
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ULONG QEDTDataToggleControl:1;
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ULONG HeadOfReclamation:1;
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ULONG MaximumPacketLength:11;
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ULONG ControlEndPointFlag:1;
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ULONG NakCountReload:4;
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} END_POINT_CHARACTERISTICS, *PEND_POINT_CHARACTERISTICS;
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typedef struct _END_POINT_CAPABILITIES
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{
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ULONG InterruptScheduleMask:8;
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ULONG SplitCompletionMask:8;
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ULONG HubAddr:6;
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ULONG PortNumber:6;
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/* Multi */
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ULONG NumberOfTransactionPerFrame:2;
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} END_POINT_CAPABILITIES, *PEND_POINT_CAPABILITIES;
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/* QUEUE HEAD defines and structs */
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/* QUEUE HEAD Select Types, OR with QUEUE_HEAD HorizontalLinkPointer */
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#define QH_TYPE_IDT 0x00
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#define QH_TYPE_QH 0x02
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#define QH_TYPE_SITD 0x04
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#define QH_TYPE_FSTN 0x06
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/* QUEUE HEAD */
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typedef struct _QUEUE_HEAD
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{
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//Hardware
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ULONG HorizontalLinkPointer;
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END_POINT_CHARACTERISTICS EndPointCharacteristics;
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END_POINT_CAPABILITIES EndPointCapabilities;
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/* TERMINATE_POINTER not valid for this member */
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ULONG CurrentLinkPointer;
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/* TERMINATE_POINTER valid */
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ULONG NextPointer;
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/* TERMINATE_POINTER valid, bits 1:4 is NAK_COUNTER */
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ULONG AlternateNextPointer;
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/* Only DataToggle, InterruptOnComplete, ErrorCounter, PingState valid */
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union
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{
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QETD_TOKEN_BITS Bits;
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ULONG DWord;
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} Token;
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ULONG BufferPointer[5];
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//Software
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ULONG PhysicalAddr;
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struct _QUEUE_HEAD *PreviousQueueHead;
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struct _QUEUE_HEAD *NextQueueHead;
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PQUEUE_TRANSFER_DESCRIPTOR TransferDescriptor;
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PIRP IrpToComplete;
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PMDL MdlToFree;
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PKEVENT Event;
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} QUEUE_HEAD, *PQUEUE_HEAD;
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/* USBCMD register 32 bits */
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typedef struct _EHCI_USBCMD_CONTENT
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{
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ULONG Run : 1;
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ULONG HCReset : 1;
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ULONG FrameListSize : 2;
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ULONG PeriodicEnable : 1;
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ULONG AsyncEnable : 1;
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ULONG DoorBell : 1;
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ULONG LightReset : 1;
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ULONG AsyncParkCount : 2;
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ULONG Reserved : 1;
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ULONG AsyncParkEnable : 1;
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ULONG Reserved1 : 4;
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ULONG IntThreshold : 8;
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ULONG Reserved2 : 8;
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} EHCI_USBCMD_CONTENT, *PEHCI_USBCMD_CONTENT;
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typedef struct _EHCI_USBSTS_CONTENT
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{
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ULONG USBInterrupt:1;
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ULONG ErrorInterrupt:1;
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ULONG DetectChangeInterrupt:1;
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ULONG FrameListRolloverInterrupt:1;
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ULONG HostSystemErrorInterrupt:1;
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ULONG AsyncAdvanceInterrupt:1;
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ULONG Reserved:6;
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ULONG HCHalted:1;
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ULONG Reclamation:1;
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ULONG PeriodicScheduleStatus:1;
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ULONG AsynchronousScheduleStatus:1;
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} EHCI_USBSTS_CONTEXT, *PEHCI_USBSTS_CONTEXT;
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typedef struct _EHCI_USBPORTSC_CONTENT
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{
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ULONG CurrentConnectStatus:1;
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ULONG ConnectStatusChange:1;
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ULONG PortEnabled:1;
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ULONG PortEnableChanged:1;
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ULONG OverCurrentActive:1;
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ULONG OverCurrentChange:1;
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ULONG ForcePortResume:1;
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ULONG Suspend:1;
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ULONG PortReset:1;
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ULONG Reserved:1;
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ULONG LineStatus:2;
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ULONG PortPower:1;
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ULONG PortOwner:1;
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} EHCI_USBPORTSC_CONTENT, *PEHCI_USBPORTSC_CONTENT;
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typedef struct _EHCI_HCS_CONTENT
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{
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ULONG PortCount : 4;
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ULONG PortPowerControl: 1;
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ULONG Reserved : 2;
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ULONG PortRouteRules : 1;
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ULONG PortPerCHC : 4;
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ULONG CHCCount : 4;
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ULONG PortIndicator : 1;
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ULONG Reserved2 : 3;
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ULONG DbgPortNum : 4;
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ULONG Reserved3 : 8;
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} EHCI_HCS_CONTENT, *PEHCI_HCS_CONTENT;
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typedef struct _EHCI_HCC_CONTENT
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{
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ULONG CurAddrBits : 1;
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ULONG VarFrameList : 1;
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ULONG ParkMode : 1;
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ULONG Reserved : 1;
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ULONG IsoSchedThreshold : 4;
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ULONG EECPCapable : 8;
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ULONG Reserved2 : 16;
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} EHCI_HCC_CONTENT, *PEHCI_HCC_CONTENT;
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typedef struct _EHCI_CAPS {
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UCHAR Length;
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UCHAR Reserved;
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USHORT HCIVersion;
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union
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{
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EHCI_HCS_CONTENT HCSParams;
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ULONG HCSParamsLong;
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};
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ULONG HCCParams;
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UCHAR PortRoute [8];
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} EHCI_CAPS, *PEHCI_CAPS;
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typedef struct
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{
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PKSPIN_LOCK Lock;
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RTL_BITMAP Bitmap;
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PULONG BitmapBuffer;
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ULONG BlockSize;
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PVOID VirtualBase;
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PHYSICAL_ADDRESS PhysicalBase;
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ULONG Length;
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}DMA_MEMORY_ALLOCATOR, *LPDMA_MEMORY_ALLOCATOR;
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typedef struct _EHCI_HOST_CONTROLLER
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{
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ULONG OpRegisters;
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EHCI_CAPS ECHICaps;
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PVOID CommonBufferVA;
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PHYSICAL_ADDRESS CommonBufferPA;
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ULONG CommonBufferSize;
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PQUEUE_HEAD AsyncListQueue;
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KSPIN_LOCK Lock;
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LPDMA_MEMORY_ALLOCATOR DmaMemAllocator;
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} EHCI_HOST_CONTROLLER, *PEHCI_HOST_CONTROLLER;
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ULONG
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ReadControllerStatus(PEHCI_HOST_CONTROLLER hcd);
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VOID
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ClearControllerStatus(PEHCI_HOST_CONTROLLER hcd, ULONG Status);
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VOID
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GetCapabilities(PEHCI_CAPS PCap, ULONG CapRegister);
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VOID
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ResetPort(PEHCI_HOST_CONTROLLER hcd, UCHAR Port);
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VOID
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StartEhci(PEHCI_HOST_CONTROLLER hcd);
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VOID
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StopEhci(PEHCI_HOST_CONTROLLER hcd);
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VOID
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SetAsyncListQueueRegister(PEHCI_HOST_CONTROLLER hcd, ULONG PhysicalAddr);
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ULONG
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GetAsyncListQueueRegister(PEHCI_HOST_CONTROLLER hcd);
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VOID
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SetPeriodicFrameListRegister(PEHCI_HOST_CONTROLLER hcd, ULONG PhysicalAddr);
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ULONG
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GetPeriodicFrameListRegister(PEHCI_HOST_CONTROLLER hcd);
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