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46831c537f
While the BIOS support for INT10h emulation has been set up, any modification of the display should wait until the kernel requests video initialization with INBV/bootvid. The latter will call HalResetDisplay() (that calls HalpBiosDisplayReset()) at the correct time. This avoids an useless video mode change and reset when booting ReactOS.
524 lines
14 KiB
C
524 lines
14 KiB
C
/*
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* PROJECT: ReactOS HAL
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* LICENSE: GPL, See COPYING in the top level directory
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* FILE: hal/halx86/amd64/x86bios.c
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* PURPOSE:
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* PROGRAMMERS: Timo Kreuzer (timo.kreuzer@reactos.org)
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*/
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/* INCLUDES ******************************************************************/
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#include <hal.h>
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//#define NDEBUG
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#include <debug.h>
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#include <fast486.h>
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/* GLOBALS *******************************************************************/
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/* This page serves as fallback for pages used by Mm */
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PFN_NUMBER x86BiosFallbackPfn;
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BOOLEAN x86BiosIsInitialized;
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LONG x86BiosBufferIsAllocated = 0;
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PUCHAR x86BiosMemoryMapping;
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/* This the physical address of the bios buffer */
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ULONG64 x86BiosBufferPhysical;
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VOID
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NTAPI
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DbgDumpPage(PUCHAR MemBuffer, USHORT Segment)
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{
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ULONG x, y, Offset;
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for (y = 0; y < 0x100; y++)
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{
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for (x = 0; x < 0x10; x++)
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{
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Offset = Segment * 16 + y * 16 + x;
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DbgPrint("%02x ", MemBuffer[Offset]);
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}
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DbgPrint("\n");
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}
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}
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VOID
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NTAPI
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HalInitializeBios(
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_In_ ULONG Phase,
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_In_ PLOADER_PARAMETER_BLOCK LoaderBlock)
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{
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PPFN_NUMBER PfnArray;
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PFN_NUMBER Pfn, Last;
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PMEMORY_ALLOCATION_DESCRIPTOR Descriptor;
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PLIST_ENTRY ListEntry;
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PMDL Mdl;
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ULONG64 PhysicalAddress;
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if (Phase == 0)
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{
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/* Allocate one page for a fallback mapping */
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PhysicalAddress = HalpAllocPhysicalMemory(LoaderBlock,
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0x100000,
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1,
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FALSE);
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if (PhysicalAddress == 0)
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{
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ASSERT(FALSE);
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}
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x86BiosFallbackPfn = PhysicalAddress / PAGE_SIZE;
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ASSERT(x86BiosFallbackPfn != 0);
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/* Allocate a page for the buffer allocation */
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x86BiosBufferPhysical = HalpAllocPhysicalMemory(LoaderBlock,
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0x100000,
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1,
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FALSE);
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if (x86BiosBufferPhysical == 0)
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{
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ASSERT(FALSE);
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}
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}
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else
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{
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/* Allocate an MDL for 1MB */
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Mdl = IoAllocateMdl(NULL, 0x100000, FALSE, FALSE, NULL);
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if (!Mdl)
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{
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ASSERT(FALSE);
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}
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/* Get pointer to the pfn array */
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PfnArray = MmGetMdlPfnArray(Mdl);
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/* Fill the array with the fallback page */
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for (Pfn = 0; Pfn < 0x100; Pfn++)
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{
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PfnArray[Pfn] = x86BiosFallbackPfn;
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}
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/* Loop the memory descriptors */
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for (ListEntry = LoaderBlock->MemoryDescriptorListHead.Flink;
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ListEntry != &LoaderBlock->MemoryDescriptorListHead;
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ListEntry = ListEntry->Flink)
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{
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/* Get the memory descriptor */
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Descriptor = CONTAINING_RECORD(ListEntry,
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MEMORY_ALLOCATION_DESCRIPTOR,
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ListEntry);
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/* Check if the memory is in the low 1 MB range */
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if (Descriptor->BasePage < 0x100)
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{
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/* Check if the memory type is firmware */
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if ((Descriptor->MemoryType == LoaderFirmwarePermanent) ||
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(Descriptor->MemoryType == LoaderSpecialMemory))
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{
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/* It's firmware, so map it! */
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Last = min(Descriptor->BasePage + Descriptor->PageCount, 0x100);
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for (Pfn = Descriptor->BasePage; Pfn < Last; Pfn++)
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{
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/* Set each physical page in the MDL */
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PfnArray[Pfn] = Pfn;
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}
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}
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}
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}
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/* Map this page proper, too */
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Pfn = x86BiosBufferPhysical / PAGE_SIZE;
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PfnArray[Pfn] = Pfn;
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Mdl->MdlFlags = MDL_PAGES_LOCKED;
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/* Map the MDL to system space */
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x86BiosMemoryMapping = MmGetSystemAddressForMdlSafe(Mdl, HighPagePriority);
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ASSERT(x86BiosMemoryMapping);
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DPRINT1("*x86BiosMemoryMapping: %p, %p\n",
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*(PVOID*)x86BiosMemoryMapping, *(PVOID*)(x86BiosMemoryMapping + 8));
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//DbgDumpPage(x86BiosMemoryMapping, 0xc351);
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x86BiosIsInitialized = TRUE;
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}
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}
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NTSTATUS
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NTAPI
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x86BiosAllocateBuffer(
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_In_ ULONG *Size,
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_In_ USHORT *Segment,
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_In_ USHORT *Offset)
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{
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/* Check if the system is initialized and the buffer is large enough */
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if (!x86BiosIsInitialized || (*Size > PAGE_SIZE))
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{
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/* Something was wrong, fail! */
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return STATUS_INSUFFICIENT_RESOURCES;
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}
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/* Check if the buffer is already allocated */
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if (InterlockedBitTestAndSet(&x86BiosBufferIsAllocated, 0))
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{
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/* Buffer was already allocated, fail */
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return STATUS_INSUFFICIENT_RESOURCES;
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}
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/* The buffer is sufficient, return hardcoded address and size */
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*Size = PAGE_SIZE;
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*Segment = x86BiosBufferPhysical / 16;
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*Offset = 0;
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return STATUS_SUCCESS;
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}
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NTSTATUS
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NTAPI
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x86BiosFreeBuffer(
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_In_ USHORT Segment,
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_In_ USHORT Offset)
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{
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/* Check if the system is initialized and if the address matches */
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if (!x86BiosIsInitialized || (Segment != 0x2000) || (Offset != 0))
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{
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/* Something was wrong, fail */
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return STATUS_INVALID_PARAMETER;
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}
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/* Check if the buffer was allocated */
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if (!InterlockedBitTestAndReset(&x86BiosBufferIsAllocated, 0))
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{
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/* It was not, fail */
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return STATUS_INVALID_PARAMETER;
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}
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/* Buffer is freed, nothing more to do */
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return STATUS_SUCCESS;
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}
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NTSTATUS
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NTAPI
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x86BiosReadMemory(
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_In_ USHORT Segment,
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_In_ USHORT Offset,
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_Out_writes_bytes_(Size) PVOID Buffer,
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_In_ ULONG Size)
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{
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ULONG_PTR Address;
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/* Calculate the physical address */
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Address = (Segment << 4) + Offset;
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/* Check if it's valid */
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if (!x86BiosIsInitialized || ((Address + Size) > 0x100000))
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{
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/* Invalid */
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return STATUS_INVALID_PARAMETER;
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}
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/* Copy the memory to the buffer */
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RtlCopyMemory(Buffer, x86BiosMemoryMapping + Address, Size);
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/* Return success */
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return STATUS_SUCCESS;
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}
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NTSTATUS
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NTAPI
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x86BiosWriteMemory(
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_In_ USHORT Segment,
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_In_ USHORT Offset,
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_In_reads_bytes_(Size) PVOID Buffer,
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_In_ ULONG Size)
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{
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ULONG_PTR Address;
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/* Calculate the physical address */
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Address = (Segment << 4) + Offset;
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/* Check if it's valid */
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if (!x86BiosIsInitialized || ((Address + Size) > 0x100000))
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{
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/* Invalid */
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return STATUS_INVALID_PARAMETER;
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}
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/* Copy the memory from the buffer */
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RtlCopyMemory(x86BiosMemoryMapping + Address, Buffer, Size);
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/* Return success */
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return STATUS_SUCCESS;
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}
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static
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VOID
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FASTCALL
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x86MemRead(
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PFAST486_STATE State,
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ULONG Address,
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PVOID Buffer,
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ULONG Size)
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{
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/* Validate the address range */
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if (((ULONG64)Address + Size) < 0x100000)
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{
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RtlCopyMemory(Buffer, x86BiosMemoryMapping + Address, Size);
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}
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else
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{
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RtlFillMemory(Buffer, Size, 0xCC);
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DPRINT1("x86MemRead: invalid read at 0x%lx (size 0x%lx)\n", Address, Size);
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}
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}
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static
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VOID
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FASTCALL
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x86MemWrite(
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PFAST486_STATE State,
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ULONG Address,
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PVOID Buffer,
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ULONG Size)
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{
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/* Validate the address range */
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if (((ULONG64)Address + Size) < 0x100000)
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{
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RtlCopyMemory(x86BiosMemoryMapping + Address, Buffer, Size);
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}
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else
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{
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DPRINT1("x86MemWrite: invalid write at 0x%lx (size 0x%lx)\n", Address, Size);
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}
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}
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static
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BOOLEAN
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ValidatePort(
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USHORT Port,
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UCHAR Size,
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BOOLEAN IsWrite)
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{
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switch (Port)
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{
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// VGA: https://wiki.osdev.org/VGA_Hardware#Port_0x3C0
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case 0x3C0: return (Size == 1) && IsWrite;
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case 0x3C1: return (Size == 1) && !IsWrite;
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case 0x3C2: return (Size == 1) && IsWrite;
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case 0x3C4: return IsWrite;
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case 0x3C5: return (Size <= 2);
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case 0x3C7: return (Size == 1) && IsWrite;
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case 0x3CC: return (Size == 1) && !IsWrite;
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case 0x3CE: return IsWrite;
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case 0x3CF: return (Size <= 2);
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case 0x3D4: return IsWrite;
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case 0x3D5: return (Size <= 2);
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case 0x3C6: return (Size == 1);
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case 0x3C8: return (Size == 1) && IsWrite;
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case 0x3C9: return (Size == 1);
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case 0x3DA: return (Size == 1) && !IsWrite;
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// OVMF debug messages used by VBox / QEMU
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// https://www.virtualbox.org/svn/vbox/trunk/src/VBox/Devices/EFI/Firmware/OvmfPkg/README
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case 0x402: return (Size == 1) && IsWrite;
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// BOCHS VBE: https://forum.osdev.org/viewtopic.php?f=1&t=14639
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case 0x1CE: return (Size == 1) && IsWrite;
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case 0x1CF: return (Size == 1);
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// CHECKME!
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case 0x3B6: return (Size <= 2);
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}
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/* Allow but report unknown ports, we trust the BIOS for now */
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DPRINT1("Unknown port 0x%x, size %d, write %d\n", Port, Size, IsWrite);
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return TRUE;
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}
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static
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VOID
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FASTCALL
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x86IoRead(
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PFAST486_STATE State,
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USHORT Port,
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PVOID Buffer,
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ULONG DataCount,
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UCHAR DataSize)
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{
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/* Validate the port */
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if (!ValidatePort(Port, DataSize, FALSE))
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{
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DPRINT1("Invalid IO port read access (port: 0x%x, count: 0x%x)\n", Port, DataSize);
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}
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switch (DataSize)
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{
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case 1: READ_PORT_BUFFER_UCHAR((PUCHAR)(ULONG_PTR)Port, Buffer, DataCount); return;
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case 2: READ_PORT_BUFFER_USHORT((PUSHORT)(ULONG_PTR)Port, Buffer, DataCount); return;
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case 4: READ_PORT_BUFFER_ULONG((PULONG)(ULONG_PTR)Port, Buffer, DataCount); return;
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}
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}
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static
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VOID
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FASTCALL
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x86IoWrite(
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PFAST486_STATE State,
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USHORT Port,
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PVOID Buffer,
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ULONG DataCount,
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UCHAR DataSize)
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{
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/* Validate the port */
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if (!ValidatePort(Port, DataSize, TRUE))
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{
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DPRINT1("Invalid IO port write access (port: 0x%x, count: 0x%x)\n", Port, DataSize);
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}
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switch (DataSize)
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{
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case 1: WRITE_PORT_BUFFER_UCHAR((PUCHAR)(ULONG_PTR)Port, Buffer, DataCount); return;
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case 2: WRITE_PORT_BUFFER_USHORT((PUSHORT)(ULONG_PTR)Port, Buffer, DataCount); return;
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case 4: WRITE_PORT_BUFFER_ULONG((PULONG)(ULONG_PTR)Port, Buffer, DataCount); return;
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}
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}
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static
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VOID
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FASTCALL
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x86BOP(
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PFAST486_STATE State,
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UCHAR BopCode)
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{
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ASSERT(FALSE);
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}
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static
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UCHAR
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FASTCALL
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x86IntAck (
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PFAST486_STATE State)
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{
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ASSERT(FALSE);
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return 0;
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}
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BOOLEAN
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NTAPI
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x86BiosCall(
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_In_ ULONG InterruptNumber,
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_Inout_ PX86_BIOS_REGISTERS Registers)
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{
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const ULONG StackBase = 0x2000;
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FAST486_STATE EmulatorContext;
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ULONG FlatIp;
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PUCHAR InstructionPointer;
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/* Initialize the emulator context */
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Fast486Initialize(&EmulatorContext,
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x86MemRead,
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x86MemWrite,
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x86IoRead,
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x86IoWrite,
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x86BOP,
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x86IntAck,
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NULL, // FpuCallback,
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NULL); // Tlb
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/* Copy the registers */
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EmulatorContext.GeneralRegs[FAST486_REG_EAX].Long = Registers->Eax;
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EmulatorContext.GeneralRegs[FAST486_REG_EBX].Long = Registers->Ebx;
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EmulatorContext.GeneralRegs[FAST486_REG_ECX].Long = Registers->Ecx;
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EmulatorContext.GeneralRegs[FAST486_REG_EDX].Long = Registers->Edx;
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EmulatorContext.GeneralRegs[FAST486_REG_ESI].Long = Registers->Esi;
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EmulatorContext.GeneralRegs[FAST486_REG_EDI].Long = Registers->Edi;
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EmulatorContext.SegmentRegs[FAST486_REG_DS].Selector = Registers->SegDs;
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EmulatorContext.SegmentRegs[FAST486_REG_ES].Selector = Registers->SegEs;
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/* Set Eflags */
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EmulatorContext.Flags.Long = 0;
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EmulatorContext.Flags.AlwaysSet = 1;
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EmulatorContext.Flags.If = 1;
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/* Set up the INT stub */
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FlatIp = StackBase - 4;
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InstructionPointer = x86BiosMemoryMapping + FlatIp;
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InstructionPointer[0] = 0xCD; // INT instruction
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InstructionPointer[1] = (UCHAR)InterruptNumber;
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InstructionPointer[2] = 0x90; // NOP. We will stop at this address.
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/* Set the stack pointer */
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Fast486SetStack(&EmulatorContext, 0, StackBase - 8);
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/* Start execution at the INT stub */
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Fast486ExecuteAt(&EmulatorContext, 0x00, FlatIp);
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while (TRUE)
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{
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/* Get the current flat IP */
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FlatIp = (EmulatorContext.SegmentRegs[FAST486_REG_CS].Selector << 4) +
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EmulatorContext.InstPtr.Long;
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/* Make sure we haven't left the allowed memory range */
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if (FlatIp >= 0x100000)
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{
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DPRINT1("x86BiosCall: invalid IP (0x%lx) during BIOS execution\n", FlatIp);
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return FALSE;
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}
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/* Check if we returned from our int stub */
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if (FlatIp == (StackBase - 2))
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{
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/* We are done! */
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break;
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}
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/* Emulate one instruction */
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Fast486StepInto(&EmulatorContext);
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}
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/* Copy the registers back */
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Registers->Eax = EmulatorContext.GeneralRegs[FAST486_REG_EAX].Long;
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Registers->Ebx = EmulatorContext.GeneralRegs[FAST486_REG_EBX].Long;
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Registers->Ecx = EmulatorContext.GeneralRegs[FAST486_REG_ECX].Long;
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Registers->Edx = EmulatorContext.GeneralRegs[FAST486_REG_EDX].Long;
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Registers->Esi = EmulatorContext.GeneralRegs[FAST486_REG_ESI].Long;
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Registers->Edi = EmulatorContext.GeneralRegs[FAST486_REG_EDI].Long;
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Registers->SegDs = EmulatorContext.SegmentRegs[FAST486_REG_DS].Selector;
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Registers->SegEs = EmulatorContext.SegmentRegs[FAST486_REG_ES].Selector;
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return TRUE;
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}
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#ifdef _M_AMD64
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BOOLEAN
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NTAPI
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HalpBiosDisplayReset(VOID)
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{
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#if 0
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X86_BIOS_REGISTERS Registers;
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ULONG OldEflags;
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/* Save flags and disable interrupts */
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OldEflags = __readeflags();
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_disable();
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/* Set AH = 0 (Set video mode), AL = 0x12 (640x480x16 vga) */
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Registers.Eax = 0x12;
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/* Call INT 0x10 */
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x86BiosCall(0x10, &Registers);
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// FIXME: check result
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/* Restore previous flags */
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__writeeflags(OldEflags);
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return TRUE;
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#else
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/* This x64 HAL does NOT currently handle display reset (TODO) */
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return FALSE;
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#endif
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}
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#endif // _M_AMD64
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