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https://github.com/reactos/reactos.git
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c501d8112c
svn path=/branches/aicom-network-fixes/; revision=34994
747 lines
16 KiB
ArmAsm
747 lines
16 KiB
ArmAsm
/*
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* FILE: hal/halx86/generic/irq.S
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* COPYRIGHT: See COPYING in the top level directory
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* PURPOSE: Software, System and Hardware IRQ Management
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* PROGRAMMER: Alex Ionescu (alex@relsoft.net)
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*/
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/* INCLUDES ******************************************************************/
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#include <asm.h>
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#include <internal/i386/asmmacro.S>
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.intel_syntax noprefix
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/* GLOBALS *******************************************************************/
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PICInitTable:
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/* Master PIC */
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.short 0x20 /* Port */
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.byte 0x11 /* Edge,, cascade, CAI 8, ICW4 */
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.byte PRIMARY_VECTOR_BASE /* Base */
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.byte 4 /* IRQ 4 connected to slave */
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.byte 1 /* Non buffered, not nested, 8086 */
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/* Slave PIC */
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.short 0xA0 /* Port */
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.byte 0x11 /* Edge, cascade, CAI 8, ICW4 */
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.byte PRIMARY_VECTOR_BASE + 8 /* Base */
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.byte 2 /* Slave ID: Slave 2 */
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.byte 1 /* Non buffered, not nested, 8086 */
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/* End of initialization table */
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.short 0
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KiI8259MaskTable:
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.long 0 /* IRQL 0 */
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.long 0 /* IRQL 1 */
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.long 0 /* IRQL 2 */
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.long 0 /* IRQL 3 */
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.long 0xFF800000 /* IRQL 4 */
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.long 0xFFC00000 /* IRQL 5 */
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.long 0xFFE00000 /* IRQL 6 */
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.long 0xFFF00000 /* IRQL 7 */
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.long 0xFFF80000 /* IRQL 8 */
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.long 0xFFFC0000 /* IRQL 9 */
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.long 0xFFFE0000 /* IRQL 10 */
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.long 0xFFFF0000 /* IRQL 11 */
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.long 0xFFFF8000 /* IRQL 12 */
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.long 0xFFFFC000 /* IRQL 13 */
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.long 0xFFFFE000 /* IRQL 14 */
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.long 0xFFFFF000 /* IRQL 15 */
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.long 0xFFFFF800 /* IRQL 16 */
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.long 0xFFFFFC00 /* IRQL 17 */
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.long 0xFFFFFE00 /* IRQL 18 */
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.long 0xFFFFFE00 /* IRQL 19 */
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.long 0xFFFFFE80 /* IRQL 20 */
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.long 0xFFFFFEC0 /* IRQL 21 */
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.long 0xFFFFFEE0 /* IRQL 22 */
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.long 0xFFFFFEF0 /* IRQL 23 */
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.long 0xFFFFFEF8 /* IRQL 24 */
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.long 0xFFFFFEF8 /* IRQL 25 */
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.long 0xFFFFFEFA /* IRQL 26 */
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.long 0xFFFFFFFA /* IRQL 27 */
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.long 0xFFFFFFFB /* IRQL 28 */
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.long 0xFFFFFFFB /* IRQL 29 */
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.long 0xFFFFFFFB /* IRQL 30 */
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.long 0xFFFFFFFB /* IRQL 31 */
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HalpSysIntHandler:
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.rept 7
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.long GenericIRQ /* IRQ 0-7 */
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.endr
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.long IRQ7 /* IRQ 7 */
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.rept 7
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.long GenericIRQ /* IRQ 8-15 */
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.endr
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.long IRQ15 /* IRQ 15 */
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.rept 20
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.long GenericIRQ /* IRQ 16-35 */
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.endr
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#if DBG
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.rept 172
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.long InvalidIRQ /* IRQ 36-207 */
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#endif
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.endr
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SoftIntByteTable:
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.byte PASSIVE_LEVEL /* IRR 0 */
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.byte PASSIVE_LEVEL /* IRR 1 */
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.byte APC_LEVEL /* IRR 2 */
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.byte APC_LEVEL /* IRR 3 */
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.byte DISPATCH_LEVEL /* IRR 4 */
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.byte DISPATCH_LEVEL /* IRR 5 */
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.byte DISPATCH_LEVEL /* IRR 6 */
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.byte DISPATCH_LEVEL /* IRR 7 */
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SoftIntHandlerTable:
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.long _KiUnexpectedInterrupt /* PASSIVE_LEVEL */
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.long _HalpApcInterrupt /* APC_LEVEL */
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.long _HalpDispatchInterrupt /* DISPATCH_LEVEL */
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SoftIntHandlerTable2:
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.long _KiUnexpectedInterrupt /* PASSIVE_LEVEL */
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.long _HalpApcInterrupt2ndEntry /* APC_LEVEL */
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.long _HalpDispatchInterrupt2ndEntry /* DISPATCH_LEVEL */
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_UnhandledMsg:
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.asciz "\n\x7\x7!!! Unhandled or Unexpected Code at line: %lx!!!\n"
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/* FUNCTIONS *****************************************************************/
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.globl _HalpInitPICs@0
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.func HalpInitPICs@0
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_HalpInitPICs@0:
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/* Save ESI and disable interrupts */
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push esi
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pushf
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cli
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/* Read the init table */
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lea esi, PICInitTable
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lodsw
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InitLoop:
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/* Put the port in EDX */
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movzx edx, ax
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/* Initialize the PIC, using a delay for each command */
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outsb
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jmp $+2
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inc edx
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outsb
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jmp $+2
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outsb
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jmp $+2
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outsb
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jmp $+2
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/* Mask all interrupts */
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mov al, 0xFF
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out dx, al
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/* Check if we're done, otherwise initialize next PIC */
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lodsw
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cmp ax, 0
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jnz InitLoop
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/* Restore interrupts and return */
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popf
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pop esi
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ret
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.endfunc
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.globl @HalClearSoftwareInterrupt@4
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.func @HalClearSoftwareInterrupt@4, @HalClearSoftwareInterrupt@4
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@HalClearSoftwareInterrupt@4:
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/* Get IRR mask */
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mov eax, 1
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shl eax, cl
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not eax
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/* Set IRR */
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and PCR[KPCR_IRR], eax
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ret
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.endfunc
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.globl @HalRequestSoftwareInterrupt@4
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.func @HalRequestSoftwareInterrupt@4, @HalRequestSoftwareInterrupt@4
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@HalRequestSoftwareInterrupt@4:
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/* Get IRR mask */
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mov eax, 1
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shl eax, cl
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/* Disable interrupts */
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pushf
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cli
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/* Set IRR and get IRQL */
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or PCR[KPCR_IRR], eax
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mov ecx, PCR[KPCR_IRQL]
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/* Get software IRR mask */
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mov eax, PCR[KPCR_IRR]
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and eax, 3
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/* Get highest pending software interrupt and check if it's higher */
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xor edx, edx
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mov dl, SoftIntByteTable[eax]
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cmp dl, cl
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jbe AfterCall
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/* Call the pending interrupt */
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call SoftIntHandlerTable[edx*4]
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AfterCall:
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/* Retore interrupts and return */
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popf
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ret
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.endfunc
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.globl _HalDisableSystemInterrupt@8
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.func HalDisableSystemInterrupt@8
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_HalDisableSystemInterrupt@8:
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/* Convert to vector */
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movzx ecx, byte ptr [esp+4]
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sub ecx, PRIMARY_VECTOR_BASE
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/* Disable interrupts and set the new IDR */
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mov edx, 1
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shl edx, cl
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cli
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or PCR[KPCR_IDR], edx
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/* Get the current mask */
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xor eax, eax
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in al, 0xA1
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shl eax, 8
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in al, 0x21
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/* Mask off the interrupt and write the new mask */
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or eax, edx
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out 0x21, al
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shr eax, 8
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out 0xA1, al
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/* Return with interrupts enabled */
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in al, 0xA1
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sti
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ret 8
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.endfunc
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.globl _HalEnableSystemInterrupt@12
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.func HalEnableSystemInterrupt@12
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_HalEnableSystemInterrupt@12:
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/* Get the vector and validate it */
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movzx ecx, byte ptr [esp+4]
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sub ecx, PRIMARY_VECTOR_BASE
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jb Invalid
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cmp ecx, CLOCK2_LEVEL
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jnb Invalid
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/* Get the current PCI Edge/Level control registers */
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mov edx, 0x4D1
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in al, dx
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shl ax, 8
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mov edx, 0x4D0
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in al, dx
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mov dx, 1
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shl dx, cl
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and dx, 0xDEF8
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/* Check if this is a latched interrupt */
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cmp dword ptr [esp+12], 0
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jnz Latched
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/* Use OR for edge interrupt */
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or ax, dx
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jmp AfterMask
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Latched:
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/* Mask it out for level interrupt */
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not dx
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and ax, dx
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AfterMask:
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/* Set the PCI Edge/Level control registers */
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mov edx, 0x4D0
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out dx, al
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shr ax, 8
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mov edx, 0x4D1
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out dx, al
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/* Calculate the new IDR */
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mov eax, 1
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shl eax, cl
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not eax
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cli
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and PCR[KPCR_IDR], eax
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/* Get the current IRQL and mask the IRQs in the PIC */
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mov eax, PCR[KPCR_IRQL]
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mov eax, KiI8259MaskTable[eax*4]
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or eax, PCR[KPCR_IDR]
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out 0x21, al
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shr eax, 8
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out 0xA1, al
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/* Enable interrupts and return TRUE */
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sti
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mov eax, 1
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ret 12
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Invalid:
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/* Fail, invalid IRQ */
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#if DBG
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int 3
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#endif
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xor eax, eax
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ret 12
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.endfunc
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.globl _HalBeginSystemInterrupt@12
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.func HalBeginSystemInterrupt@12
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_HalBeginSystemInterrupt@12:
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/* Convert to IRQ and call the handler */
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movzx ebx, byte ptr [esp+8]
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sub ebx, PRIMARY_VECTOR_BASE
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jmp HalpSysIntHandler[ebx*4]
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IRQ15:
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/* This is IRQ 15, check if it's spurious */
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mov al, 0xB
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out 0xA0, al
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jmp $+2
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in al, 0xA0
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test al, 0x80
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jnz GenericIRQ
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/* Cascaded interrupt... dismiss it and return FALSE */
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mov al, 0x62
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out 0x20, al
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mov eax, 0
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ret 12
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IRQ7:
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/* This is IRQ 7, check if it's spurious */
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mov al, 0xB
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out 0x20, al
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jmp $+2
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in al, 0x20
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test al, 0x80
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jnz GenericIRQ
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/* It is, return FALSE */
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mov eax, 0
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ret 12
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GenericIRQ:
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/* Return the current IRQL */
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mov eax, [esp+12]
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mov ecx, PCR[KPCR_IRQL]
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mov [eax], cl
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/* Set the new IRQL */
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movzx eax, byte ptr [esp+4]
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mov PCR[KPCR_IRQL], eax
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/* Set IRQ mask in the PIC */
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mov eax, KiI8259MaskTable[eax*4]
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or eax, PCR[KPCR_IDR]
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out 0x21, al
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shr eax, 8
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out 0xA1, al
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/* Check to which PIC the EOI was sent */
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mov eax, ebx
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cmp eax, 8
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jnb Pic1
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/* Write mask to master PIC */
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or al, 0x60
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out 0x20, al
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jmp DoneBegin
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Pic1:
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/* Write mask to slave PIC */
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mov al, 0x20
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out 0xA0, al
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mov al, 0x62
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out 0x20, al
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DoneBegin:
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/* Enable interrupts and return TRUE */
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in al, 0x21
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sti
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mov eax, 1
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ret 12
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#if DBG
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InvalidIRQ:
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/* Dismiss it */
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mov eax, 0
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ret 12
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#endif
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.endfunc
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.globl _HalEndSystemInterrupt@8
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.func HalEndSystemInterrupt@8
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_HalEndSystemInterrupt@8:
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/* Get the IRQL and check if it's a software interrupt */
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movzx ecx, byte ptr [esp+4]
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cmp dword ptr PCR[KPCR_IRQL], DISPATCH_LEVEL
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jbe SkipMask2
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/* Hardware interrupt, mask the appropriate IRQs in the PIC */
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mov eax, KiI8259MaskTable[ecx*4]
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or eax, PCR[KPCR_IDR]
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out 0x21, al
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shr eax, 8
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out 0xA1, al
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SkipMask2:
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/* Set IRQL and check if there are pending software interrupts */
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mov PCR[KPCR_IRQL], ecx
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mov eax, PCR[KPCR_IRR]
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mov al, SoftIntByteTable[eax]
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cmp al, cl
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ja DoCall
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ret 8
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DoCall:
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/* There are pending software interrupts, call their handlers */
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add esp, 12
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jmp SoftIntHandlerTable2[eax*4]
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.endfunc
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.globl @KfLowerIrql@4
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.func @KfLowerIrql@4
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_@KfLowerIrql@4:
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@KfLowerIrql@4:
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/* Save flags since we'll disable interrupts */
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pushf
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/* Validate IRQL */
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movzx ecx, cl
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#if DBG
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cmp cl, PCR[KPCR_IRQL]
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ja InvalidIrql
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#endif
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/* Disable interrupts and check if IRQL is below DISPATCH_LEVEL */
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cmp dword ptr PCR[KPCR_IRQL], DISPATCH_LEVEL
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cli
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jbe SkipMask
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/* Clear interrupt masks since there's a pending hardware interrupt */
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mov eax, KiI8259MaskTable[ecx*4]
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or eax, PCR[KPCR_IDR]
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out 0x21, al
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shr eax, 8
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out 0xA1, al
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SkipMask:
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/* Set the new IRQL and check if there's a pending software interrupt */
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mov PCR[KPCR_IRQL], ecx
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mov eax, PCR[KPCR_IRR]
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mov al, SoftIntByteTable[eax]
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cmp al, cl
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ja DoCall3
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/* Restore interrupts and return */
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popf
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ret
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#if DBG
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InvalidIrql:
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/* Set HIGH_LEVEL */
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mov eax, PCR[KPCR_IRQL]
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mov dword ptr PCR[KPCR_IRQL], HIGH_LEVEL
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/* Bugcheck the system */
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push 3
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push 0
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push ecx
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push eax
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push IRQL_NOT_LESS_OR_EQUAL
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call _KeBugCheckEx@20
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#endif
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DoCall3:
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/* There is, call it */
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call SoftIntHandlerTable[eax*4]
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/* Restore interrupts and return */
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popf
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ret
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.endfunc
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.globl @KfRaiseIrql@4
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.func @KfRaiseIrql@4
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_@KfRaiseIrql@4:
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@KfRaiseIrql@4:
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/* Get the IRQL */
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mov eax, PCR[KPCR_IRQL]
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movzx ecx, cl
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#if DBG
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/* Validate it */
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cmp eax, ecx
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ja InvalidKfRaise
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#endif
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/* Check if it's in the software level */
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cmp cl, DISPATCH_LEVEL
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jbe SetIrql
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/* Save the current IRQL */
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mov edx, eax
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/* It's a hardware IRQL, so disable interrupts */
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pushf
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cli
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/* Set the new IRQL */
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mov PCR[KPCR_IRQL], cl
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/* Mask the interrupts in the PIC */
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mov eax, KiI8259MaskTable[ecx*4]
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or eax, PCR[KPCR_IDR]
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out 0x21, al
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shr eax, 8
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out 0xA1, al
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/* Restore interrupts and return old IRQL */
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popf
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mov eax, edx
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ret
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SetIrql:
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/* Set the IRQL and return */
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mov PCR[KPCR_IRQL], ecx
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ret
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#if DBG
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InvalidKfRaise:
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/* Set to passive */
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mov dword ptr PCR[KPCR_IRQL], PASSIVE_LEVEL
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/* Bugcheck the system */
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push 9
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push 0
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push ecx
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push eax
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push IRQL_NOT_GREATER_OR_EQUAL
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call _KeBugCheckEx@20
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#endif
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.endfunc
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.globl _KeGetCurrentIrql@0
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.func KeGetCurrentIrql@0
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_KeGetCurrentIrql@0:
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/* Return the IRQL */
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mov eax, PCR[KPCR_IRQL]
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ret
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.endfunc
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.globl _KeRaiseIrqlToDpcLevel@0
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.func KeRaiseIrqlToDpcLevel@0
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_KeRaiseIrqlToDpcLevel@0:
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/* Get the current IRQL */
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mov eax, PCR[KPCR_IRQL]
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/* Set DISPATCH_LEVEL */
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mov dword ptr PCR[KPCR_IRQL], DISPATCH_LEVEL
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#if DBG
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/* Make sure we were not higher then dispatch */
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cmp eax, DISPATCH_LEVEL
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ja InvalidRaise
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#endif
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ret
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#if DBG
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InvalidRaise:
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/* Bugcheck the system */
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push 1
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push 0
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push DISPATCH_LEVEL
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push eax
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push IRQL_NOT_GREATER_OR_EQUAL
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call _KeBugCheckEx@20
|
|
#endif
|
|
.endfunc
|
|
|
|
.globl _KeRaiseIrqlToSynchLevel@0
|
|
.func KeRaiseIrqlToSynchLevel@0
|
|
_KeRaiseIrqlToSynchLevel@0:
|
|
|
|
/* Disable interrupts */
|
|
pushf
|
|
cli
|
|
|
|
/* Mask out interrupts */
|
|
mov eax, KiI8259MaskTable[DISPATCH_LEVEL*4]
|
|
or eax, PCR[KPCR_IDR]
|
|
out 0x21, al
|
|
shr eax, 8
|
|
out 0xA1, al
|
|
|
|
/* Return the old IRQL, enable interrupts and set to DISPATCH */
|
|
mov eax, PCR[KPCR_IRQL]
|
|
mov dword ptr PCR[KPCR_IRQL], DISPATCH_LEVEL
|
|
popf
|
|
|
|
#if DBG
|
|
/* Validate raise */
|
|
cmp eax, DISPATCH_LEVEL
|
|
ja InvalidSyRaise
|
|
#endif
|
|
|
|
/* Return */
|
|
ret
|
|
|
|
#if DBG
|
|
InvalidSyRaise:
|
|
/* Bugcheck the system */
|
|
push 2
|
|
push 0
|
|
push DISPATCH_LEVEL
|
|
push eax
|
|
push IRQL_NOT_GREATER_OR_EQUAL
|
|
call _KeBugCheckEx@20
|
|
#endif
|
|
.endfunc
|
|
|
|
.globl _HalpApcInterrupt
|
|
.func HalpApcInterrupt
|
|
TRAP_FIXUPS hapc_a, hapc_t, DoFixupV86, DoFixupAbios
|
|
_HalpApcInterrupt:
|
|
|
|
/* Create fake interrupt stack */
|
|
pop eax
|
|
pushf
|
|
push cs
|
|
push eax
|
|
|
|
/* Enter interrupt */
|
|
INT_PROLOG hapc_a, hapc_t, DoPushFakeErrorCode
|
|
.endfunc
|
|
|
|
.globl _HalpApcInterrupt2ndEntry
|
|
.func HalpApcInterrupt2ndEntry
|
|
_HalpApcInterrupt2ndEntry:
|
|
|
|
/* Save current IRQL and set to APC level */
|
|
push PCR[KPCR_IRQL]
|
|
mov dword ptr PCR[KPCR_IRQL], APC_LEVEL
|
|
and dword ptr PCR[KPCR_IRR], ~(1 << APC_LEVEL)
|
|
|
|
/* Enable interrupts and check if we came from User/V86 mode */
|
|
sti
|
|
mov eax, [ebp+KTRAP_FRAME_CS]
|
|
and eax, MODE_MASK
|
|
test dword ptr [ebp+KTRAP_FRAME_EFLAGS], EFLAGS_V86_MASK
|
|
jz DeliverApc
|
|
|
|
/* Set user mode delivery */
|
|
or eax, UserMode
|
|
|
|
DeliverApc:
|
|
|
|
/* Deliver the APCs */
|
|
push ebp
|
|
push 0
|
|
push eax
|
|
call _KiDeliverApc@12
|
|
|
|
/* Disable interrupts and end it */
|
|
cli
|
|
call _HalpEndSoftwareInterrupt@4
|
|
jmp _Kei386EoiHelper@0
|
|
.endfunc
|
|
|
|
.globl _HalpDispatchInterrupt
|
|
.func HalpDispatchInterrupt
|
|
TRAP_FIXUPS hdpc_a, hdpc_t, DoFixupV86, DoFixupAbios
|
|
_HalpDispatchInterrupt:
|
|
|
|
/* Create fake interrupt stack */
|
|
pop eax
|
|
pushf
|
|
push cs
|
|
push eax
|
|
|
|
/* Enter interrupt */
|
|
INT_PROLOG hdpc_a, hdpc_t, DoPushFakeErrorCode
|
|
.endfunc
|
|
|
|
.globl _HalpDispatchInterrupt2ndEntry
|
|
.func HalpDispatchInterrupt2ndEntry
|
|
_HalpDispatchInterrupt2ndEntry:
|
|
|
|
/* Save current IRQL and set to DPC level */
|
|
push PCR[KPCR_IRQL]
|
|
mov dword ptr PCR[KPCR_IRQL], DISPATCH_LEVEL
|
|
and dword ptr PCR[KPCR_IRR], ~(1 << DISPATCH_LEVEL)
|
|
|
|
/* Enable interrupts and let the kernel handle this */
|
|
sti
|
|
call _KiDispatchInterrupt@0
|
|
|
|
/* Disable interrupts and end it */
|
|
cli
|
|
call _HalpEndSoftwareInterrupt@4
|
|
jmp _Kei386EoiHelper@0
|
|
.endfunc
|
|
|
|
.globl _HalpEndSoftwareInterrupt@4
|
|
.func HalpEndSoftwareInterrupt@4
|
|
_HalpEndSoftwareInterrupt@4:
|
|
|
|
/* Get the IRQL and check if we're in the software region */
|
|
movzx ecx, byte ptr [esp+4]
|
|
cmp dword ptr PCR[KPCR_IRQL], DISPATCH_LEVEL
|
|
jbe SoftwareInt
|
|
|
|
/* Set the right mask in the PIC for the hardware IRQ */
|
|
mov eax, KiI8259MaskTable[ecx*4]
|
|
or eax, PCR[KPCR_IDR]
|
|
out 0x21, al
|
|
shr eax, 8
|
|
out 0xA1, al
|
|
|
|
SoftwareInt:
|
|
/* Check if there are pending software interrupts */
|
|
mov PCR[KPCR_IRQL], ecx
|
|
mov eax, PCR[KPCR_IRR]
|
|
mov al, SoftIntByteTable[eax]
|
|
cmp al, cl
|
|
ja DoCall2
|
|
ret 4
|
|
|
|
DoCall2:
|
|
/* There are pending softwate interrupts, call their handlers */
|
|
add esp, 8
|
|
jmp SoftIntHandlerTable2[eax*4]
|
|
.endfunc
|