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https://github.com/reactos/reactos.git
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c0c57e2324
- Fix IRP handling, add missing IRP handlers - Specify the device name for DO - The legacy IRQ descriptor is edge-triggered - Improve pool tagging - Place the PNP code in a pageable section CORE-17256
147 lines
3.8 KiB
C
147 lines
3.8 KiB
C
/*
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* PROJECT: PCI IDE bus driver extension
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* LICENSE: See COPYING in the top level directory
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* PURPOSE: Common header file
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* COPYRIGHT: Copyright 2005 Hervé Poussineau <hpoussin@reactos.org>
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* Copyright 2023 Dmitry Borisov <di.sean@protonmail.com>
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*/
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#ifndef _PCIIDEX_PCH_
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#define _PCIIDEX_PCH_
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#include <ntddk.h>
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#include <ntstrsafe.h>
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#include <ntintsafe.h>
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#include <initguid.h>
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#include <wdmguid.h>
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#include <ide.h>
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#define TAG_PCIIDEX 'XedI'
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#define IS_FDO(p) (((PCOMMON_DEVICE_EXTENSION)(p))->IsFDO)
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#define IS_PRIMARY_CHANNEL(PdoExtension) (PdoExtension->Channel == 0)
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/*
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* Legacy ranges and interrupts
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*/
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#define PCIIDE_LEGACY_RESOURCE_COUNT 3
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#define PCIIDE_LEGACY_COMMAND_IO_RANGE_LENGTH 8
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#define PCIIDE_LEGACY_CONTROL_IO_RANGE_LENGTH 1
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#define PCIIDE_LEGACY_PRIMARY_COMMAND_BASE 0x1F0
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#define PCIIDE_LEGACY_PRIMARY_CONTROL_BASE 0x3F6
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#define PCIIDE_LEGACY_PRIMARY_IRQ 14
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#define PCIIDE_LEGACY_SECONDARY_COMMAND_BASE 0x170
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#define PCIIDE_LEGACY_SECONDARY_CONTROL_BASE 0x376
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#define PCIIDE_LEGACY_SECONDARY_IRQ 15
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/*
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* Programming Interface Register
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*/
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#define PCIIDE_PROGIF_PRIMARY_CHANNEL_NATIVE_MODE 0x01
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#define PCIIDE_PROGIF_PRIMARY_CHANNEL_NATIVE_MODE_CAPABLE 0x02
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#define PCIIDE_PROGIF_SECONDARY_CHANNEL_NATIVE_MODE 0x04
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#define PCIIDE_PROGIF_SECONDARY_CHANNEL_NATIVE_MODE_CAPABLE 0x08
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#define PCIIDE_PROGIF_DMA_CAPABLE 0x80
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#define BM_SECONDARY_CHANNEL_OFFSET 8
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typedef struct _PDO_DEVICE_EXTENSION PDO_DEVICE_EXTENSION, *PPDO_DEVICE_EXTENSION;
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typedef struct _PCIIDEX_DRIVER_EXTENSION
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{
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PCONTROLLER_PROPERTIES HwGetControllerProperties;
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ULONG MiniControllerExtensionSize;
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} PCIIDEX_DRIVER_EXTENSION, *PPCIIDEX_DRIVER_EXTENSION;
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typedef struct _COMMON_DEVICE_EXTENSION
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{
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BOOLEAN IsFDO;
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PDEVICE_OBJECT Self;
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_Write_guarded_by_(_Global_interlock_)
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volatile LONG PageFiles;
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_Write_guarded_by_(_Global_interlock_)
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volatile LONG HibernateFiles;
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_Write_guarded_by_(_Global_interlock_)
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volatile LONG DumpFiles;
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} COMMON_DEVICE_EXTENSION, *PCOMMON_DEVICE_EXTENSION;
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typedef struct _FDO_DEVICE_EXTENSION
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{
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COMMON_DEVICE_EXTENSION Common;
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PDEVICE_OBJECT Ldo;
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ULONG ControllerNumber;
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BOOLEAN InNativeMode;
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BOOLEAN IoBaseMapped;
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BOOLEAN MiniportStarted;
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FAST_MUTEX DeviceSyncMutex;
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_Guarded_by_(DeviceSyncMutex)
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PPDO_DEVICE_EXTENSION Channels[MAX_IDE_CHANNEL];
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USHORT VendorId;
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USHORT DeviceId;
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PDRIVER_OBJECT DriverObject;
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PUCHAR BusMasterPortBase;
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KSPIN_LOCK BusDataLock;
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BUS_INTERFACE_STANDARD BusInterface;
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IDE_CONTROLLER_PROPERTIES Properties;
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/* Must be the last entry */
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PUCHAR MiniControllerExtension[0];
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} FDO_DEVICE_EXTENSION, *PFDO_DEVICE_EXTENSION;
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typedef struct _PDO_DEVICE_EXTENSION
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{
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COMMON_DEVICE_EXTENSION Common;
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ULONG Channel;
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PFDO_DEVICE_EXTENSION ParentController;
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BOOLEAN ReportedMissing;
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PUCHAR IoBase;
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} PDO_DEVICE_EXTENSION, *PPDO_DEVICE_EXTENSION;
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CODE_SEG("PAGE")
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DRIVER_INITIALIZE DriverEntry;
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CODE_SEG("PAGE")
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DRIVER_UNLOAD PciIdeXUnload;
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CODE_SEG("PAGE")
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DRIVER_ADD_DEVICE PciIdeXAddDevice;
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_Dispatch_type_(IRP_MJ_PNP)
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CODE_SEG("PAGE")
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DRIVER_DISPATCH_PAGED PciIdeXDispatchPnp;
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_Dispatch_type_(IRP_MJ_SYSTEM_CONTROL)
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CODE_SEG("PAGE")
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DRIVER_DISPATCH_PAGED PciIdeXDispatchWmi;
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_Dispatch_type_(IRP_MJ_POWER)
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DRIVER_DISPATCH_RAISED PciIdeXDispatchPower;
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CODE_SEG("PAGE")
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NTSTATUS
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PciIdeXFdoDispatchPnp(
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_In_ PFDO_DEVICE_EXTENSION FdoExtension,
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_Inout_ PIRP Irp);
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CODE_SEG("PAGE")
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NTSTATUS
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PciIdeXStartMiniport(
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_In_ PFDO_DEVICE_EXTENSION FdoExtension);
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CODE_SEG("PAGE")
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IDE_CHANNEL_STATE
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PciIdeXChannelState(
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_In_ PFDO_DEVICE_EXTENSION FdoExtension,
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_In_ ULONG Channel);
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#endif /* _PCIIDEX_PCH_ */
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