mirror of
https://github.com/reactos/reactos.git
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6c0c23cb53
- Sync with trunk head (r50270) - This also reverts r49298. svn path=/branches/cmake-bringup/; revision=50271
275 lines
8.1 KiB
C
275 lines
8.1 KiB
C
/*
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* PROJECT: ReactOS Universal Serial Bus Bulk Enhanced Host Controller Interface
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* LICENSE: GPL - See COPYING in the top level directory
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* FILE: drivers/usb/usbehci/hardware.c
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* PURPOSE: Hardware related routines.
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* PROGRAMMERS:
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* Michael Martin (michael.martin@reactos.org)
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*/
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#include "hardware.h"
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#define NDEBUG
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#include <debug.h>
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//FORCEINLINE
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VOID
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SetAsyncListQueueRegister(PEHCI_HOST_CONTROLLER hcd, ULONG PhysicalAddr)
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{
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ULONG OpRegisters = hcd->OpRegisters;
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WRITE_REGISTER_ULONG((PULONG)(OpRegisters + EHCI_ASYNCLISTBASE), PhysicalAddr);
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}
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//FORCEINLINE
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ULONG
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GetAsyncListQueueRegister(PEHCI_HOST_CONTROLLER hcd)
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{
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ULONG OpRegisters = hcd->OpRegisters;
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return READ_REGISTER_ULONG((PULONG)(OpRegisters + EHCI_ASYNCLISTBASE));
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}
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//FORCEINLINE
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VOID
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SetPeriodicFrameListRegister(PEHCI_HOST_CONTROLLER hcd, ULONG PhysicalAddr)
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{
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ULONG OpRegisters = hcd->OpRegisters;
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WRITE_REGISTER_ULONG((PULONG)(OpRegisters + EHCI_PERIODICLISTBASE), PhysicalAddr);
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}
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//FORCEINLINE
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ULONG
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GetPeriodicFrameListRegister(PEHCI_HOST_CONTROLLER hcd)
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{
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ULONG OpRegisters = hcd->OpRegisters;
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return READ_REGISTER_ULONG((PULONG) (OpRegisters + EHCI_PERIODICLISTBASE));
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}
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//FORCEINLINE
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ULONG
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ReadControllerStatus(PEHCI_HOST_CONTROLLER hcd)
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{
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ULONG OpRegisters = hcd->OpRegisters;
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return READ_REGISTER_ULONG ((PULONG) (OpRegisters + EHCI_USBSTS));
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}
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//FORCEINLINE
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VOID
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ClearControllerStatus(PEHCI_HOST_CONTROLLER hcd, ULONG Status)
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{
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ULONG OpRegisters = hcd->OpRegisters;
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WRITE_REGISTER_ULONG((PULONG) (OpRegisters + EHCI_USBSTS), Status);
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}
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VOID
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ResetPort(PEHCI_HOST_CONTROLLER hcd, UCHAR Port)
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{
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ULONG tmp;
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ULONG OpRegisters = hcd->OpRegisters;
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DPRINT1("Reset Port %x\n", Port);
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tmp = READ_REGISTER_ULONG((PULONG) ((OpRegisters + EHCI_PORTSC) + (4 * Port)));
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if (tmp & 0x400)
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{
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DPRINT1("Non HighSpeed device connected. Releasing ownership.\n");
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WRITE_REGISTER_ULONG((PULONG) ((OpRegisters + EHCI_PORTSC) + (4 * Port)), 0x2000);
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}
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/* Get current port state */
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tmp = READ_REGISTER_ULONG((PULONG) ((OpRegisters + EHCI_PORTSC) + (4 * Port)));
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/* Set reset and clear enable */
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tmp |= 0x100;
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tmp &= ~0x04;
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WRITE_REGISTER_ULONG((PULONG) ((OpRegisters + EHCI_PORTSC) + (4 * Port)), tmp);
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/* USB 2.0 Spec 10.2.8.1, more than 50ms */
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KeStallExecutionProcessor(100);
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/* Clear reset */
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tmp &= ~0x100;
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WRITE_REGISTER_ULONG((PULONG) ((OpRegisters + EHCI_PORTSC) + (4 * Port)), tmp);
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KeStallExecutionProcessor(100);
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tmp = READ_REGISTER_ULONG((PULONG) ((OpRegisters + EHCI_PORTSC) + (4 * Port)));
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if (tmp & 0x100)
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{
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DPRINT1("EHCI ERROR: Port Reset did not complete!\n");
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}
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}
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VOID
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StopEhci(PEHCI_HOST_CONTROLLER hcd)
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{
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ULONG OpRegisters = hcd->OpRegisters;
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PEHCI_USBCMD_CONTENT UsbCmd;
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PEHCI_USBSTS_CONTEXT UsbSts;
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LONG FailSafe;
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LONG tmp;
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DPRINT1("Stopping Ehci controller\n");
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WRITE_REGISTER_ULONG((PULONG) (OpRegisters + EHCI_USBINTR), 0);
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tmp = READ_REGISTER_ULONG((PULONG) (OpRegisters + EHCI_USBCMD));
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UsbCmd = (PEHCI_USBCMD_CONTENT) & tmp;
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UsbCmd->Run = FALSE;
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WRITE_REGISTER_ULONG((PULONG) (OpRegisters + EHCI_USBCMD), tmp);
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/* Wait for the device to stop */
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for (FailSafe = 100; FailSafe > 1; FailSafe++)
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{
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KeStallExecutionProcessor(10);
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tmp = READ_REGISTER_ULONG((PULONG)(OpRegisters + EHCI_USBSTS));
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UsbSts = (PEHCI_USBSTS_CONTEXT)&tmp;
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if (UsbSts->HCHalted)
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{
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break;
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}
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}
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if (!UsbSts->HCHalted)
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DPRINT1("EHCI ERROR: Controller is not responding to Stop request!\n");
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}
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VOID
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StartEhci(PEHCI_HOST_CONTROLLER hcd)
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{
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ULONG OpRegisters = hcd->OpRegisters;
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PEHCI_USBCMD_CONTENT UsbCmd;
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PEHCI_USBSTS_CONTEXT UsbSts;
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LONG FailSafe;
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LONG tmp;
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LONG tmp2;
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DPRINT("Starting Ehci controller\n");
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tmp = READ_REGISTER_ULONG((PULONG)(OpRegisters + EHCI_USBSTS));
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UsbSts = (PEHCI_USBSTS_CONTEXT)&tmp;
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if (!UsbSts->HCHalted)
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{
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StopEhci(hcd);
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}
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tmp = READ_REGISTER_ULONG ((PULONG)(OpRegisters + EHCI_USBCMD));
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/* Reset the device */
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UsbCmd = (PEHCI_USBCMD_CONTENT) &tmp;
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UsbCmd->HCReset = TRUE;
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WRITE_REGISTER_ULONG ((PULONG)(OpRegisters + EHCI_USBCMD), tmp);
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/* Wait for the device to reset */
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for (FailSafe = 100; FailSafe > 1; FailSafe++)
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{
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KeStallExecutionProcessor(10);
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tmp = READ_REGISTER_ULONG((PULONG)(OpRegisters + EHCI_USBCMD));
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UsbCmd = (PEHCI_USBCMD_CONTENT)&tmp;
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if (!UsbCmd->HCReset)
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{
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break;
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}
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DPRINT("Waiting for reset, USBCMD: %x\n", READ_REGISTER_ULONG ((PULONG)(OpRegisters + EHCI_USBCMD)));
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}
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if (UsbCmd->HCReset)
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{
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DPRINT1("EHCI ERROR: Controller failed to reset! Will attempt to continue.\n");
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}
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UsbCmd = (PEHCI_USBCMD_CONTENT) &tmp;
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/* Disable Interrupts on the device */
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WRITE_REGISTER_ULONG((PULONG)(OpRegisters + EHCI_USBINTR), 0);
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/* Clear the Status */
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WRITE_REGISTER_ULONG((PULONG)(OpRegisters + EHCI_USBSTS), 0x0000001f);
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WRITE_REGISTER_ULONG((PULONG)(OpRegisters + EHCI_CTRLDSSEGMENT), 0);
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SetAsyncListQueueRegister(hcd, hcd->AsyncListQueue->PhysicalAddr | QH_TYPE_QH);
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/* Set the ansync and periodic to disable */
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UsbCmd->PeriodicEnable = FALSE;
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UsbCmd->AsyncEnable = TRUE;
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WRITE_REGISTER_ULONG((PULONG)(OpRegisters + EHCI_USBCMD), tmp);
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/* Set the threshold */
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UsbCmd->IntThreshold = 1;
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WRITE_REGISTER_ULONG((PULONG)(OpRegisters + EHCI_USBCMD), tmp);
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/* Turn back on interrupts */
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WRITE_REGISTER_ULONG((PULONG)(OpRegisters + EHCI_USBINTR),
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EHCI_USBINTR_ERR | EHCI_USBINTR_ASYNC | EHCI_USBINTR_HSERR
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/*| EHCI_USBINTR_FLROVR*/ | EHCI_USBINTR_PC);
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WRITE_REGISTER_ULONG((PULONG)(OpRegisters + EHCI_USBINTR),
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EHCI_USBINTR_INTE | EHCI_USBINTR_ERR | EHCI_USBINTR_ASYNC | EHCI_USBINTR_HSERR
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/*| EHCI_USBINTR_FLROVR*/ | EHCI_USBINTR_PC);
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UsbCmd->Run = TRUE;
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WRITE_REGISTER_ULONG((PULONG)(OpRegisters + EHCI_USBCMD), tmp);
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/* Wait for the device to start */
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for (;;)
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{
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KeStallExecutionProcessor(10);
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tmp2 = READ_REGISTER_ULONG((PULONG)(OpRegisters + EHCI_USBSTS));
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UsbSts = (PEHCI_USBSTS_CONTEXT)&tmp2;
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if (!UsbSts->HCHalted)
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{
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break;
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}
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DPRINT("Waiting for start, USBSTS: %x\n", READ_REGISTER_ULONG ((PULONG)(OpRegisters + EHCI_USBSTS)));
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}
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/* Set all port routing to ECHI controller */
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WRITE_REGISTER_ULONG((PULONG)(OpRegisters + EHCI_CONFIGFLAG), 1);
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}
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VOID
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GetCapabilities(PEHCI_CAPS PCap, ULONG CapRegister)
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{
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PEHCI_HCS_CONTENT PHCS;
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LONG i;
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if (!PCap)
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return;
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PCap->Length = READ_REGISTER_UCHAR((PUCHAR)CapRegister);
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PCap->Reserved = READ_REGISTER_UCHAR((PUCHAR)(CapRegister + 1));
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PCap->HCIVersion = READ_REGISTER_USHORT((PUSHORT)(CapRegister + 2));
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PCap->HCSParamsLong = READ_REGISTER_ULONG((PULONG)(CapRegister + 4));
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PCap->HCCParams = READ_REGISTER_ULONG((PULONG)(CapRegister + 8));
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DPRINT1("Length %d\n", PCap->Length);
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DPRINT1("Reserved %d\n", PCap->Reserved);
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DPRINT1("HCIVersion %x\n", PCap->HCIVersion);
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DPRINT1("HCSParams %x\n", PCap->HCSParamsLong);
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DPRINT1("HCCParams %x\n", PCap->HCCParams);
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if (PCap->HCCParams & 0x02)
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DPRINT1("Frame list size is configurable\n");
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if (PCap->HCCParams & 0x01)
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DPRINT1("64bit address mode not supported!\n");
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DPRINT1("Number of Ports: %d\n", PCap->HCSParams.PortCount);
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if (PCap->HCSParams.PortPowerControl)
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DPRINT1("Port Power Control is enabled\n");
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if (!PCap->HCSParams.CHCCount)
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{
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DPRINT1("Number of Companion Host controllers %x\n", PCap->HCSParams.CHCCount);
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DPRINT1("Number of Ports Per CHC: %d\n", PCap->HCSParams.PortPerCHC);
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}
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PHCS = (PEHCI_HCS_CONTENT)&PCap->HCSParams;
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if (PHCS->PortRouteRules)
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{
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for (i = 0; i < PCap->HCSParams.PortCount; i++)
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{
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PCap->PortRoute[i] = READ_REGISTER_UCHAR((PUCHAR) (CapRegister + 12 + i));
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}
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}
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}
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