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fa8f26e7c6
Adding stw for dissembler and converting (PPC and IA32) Fixing a counter bug in ConvertBitToByte, ConvertBitToByte32, GetMaskByte, GetMaskByte32 we did miss one bit calculation when we count the mask the bit 0 svn path=/trunk/; revision=25527
78 lines
3.3 KiB
Plaintext
78 lines
3.3 KiB
Plaintext
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PowerPC 32bits
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reg = R0-R31
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#imm = a value you set
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Bit expain
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0 = mean bit is zero
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1 = mean bit is set
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2 = mean this bit can be 0 or 1
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opcode Name Desciptions
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0010 0000 0000 0000 1000 0000 0100 1110 blr return from a functions
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0222 2222 2222 2222 2222 2222 0011 1000 Li reg,#imm move a value to a register
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2222 2222 2222 2222 2222 2222 1001 0022 stw reg,mem store a value into memory
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2222 2222 2222 2222 2222 2222 1001 0122 stwu reg,mem store contain of reg to memory and
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move reg to that memory position
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Here how the primary opcode work
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xxxx xxxx xxxx xxxx DDDS SSSS 3333 33DD
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3 = it is the primary opcode
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D = Destions register
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S = Source reigters
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opcode
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-------------------------
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|bit order: 5432 10 67 |
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------- ------- ----------- ----
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34: | 0c 00 | | e1 93 | stw r31,12(r1) 0000 1100 0000 0000 1110 0001 | 1001 00 | 00
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38: | 14 00 | | 01 90 | stw r0,20(r1) 0001 0100 0000 0000 0000 0001 | 1001 00 | 11
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------- ------- ---------
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| |--> Get source register R0-R31 (0xE1 & 0x1F) = 1
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| |--> Get Dest register R0-R31 ((0xE1 & 0xE0)>>5) | ((0x90 & 0x3)<<3) = 31 or 0
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| | (The adding the two last bit on the end is maybe wrong need examine it)
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| --> Get the opcpde (0x90 & 0xFC)
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\ /
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The address offset 12 or 20
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opcode
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---------------------------------------------------------
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|bit order: pos 1111 1111 1111 1111 0000 0000 0000 0000 |
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| 5432 10 |
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|---------------------------------------------------------|
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| bits 0000 1100 0000 0000 1110 0001 1001 0000 |
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---------------------------------------------------------
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| math (opcode>>2) & 0x3F |
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---------------------------------------------------------
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Dest Register
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---------------------------------------------------------
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|bit order: pos 1111 1111 1111 1111 0000 0000 0000 0000 |
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| 210 43 |
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|---------------------------------------------------------|
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| bits 0000 1100 0000 0000 1110 0001 1001 0000 |
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---------------------------------------------------------
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| math (((opcode & 0x3) << 3) | ((opcode & 0xE000) >> 13))|
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---------------------------------------------------------
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source Register
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---------------------------------------------------------
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|bit order: pos 1111 1111 1111 1111 0000 0000 0000 0000 |
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| x xxxx |
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|---------------------------------------------------------|
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| bits 0000 1100 0000 0000 1110 0001 1001 0000 |
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---------------------------------------------------------
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| math |
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---------------------------------------------------------
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