mirror of
https://github.com/reactos/reactos.git
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599 lines
18 KiB
C
599 lines
18 KiB
C
/*
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* PROJECT: ReactOS ComPort Library for NEC PC-98 series
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* LICENSE: GPL-2.0-or-later (https://spdx.org/licenses/GPL-2.0-or-later)
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* PURPOSE: Provides a serial port library for KDCOM, INIT, and FREELDR
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* COPYRIGHT: Copyright 2020 Dmitry Borisov (di.sean@protonmail.com)
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*/
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/* Note: ns16550 code from cportlib.c */
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/* INCLUDES *******************************************************************/
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#include <intrin.h>
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#include <ioaccess.h>
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#include <ntstatus.h>
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#include <ntstatus.h>
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#include <cportlib/cportlib.h>
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#include <drivers/pc98/serial.h>
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#include <drivers/pc98/sysport.h>
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#include <drivers/pc98/pit.h>
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#include <drivers/pc98/cpu.h>
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#define NDEBUG
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#include <debug.h>
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/* GLOBALS ********************************************************************/
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#define TIMEOUT_COUNT 1024 * 200
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static struct
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{
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PUCHAR Address;
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BOOLEAN HasFifo;
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BOOLEAN FifoEnabled;
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UCHAR RingIndicator;
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} Rs232ComPort[] =
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{
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{ (PUCHAR)0x030, FALSE, FALSE, 0 },
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{ (PUCHAR)0x238, FALSE, FALSE, 0 }
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};
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static BOOLEAN IsNekoProject = FALSE;
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/* FUNCTIONS ******************************************************************/
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static BOOLEAN
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CpIsNekoProject(VOID)
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{
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UCHAR Input[4] = "NP2";
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UCHAR Output[4] = {0};
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UCHAR i;
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for (i = 0; i < 3; i++)
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WRITE_PORT_UCHAR((PUCHAR)0x7EF, Input[i]);
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for (i = 0; i < 3; i++)
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Output[i] = READ_PORT_UCHAR((PUCHAR)0x7EF);
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return (*(PULONG)Input == *(PULONG)Output);
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}
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static VOID
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CpWait(VOID)
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{
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UCHAR i;
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for (i = 0; i < 6; i++)
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WRITE_PORT_UCHAR((PUCHAR)CPU_IO_o_ARTIC_DELAY, 0);
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}
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VOID
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NTAPI
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CpEnableFifo(
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IN PUCHAR Address,
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IN BOOLEAN Enable)
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{
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/* Set FIFO and clear the receive/transmit buffers */
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if (Address == Rs232ComPort[0].Address && Rs232ComPort[0].HasFifo)
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{
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if (Enable)
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WRITE_PORT_UCHAR((PUCHAR)SER1_IO_o_FIFO_CONTROL,
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SER_FCR_ENABLE | SER_FCR_RCVR_RESET | SER_FCR_TXMT_RESET);
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else
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WRITE_PORT_UCHAR((PUCHAR)SER1_IO_o_FIFO_CONTROL, SER_FCR_DISABLE);
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Rs232ComPort[0].FifoEnabled = Enable;
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}
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else if (Address == Rs232ComPort[1].Address && Rs232ComPort[1].HasFifo)
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{
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if (Enable)
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WRITE_PORT_UCHAR((PUCHAR)SER2_IO_o_FIFO_CONTROL,
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SER_FCR_ENABLE | SER_FCR_RCVR_RESET | SER_FCR_TXMT_RESET);
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else
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WRITE_PORT_UCHAR((PUCHAR)SER2_IO_o_FIFO_CONTROL, SER_FCR_DISABLE);
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Rs232ComPort[1].FifoEnabled = Enable;
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}
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CpWait();
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}
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VOID
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NTAPI
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CpSetBaud(
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IN PCPPORT Port,
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IN ULONG BaudRate)
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{
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UCHAR Lcr;
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USHORT Count;
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TIMER_CONTROL_PORT_REGISTER TimerControl;
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if (Port->Address == Rs232ComPort[0].Address)
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{
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if (Rs232ComPort[0].HasFifo)
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WRITE_PORT_UCHAR((PUCHAR)SER1_IO_o_DIVISOR_LATCH, SER1_DLR_MODE_LEGACY);
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TimerControl.BcdMode = FALSE;
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TimerControl.OperatingMode = PitOperatingMode3;
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TimerControl.AccessMode = PitAccessModeLowHigh;
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TimerControl.Channel = PitChannel2;
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if (IsNekoProject)
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{
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/* The horrible text input lag happens by about 6 seconds on my PC */
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Count = 3;
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}
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else
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{
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Count = (READ_PORT_UCHAR((PUCHAR)0x42) & 0x20) ?
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(TIMER_FREQUENCY_1 / (BaudRate * 16)) : (TIMER_FREQUENCY_2 / (BaudRate * 16));
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}
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Write8253Timer(TimerControl, Count);
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/* Save baud rate in port */
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Port->BaudRate = BaudRate;
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}
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else if (Port->Address == Rs232ComPort[1].Address)
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{
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/* Set the DLAB on */
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Lcr = READ_PORT_UCHAR((PUCHAR)SER2_IO_i_LINE_CONTROL);
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WRITE_PORT_UCHAR((PUCHAR)SER2_IO_o_LINE_CONTROL, Lcr | SER2_LCR_DLAB);
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/* Set the baud rate */
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Count = SER2_CLOCK_RATE / BaudRate;
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WRITE_PORT_UCHAR((PUCHAR)SER2_IO_o_DIVISOR_LATCH_LSB, Count & 0xFF);
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WRITE_PORT_UCHAR((PUCHAR)SER2_IO_o_DIVISOR_LATCH_MSB, (Count >> 8) & 0xFF);
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/* Reset DLAB */
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WRITE_PORT_UCHAR((PUCHAR)SER2_IO_o_LINE_CONTROL, Lcr & ~SER2_LCR_DLAB);
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/* Save baud rate in port */
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Port->BaudRate = BaudRate;
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}
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}
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NTSTATUS
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NTAPI
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CpInitialize(
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IN PCPPORT Port,
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IN PUCHAR Address,
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IN ULONG BaudRate)
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{
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SYSTEM_CONTROL_PORT_C_REGISTER SystemControl;
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UCHAR FifoStatus;
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if (Port == NULL || Address == NULL || BaudRate == 0)
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return STATUS_INVALID_PARAMETER;
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if (!CpDoesPortExist(Address))
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return STATUS_NOT_FOUND;
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/* Initialize port data */
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Port->Address = Address;
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Port->BaudRate = 0;
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Port->Flags = 0;
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IsNekoProject = CpIsNekoProject();
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if (Port->Address == Rs232ComPort[0].Address)
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{
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/* FIFO test */
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FifoStatus = READ_PORT_UCHAR((PUCHAR)SER1_IO_i_INTERRUPT_ID) & SER1_IIR_FIFOS_ENABLED;
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CpWait();
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Rs232ComPort[0].HasFifo = ((READ_PORT_UCHAR((PUCHAR)SER1_IO_i_INTERRUPT_ID) & SER1_IIR_FIFOS_ENABLED) != FifoStatus);
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/* Disable the interrupts */
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SystemControl.Bits = READ_PORT_UCHAR((PUCHAR)PPI_IO_i_PORT_C);
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SystemControl.InterruptEnableRxReady = FALSE;
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SystemControl.InterruptEnableTxEmpty = FALSE;
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SystemControl.InterruptEnableTxReady = FALSE;
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WRITE_PORT_UCHAR((PUCHAR)PPI_IO_o_PORT_C, SystemControl.Bits);
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/* Turn off FIFO */
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if (Rs232ComPort[0].HasFifo)
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CpEnableFifo(Address, FALSE);
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/* Set the baud rate */
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CpSetBaud(Port, BaudRate);
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/* Software reset */
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WRITE_PORT_UCHAR((PUCHAR)SER1_IO_o_MODE_COMMAND, 0);
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CpWait();
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WRITE_PORT_UCHAR((PUCHAR)SER1_IO_o_MODE_COMMAND, 0);
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CpWait();
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WRITE_PORT_UCHAR((PUCHAR)SER1_IO_o_MODE_COMMAND, 0);
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CpWait();
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WRITE_PORT_UCHAR((PUCHAR)SER1_IO_o_MODE_COMMAND, SER1_COMMMAND_IR);
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CpWait();
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/* Mode instruction - asynchronous mode, 8 data bits, 1 stop bit, no parity, 16x clock divisor */
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WRITE_PORT_UCHAR((PUCHAR)SER1_IO_o_MODE_COMMAND,
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SER1_MODE_LENGTH_8 | SER1_MODE_1_STOP | SER1_MODE_CLOCKx16);
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CpWait();
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/* Command instruction - transmit enable, turn on DTR and RTS, receive enable, clear error flag */
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WRITE_PORT_UCHAR((PUCHAR)SER1_IO_o_MODE_COMMAND,
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SER1_COMMMAND_TxEN | SER1_COMMMAND_DTR |
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SER1_COMMMAND_RxEN | SER1_COMMMAND_ER | SER1_COMMMAND_RTS);
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CpWait();
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/* Disable the interrupts again */
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WRITE_PORT_UCHAR((PUCHAR)PPI_IO_o_PORT_C, SystemControl.Bits);
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/* Turn on FIFO */
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if (Rs232ComPort[0].HasFifo)
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CpEnableFifo(Address, TRUE);
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/* Read junk out of the data register */
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if (Rs232ComPort[0].HasFifo)
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(VOID)READ_PORT_UCHAR((PUCHAR)SER1_IO_i_RECEIVER_BUFFER);
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else
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(VOID)READ_PORT_UCHAR((PUCHAR)SER1_IO_i_DATA);
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return STATUS_SUCCESS;
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}
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else if (Port->Address == Rs232ComPort[1].Address)
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{
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/* Disable the interrupts */
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WRITE_PORT_UCHAR((PUCHAR)SER2_IO_o_LINE_CONTROL, 0);
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WRITE_PORT_UCHAR((PUCHAR)SER2_IO_o_INTERRUPT_EN, 0);
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/* Turn on DTR, RTS and OUT2 */
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WRITE_PORT_UCHAR((PUCHAR)SER2_IO_o_MODEM_CONTROL,
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SER2_MCR_DTR_STATE | SER2_MCR_RTS_STATE | SER2_MCR_OUT_2);
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/* Set the baud rate */
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CpSetBaud(Port, BaudRate);
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/* Set 8 data bits, 1 stop bit, no parity, no break */
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WRITE_PORT_UCHAR((PUCHAR)SER2_IO_o_LINE_CONTROL,
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SER2_LCR_LENGTH_8 | SER2_LCR_ST1 | SER2_LCR_NO_PARITY);
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/* FIFO test */
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Rs232ComPort[1].HasFifo = READ_PORT_UCHAR((PUCHAR)SER2_IO_i_INTERRUPT_ID) & SER2_IIR_HAS_FIFO;
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/* Turn on FIFO */
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if (Rs232ComPort[1].HasFifo)
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CpEnableFifo(Address, TRUE);
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/* Read junk out of the RBR */
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(VOID)READ_PORT_UCHAR((PUCHAR)SER2_IO_i_RECEIVER_BUFFER);
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return STATUS_SUCCESS;
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}
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return STATUS_NOT_FOUND;
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}
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static BOOLEAN
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ComPortTest1(IN PUCHAR Address)
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{
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/*
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* See "Building Hardware and Firmware to Complement Microsoft Windows Headless Operation"
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* Out-of-Band Management Port Device Requirements:
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* The device must act as a 16550 or 16450 UART.
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* Windows Server 2003 will test this device using the following process:
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* 1. Save off the current modem status register.
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* 2. Place the UART into diagnostic mode (The UART is placed into loopback mode
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* by writing SERIAL_MCR_LOOP to the modem control register).
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* 3. The modem status register is read and the high bits are checked. This means
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* SERIAL_MSR_CTS, SERIAL_MSR_DSR, SERIAL_MSR_RI and SERIAL_MSR_DCD should
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* all be clear.
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* 4. Place the UART in diagnostic mode and turn on OUTPUT (Loopback Mode and
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* OUTPUT are both turned on by writing (SERIAL_MCR_LOOP | SERIAL_MCR_OUT1)
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* to the modem control register).
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* 5. The modem status register is read and the ring indicator is checked.
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* This means SERIAL_MSR_RI should be set.
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* 6. Restore original modem status register.
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*
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* REMARK: Strangely enough, the Virtual PC 2007 virtual machine
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* doesn't pass this test.
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*/
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BOOLEAN RetVal = FALSE;
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UCHAR Mcr, Msr;
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/* Save the Modem Control Register */
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Mcr = READ_PORT_UCHAR((PUCHAR)SER2_IO_i_MODEM_CONTROL);
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/* Enable loop (diagnostic) mode (set Bit 4 of the MCR) */
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WRITE_PORT_UCHAR((PUCHAR)SER2_IO_o_MODEM_CONTROL, SER2_MCR_LOOPBACK);
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/* Clear all modem output bits */
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WRITE_PORT_UCHAR((PUCHAR)SER2_IO_o_MODEM_CONTROL, SER2_MCR_LOOPBACK);
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/* Read the Modem Status Register */
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Msr = READ_PORT_UCHAR((PUCHAR)SER2_IO_i_MODEM_STATUS);
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/*
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* The upper nibble of the MSR (modem output bits) must be
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* equal to the lower nibble of the MCR (modem input bits).
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*/
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if ((Msr & (SER_MSR_CTS | SER_MSR_DSR | SER_MSR_RI | SER_MSR_DCD)) == 0x00)
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{
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/* Set all modem output bits */
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WRITE_PORT_UCHAR((PUCHAR)SER2_IO_o_MODEM_CONTROL,
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SER2_MCR_OUT_1 | SER2_MCR_LOOPBACK); // Windows
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/* ReactOS
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WRITE_PORT_UCHAR((PUCHAR)SER2_IO_o_MODEM_CONTROL,
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SER2_MCR_DTR_STATE | SER2_MCR_RTS_STATE |
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SER2_MCR_OUT_1 | SER2_MCR_OUT_2 | SER2_MCR_LOOPBACK);
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*/
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/* Read the Modem Status Register */
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Msr = READ_PORT_UCHAR((PUCHAR)SER2_IO_i_MODEM_STATUS);
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/*
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* The upper nibble of the MSR (modem output bits) must be
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* equal to the lower nibble of the MCR (modem input bits).
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*/
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if (Msr & SER_MSR_RI) // Windows
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// if (Msr & (SER_MSR_CTS | SER_MSR_DSR | SER_MSR_RI | SER_MSR_DCD) == 0xF0) // ReactOS
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{
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RetVal = TRUE;
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}
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}
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/* Restore the MCR */
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WRITE_PORT_UCHAR((PUCHAR)SER2_IO_o_MODEM_CONTROL, Mcr);
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return RetVal;
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}
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static BOOLEAN
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ComPortTest2(IN PUCHAR Address)
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{
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/*
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* This test checks whether the 16450/16550 scratch register is available.
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* If not, the serial port is considered as unexisting.
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*/
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UCHAR Byte = 0;
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do
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{
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WRITE_PORT_UCHAR((PUCHAR)SER2_IO_o_SCRATCH, Byte);
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if (READ_PORT_UCHAR((PUCHAR)SER2_IO_i_SCRATCH) != Byte)
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return FALSE;
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}
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while (++Byte != 0);
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return TRUE;
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}
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BOOLEAN
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NTAPI
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CpDoesPortExist(IN PUCHAR Address)
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{
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UCHAR Data, Status;
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if (Address == Rs232ComPort[0].Address || Address == (PUCHAR)0x41)
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{
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Data = READ_PORT_UCHAR(Address);
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Status = READ_PORT_UCHAR(Address + 2);
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if ((Data & Status) == 0xFF || (Data | Status) == 0x00)
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return FALSE;
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else
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return TRUE;
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}
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else if (Address == Rs232ComPort[1].Address)
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{
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return (ComPortTest1(Address) || ComPortTest2(Address));
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}
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return FALSE;
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}
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UCHAR
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NTAPI
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CpReadLsr(
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IN PCPPORT Port,
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IN UCHAR ExpectedValue)
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{
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UCHAR Lsr, Msr;
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SYSTEM_CONTROL_PORT_B_REGISTER SystemControl;
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if (Port->Address == Rs232ComPort[0].Address)
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{
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/* Read the LSR and check if the expected value is present */
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if (Rs232ComPort[0].HasFifo)
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{
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Lsr = READ_PORT_UCHAR((PUCHAR)SER1_IO_i_LINE_STATUS);
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if (!(Lsr & ExpectedValue))
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{
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Msr = READ_PORT_UCHAR((PUCHAR)SER1_IO_i_MODEM_STATUS);
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/* If the ring indicator reaches 3, we've seen this on/off twice */
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Rs232ComPort[0].RingIndicator |= (Msr & SER_MSR_RI) ? 1 : 2;
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if (Rs232ComPort[0].RingIndicator == 3)
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Port->Flags |= CPPORT_FLAG_MODEM_CONTROL;
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}
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}
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else
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{
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Lsr = READ_PORT_UCHAR((PUCHAR)SER1_IO_i_STATUS);
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if (!(Lsr & ExpectedValue))
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{
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SystemControl.Bits = READ_PORT_UCHAR((PUCHAR)PPI_IO_i_PORT_B);
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/* If the ring indicator reaches 3, we've seen this on/off twice */
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Rs232ComPort[0].RingIndicator |= SystemControl.RingIndicator ? 1 : 2;
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if (Rs232ComPort[0].RingIndicator == 3)
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Port->Flags |= CPPORT_FLAG_MODEM_CONTROL;
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}
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}
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return Lsr;
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}
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else if (Port->Address == Rs232ComPort[1].Address)
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{
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/* Read the LSR and check if the expected value is present */
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Lsr = READ_PORT_UCHAR((PUCHAR)SER2_IO_i_LINE_STATUS);
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if (!(Lsr & ExpectedValue))
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{
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Msr = READ_PORT_UCHAR((PUCHAR)SER2_IO_i_MODEM_STATUS);
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/* If the indicator reaches 3, we've seen this on/off twice */
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Rs232ComPort[1].RingIndicator |= (Msr & SER_MSR_RI) ? 1 : 2;
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if (Rs232ComPort[1].RingIndicator == 3)
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Port->Flags |= CPPORT_FLAG_MODEM_CONTROL;
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}
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return Lsr;
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}
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return 0;
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}
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USHORT
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NTAPI
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CpGetByte(
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IN PCPPORT Port,
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OUT PUCHAR Byte,
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IN BOOLEAN Wait,
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IN BOOLEAN Poll)
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{
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UCHAR Lsr;
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ULONG LimitCount = Wait ? TIMEOUT_COUNT : 1;
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UCHAR SuccessFlags, ErrorFlags;
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BOOLEAN FifoEnabled;
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/* Handle early read-before-init */
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if (!Port->Address)
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return CP_GET_NODATA;
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if (Port->Address == Rs232ComPort[0].Address)
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{
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SuccessFlags = Rs232ComPort[0].HasFifo ? SER1_LSR_RxRDY : SER1_STATUS_RxRDY;
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ErrorFlags = Rs232ComPort[0].HasFifo ? (SER1_LSR_PE | SER1_LSR_OE) :
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(SER1_STATUS_FE | SER1_STATUS_PE | SER1_STATUS_OE);
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/* If "wait" mode enabled, spin many times, otherwise attempt just once */
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while (LimitCount--)
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{
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/* Read LSR for data ready */
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Lsr = CpReadLsr(Port, SuccessFlags);
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if (Lsr & SuccessFlags)
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{
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/* If an error happened, clear the byte and fail */
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if (Lsr & ErrorFlags)
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{
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/* Save the last FIFO state */
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FifoEnabled = Rs232ComPort[0].FifoEnabled;
|
|
|
|
/* Turn off FIFO */
|
|
if (FifoEnabled)
|
|
CpEnableFifo(Port->Address, FALSE);
|
|
|
|
/* Clear error flag */
|
|
WRITE_PORT_UCHAR((PUCHAR)SER1_IO_o_MODE_COMMAND,
|
|
SER1_COMMMAND_TxEN | SER1_COMMMAND_DTR |
|
|
SER1_COMMMAND_RxEN | SER1_COMMMAND_ER | SER1_COMMMAND_RTS);
|
|
|
|
/* Turn on FIFO */
|
|
if (FifoEnabled)
|
|
CpEnableFifo(Port->Address, TRUE);
|
|
|
|
*Byte = 0;
|
|
return CP_GET_ERROR;
|
|
}
|
|
|
|
/* If only polling was requested by caller, return now */
|
|
if (Poll)
|
|
return CP_GET_SUCCESS;
|
|
|
|
/* Otherwise read the byte and return it */
|
|
if (Rs232ComPort[0].HasFifo)
|
|
*Byte = READ_PORT_UCHAR((PUCHAR)SER1_IO_i_RECEIVER_BUFFER);
|
|
else
|
|
*Byte = READ_PORT_UCHAR((PUCHAR)SER1_IO_i_DATA);
|
|
|
|
/* TODO: Handle CD if port is in modem control mode */
|
|
|
|
/* Byte was read */
|
|
return CP_GET_SUCCESS;
|
|
}
|
|
else if (IsNekoProject && Rs232ComPort[0].HasFifo)
|
|
{
|
|
/*
|
|
* Neko Project 21/W doesn't set RxRDY without reading any data from 0x136.
|
|
* TODO: Check real hardware behavior.
|
|
*/
|
|
(VOID)READ_PORT_UCHAR((PUCHAR)SER1_IO_i_INTERRUPT_ID);
|
|
}
|
|
}
|
|
|
|
/* Reset LSR, no data was found */
|
|
CpReadLsr(Port, 0);
|
|
}
|
|
else if (Port->Address == Rs232ComPort[1].Address)
|
|
{
|
|
/* If "wait" mode enabled, spin many times, otherwise attempt just once */
|
|
while (LimitCount--)
|
|
{
|
|
/* Read LSR for data ready */
|
|
Lsr = CpReadLsr(Port, SER2_LSR_DR);
|
|
if ((Lsr & SER2_LSR_DR) == SER2_LSR_DR)
|
|
{
|
|
/* If an error happened, clear the byte and fail */
|
|
if (Lsr & (SER2_LSR_FE | SER2_LSR_PE | SER2_LSR_OE))
|
|
{
|
|
*Byte = 0;
|
|
return CP_GET_ERROR;
|
|
}
|
|
|
|
/* If only polling was requested by caller, return now */
|
|
if (Poll)
|
|
return CP_GET_SUCCESS;
|
|
|
|
/* Otherwise read the byte and return it */
|
|
*Byte = READ_PORT_UCHAR((UCHAR)SER2_IO_i_RECEIVER_BUFFER);
|
|
|
|
/* TODO: Handle CD if port is in modem control mode */
|
|
|
|
/* Byte was read */
|
|
return CP_GET_SUCCESS;
|
|
}
|
|
}
|
|
|
|
/* Reset LSR, no data was found */
|
|
CpReadLsr(Port, 0);
|
|
}
|
|
|
|
return CP_GET_NODATA;
|
|
}
|
|
|
|
VOID
|
|
NTAPI
|
|
CpPutByte(
|
|
IN PCPPORT Port,
|
|
IN UCHAR Byte)
|
|
{
|
|
if (Port->Address == Rs232ComPort[0].Address)
|
|
{
|
|
/* TODO: Check if port is in modem control to handle CD */
|
|
|
|
if (Rs232ComPort[0].HasFifo)
|
|
{
|
|
while ((CpReadLsr(Port, SER1_LSR_TxRDY) & SER1_LSR_TxRDY) == 0)
|
|
NOTHING;
|
|
|
|
WRITE_PORT_UCHAR((PUCHAR)SER1_IO_o_TRANSMITTER_BUFFER, Byte);
|
|
}
|
|
else
|
|
{
|
|
while ((CpReadLsr(Port, SER1_STATUS_TxRDY) & SER1_STATUS_TxRDY) == 0)
|
|
NOTHING;
|
|
|
|
WRITE_PORT_UCHAR((PUCHAR)SER1_IO_o_DATA, Byte);
|
|
}
|
|
}
|
|
else if (Port->Address == Rs232ComPort[1].Address)
|
|
{
|
|
/* TODO: Check if port is in modem control to handle CD */
|
|
|
|
while ((CpReadLsr(Port, SER2_LSR_THR_EMPTY) & SER2_LSR_THR_EMPTY) == 0)
|
|
NOTHING;
|
|
|
|
WRITE_PORT_UCHAR((PUCHAR)SER2_IO_o_TRANSMITTER_BUFFER, Byte);
|
|
}
|
|
}
|