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173 lines
8.2 KiB
C
173 lines
8.2 KiB
C
/*
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* COPYRIGHT: See COPYING in the top level directory
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* PROJECT: ReactOS Novell Eagle 2000 driver
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* FILE: include/8390.h
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* PURPOSE: National Semiconductor 8390 NIC definitions
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*/
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#pragma once
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/* Page 0 register layout (PS1 = 0, PS0 = 0) */
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#define PG0_CR 0x00 /* Command Register (R/W) */
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#define PG0_CLDA0 0x01 /* Current Local DMA Address 0 (R) */
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#define PG0_PSTART 0x01 /* Page Start Register (W) */
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#define PG0_CLDA1 0x02 /* Current Local DMA Address 1 (R) */
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#define PG0_PSTOP 0x02 /* Page Stop Register (W) */
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#define PG0_BNRY 0x03 /* Boundary Pointer (R/W) */
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#define PG0_TSR 0x04 /* Transmit Status Register (R) */
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#define PG0_TPSR 0x04 /* Transmit Page Start Register (W) */
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#define PG0_NCR 0x05 /* Number of Collisions Register (R) */
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#define PG0_TBCR0 0x05 /* Transmit Byte Count Register 0 (W) */
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#define PG0_FIFO 0x06 /* FIFO (R) */
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#define PG0_TBCR1 0x06 /* Transmit Byte Count Register 1 (W) */
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#define PG0_ISR 0x07 /* Interrupt Status Register (R/W) */
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#define PG0_CRDA0 0x08 /* Current Remote DMA Address 0 (R) */
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#define PG0_RSAR0 0x08 /* Remote Start Address Register 0 (W) */
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#define PG0_CRDA1 0x09 /* Current Remote DMA Address 1 (R) */
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#define PG0_RSAR1 0x09 /* Remote Start Address Register 1 (W) */
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#define PG0_RBCR0 0x0A /* Remote Byte Count Register 0 (W) */
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#define PG0_RBCR1 0x0B /* Remote Byte Count Register 1 (W) */
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#define PG0_RSR 0x0C /* Receive Status Register (R) */
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#define PG0_RCR 0x0C /* Receive Configuration Register (W) */
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#define PG0_CNTR0 0x0D /* Tally Counter 0 (Frame Alignment Errors) (R) */
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#define PG0_TCR 0x0D /* Transmit Configuration Register (W) */
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#define PG0_CNTR1 0x0E /* Tally Counter 1 (CRC Errors) (R) */
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#define PG0_DCR 0x0E /* Data Configuration Register (W) */
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#define PG0_CNTR2 0x0F /* Tally Counter 2 (Missed Packet Errors) (R) */
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#define PG0_IMR 0x0F /* Interrupt Mask Register (W) */
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/* Page 1 register layout (PS1 = 0, PS0 = 1) */
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#define PG1_CR 0x00 /* Command Register (R/W) */
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#define PG1_PAR 0x01 /* Physical Address Registers (6 registers) (R/W) */
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#define PG1_CURR 0x07 /* Current Page Register (R/W) */
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#define PG1_MAR 0x08 /* Multicast Address Registers (8 registers) (R/W) */
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/* Page 2 register layout (PS1 = 1, PS0 = 0) */
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#define PG2_CR 0x00 /* Command Register (R/W) */
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#define PG2_PSTART 0x01 /* Page Start Register (R) */
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#define PG2_CLDA0 0x01 /* Current Local DMA Address 0 (W) */
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#define PG2_PSTOP 0x02 /* Page Stop Register (R) */
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#define PG2_CLDA1 0x02 /* Current Local DMA Address 1 (W) */
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#define PG2_RNPP 0x03 /* Remote Next Packet Pointer (R/W) */
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#define PG2_TPSR 0x04 /* Transmit Page Start Address (R) */
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#define PG2_LNPP 0x05 /* Local Next Packet Pointer (R/W) */
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#define PG2_AC1 0x06 /* Address Counter (Upper) (R/W) */
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#define PG2_AC0 0x07 /* Address Counter (Lower) (R/W) */
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#define PG2_RCR 0x0C /* Receive Configuration Register (R) */
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#define PG2_TCR 0x0D /* Transmit Configuration Register (R) */
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#define PG2_DCR 0x0E /* Data Configuration Register (R) */
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#define PG2_IMR 0x0F /* Interrupt Mask Register (R) */
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/* Bits in PGX_CR - Command Register */
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#define CR_STP 0x01 /* Stop chip */
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#define CR_STA 0x02 /* Start chip */
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#define CR_TXP 0x04 /* Transmit a frame */
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#define CR_RD0 0x08 /* Remote read */
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#define CR_RD1 0x10 /* Remote write */
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#define CR_RD2 0x20 /* Abort/complete remote DMA */
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#define CR_PAGE0 0x00 /* Select page 0 of chip registers */
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#define CR_PAGE1 0x40 /* Select page 1 of chip registers */
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#define CR_PAGE2 0x80 /* Select page 2 of chip registers */
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/* Bits in PG0_ISR - Interrupt Status Register */
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#define ISR_PRX 0x01 /* Packet received, no errors */
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#define ISR_PTX 0x02 /* Packet transmitted, no errors */
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#define ISR_RXE 0x04 /* Receive error */
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#define ISR_TXE 0x08 /* Transmit error */
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#define ISR_OVW 0x10 /* Overwrite warning */
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#define ISR_CNT 0x20 /* Counter overflow */
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#define ISR_RDC 0x40 /* Remote DMA complete */
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#define ISR_RST 0x80 /* Reset status */
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/* Bits in PG0_TSR - Transmit Status Register */
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#define TSR_PTX 0x01h /* Packet transmitted without error */
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#define TSR_COL 0x04h /* Collided at least once */
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#define TSR_ABT 0x08h /* Collided 16 times and was dropped */
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#define TSR_CRS 0x10h /* Carrier sense lost */
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#define TSR_FU 0x20h /* Transmit FIFO Underrun */
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#define TSR_CDH 0x40h /* Collision detect heartbeat */
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#define TSR_OWC 0x80h /* Out of window collision */
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/* Bits for PG0_RCR - Receive Configuration Register */
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#define RCR_SEP 0x01 /* Save error packets */
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#define RCR_AR 0x02 /* Accept runt packets */
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#define RCR_AB 0x04 /* Accept broadcasts */
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#define RCR_AM 0x08 /* Accept multicast */
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#define RCR_PRO 0x10 /* Promiscuous physical addresses */
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#define RCR_MON 0x20 /* Monitor mode */
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/* Bits in PG0_RSR - Receive Status Register */
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#define RSR_PRX 0x01 /* Received packet intact */
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#define RSR_CRC 0x02 /* CRC error */
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#define RSR_FAE 0x04 /* Frame alignment error */
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#define RSR_FO 0x08 /* FIFO overrun */
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#define RSR_MPA 0x10 /* Missed packet */
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#define RSR_PHY 0x20 /* Physical/multicast address */
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#define RSR_DIS 0x40 /* Receiver disabled (monitor mode) */
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#define RSR_DFR 0x80 /* Deferring */
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/* Bits in PG0_TCR - Transmit Configuration Register */
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#define TCR_CRC 0x01 /* Inhibit CRC, do not append CRC */
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#define TCR_LOOP 0x02 /* Set loopback mode */
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#define TCR_LB01 0x06 /* Encoded loopback control */
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#define TCR_ATD 0x08 /* Auto transmit disable */
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#define TCR_OFST 0x10 /* Collision offset enable */
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/* Bits in PG0_DCR - Data Configuration Register */
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#define DCR_WTS 0x01 /* Word transfer mode selection */
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#define DCR_BOS 0x02 /* Byte order selection */
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#define DCR_LAS 0x04 /* Long address selection */
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#define DCR_LS 0x08 /* Loopback select (when 0) */
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#define DCR_ARM 0x10 /* Autoinitialize remote */
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#define DCR_FT00 0x00 /* Burst length selection (1 word/2 bytes) */
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#define DCR_FT01 0x20 /* burst length selection (2 words/4 bytes) */
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#define DCR_FT10 0x40 /* Burst length selection (4 words/8 bytes) */
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#define DCR_FT11 0x60 /* Burst length selection (6 words/12 bytes) */
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/* Bits in PG0_IMR - Interrupt Mask Register */
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#define IMR_PRXE 0x01 /* Packet received interrupt enable */
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#define IMR_PTXE 0x02 /* Packet transmitted interrupt enable */
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#define IMR_RXEE 0x04 /* Receive error interrupt enable */
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#define IMR_TXEE 0x08 /* Transmit error interrupt enable */
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#define IMR_OVWE 0x10 /* Overwrite warning interrupt enable */
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#define IMR_CNTE 0x20 /* Counter overflow interrupt enable */
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#define IMR_RDCE 0x40 /* Remote DMA complete interrupt enable */
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#define IMR_ALLE 0x7F /* All interrupts enable */
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/* NIC prepended structure to a received packet */
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typedef struct _PACKET_HEADER {
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UCHAR Status; /* See RSR_* constants */
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UCHAR NextPacket; /* Pointer to next packet in chain */
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USHORT PacketLength; /* Length of packet including this header */
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} PACKET_HEADER, *PPACKET_HEADER;
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#define IEEE_802_ADDR_LENGTH 6
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/* Ethernet frame header */
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typedef struct _ETH_HEADER {
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UCHAR Destination[IEEE_802_ADDR_LENGTH];
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UCHAR Source[IEEE_802_ADDR_LENGTH];
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USHORT PayloadType;
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} ETH_HEADER, *PETH_HEADER;
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typedef struct _DISCARD_HEADER {
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PACKET_HEADER HWHeader;
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ETH_HEADER EthernetHeader;
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} DISCARD_HEADER, *PDISCARD_HEADER;
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#define NICDisableInterrupts(Adapter) { \
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NDIS_DbgPrint(MAX_TRACE, ("NICDisableInterrupts()\n")); \
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NdisRawWritePortUchar((Adapter)->IOBase + PG0_IMR, 0x00); \
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}
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#define NICEnableInterrupts(Adapter) { \
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NDIS_DbgPrint(MAX_TRACE, ("NICEnableInterrupts() Mask (0x%X)\n", (Adapter)->InterruptMask)); \
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NdisRawWritePortUchar((Adapter)->IOBase + PG0_IMR, (Adapter)->InterruptMask); \
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}
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VOID NTAPI MiniportHandleInterrupt(
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IN NDIS_HANDLE MiniportAdapterContext);
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/* EOF */
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