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491 lines
12 KiB
C
491 lines
12 KiB
C
/*
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* PROJECT: ReactOS VGA Miniport Driver
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* LICENSE: Microsoft NT4 DDK Sample Code License
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* FILE: win32ss/drivers/miniport/vga_new/vgadata.c
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* PURPOSE: Handles switching to VGA Modes and holds VGA Built-in Modes
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* PROGRAMMERS: Copyright (c) 1992 Microsoft Corporation
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* ReactOS Portable Systems Group
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*/
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#include "vga.h"
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//
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// This structure describes to which ports access is required.
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//
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VIDEO_ACCESS_RANGE VgaAccessRange[] = {
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{
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{{VGA_BASE_IO_PORT, 0x00000000}}, // 64-bit linear base address
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// of range
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VGA_START_BREAK_PORT - VGA_BASE_IO_PORT + 1, // # of ports
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1, // range is in I/O space
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1, // range should be visible
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0 // range should be shareable
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},
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{
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{{VGA_END_BREAK_PORT, 0x00000000}},
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VGA_MAX_IO_PORT - VGA_END_BREAK_PORT + 1,
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1,
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1,
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0
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},
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//
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// This next region also includes Memory mapped IO. In MMIO, the ports are
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// repeated every 256 bytes from b8000 to bff00.
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//
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{
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{{MEM_VGA, 0x00000000}},
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MEM_VGA_SIZE,
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0,
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1,
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0
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},
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// eVb: 4.1 [VGA] - Add ATI/Mach64 VGA registers
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//
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// ATI Registers
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//
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{
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{{0x1CE, 0x00000000}},
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2,
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1,
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1,
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0
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},
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{
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{{0x2E8, 0x00000000}},
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8,
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1,
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1,
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0
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}
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// eVb: 4.1 [END]
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};
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//
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// 640x480 256-color 60Hz mode (BIOS mode 12) set command string for
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// VGA.
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//
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// eVb: 4.2 [VGA] - Add VGA command streams instead of Cirrus
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USHORT VGA_640x480[] = {
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OWM, // begin setmode
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SEQ_ADDRESS_PORT,
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5, // count
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0x100, // start sync reset
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0x0101,0x0F02,0x0003,0x0604, // program up sequencer
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OB, // misc. register
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MISC_OUTPUT_REG_WRITE_PORT,
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0xE3,
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OW, // text/graphics bit
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GRAPH_ADDRESS_PORT,
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0x506,
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OW, // end sync reset
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SEQ_ADDRESS_PORT,
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IND_SYNC_RESET,
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OB,
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SEQ_DATA_PORT,
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END_SYNC_RESET_VALUE,
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OW, // unprotect crtc 0-7
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CRTC_ADDRESS_PORT_COLOR,
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0x511,
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METAOUT+INDXOUT, // program crtc registers
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CRTC_ADDRESS_PORT_COLOR,
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VGA_NUM_CRTC_PORTS,0, // count, startindex
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0x5F,0x4F,0x50,0x82,0x54,0x80,0x0B,0x3E,0x00,0x40,0x0,0x0,0x0,0x0,0x0,0x0,
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0xEA,0x8C,0xDF,0x28,0x0,0xE7,0x4,0xE3,0xFF,
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IB, // prepare atc for writing
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INPUT_STATUS_1_COLOR,
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METAOUT+ATCOUT, // program atc registers
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ATT_ADDRESS_PORT,
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VGA_NUM_ATTRIB_CONT_PORTS,0, // count, startindex
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0x00, 0x01, 0x02, 0x03, 0x04, 0x05,
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0x17, 0x38, 0x39, 0x3A, 0x3B, 0x3C,
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0x3D, 0x3E, 0x3F, 0x3F, 0x01, 0x00,
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0x0F, 0x00, 0x00,
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METAOUT+INDXOUT, // program gdc registers
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GRAPH_ADDRESS_PORT,
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VGA_NUM_GRAPH_CONT_PORTS,0, // count, startindex
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0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
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0x05, 0x0F, 0xFF,
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OB,
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DAC_PIXEL_MASK_PORT,
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0xFF,
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IB, // prepare atc for writing
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INPUT_STATUS_1_COLOR,
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OB, // turn video on.
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ATT_ADDRESS_PORT,
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VIDEO_ENABLE,
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EOD
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};
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//
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// 720x400 color text mode (BIOS mode 3) set command string for
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// VGA.
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//
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USHORT VGA_TEXT_0[] = {
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OWM, // begin setmode
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SEQ_ADDRESS_PORT,
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5, // count
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0x100, // start sync reset
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0x0101,0x0302,0x0003,0x0204, // program up sequencer
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OB, // misc. register
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MISC_OUTPUT_REG_WRITE_PORT,
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0x67,
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OW, // text/graphics bit
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GRAPH_ADDRESS_PORT,
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0x0e06,
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OW, // end sync reset
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SEQ_ADDRESS_PORT,
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IND_SYNC_RESET,
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OB,
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SEQ_DATA_PORT,
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END_SYNC_RESET_VALUE,
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OW, // unprotect crtc 0-7
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CRTC_ADDRESS_PORT_COLOR,
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0xE11,
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METAOUT+INDXOUT, // program crtc registers
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CRTC_ADDRESS_PORT_COLOR,
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VGA_NUM_CRTC_PORTS,0, // count, startindex
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0x5F,0x4F,0x50,0x82,0x55,0x81,0xBF,0x1F,0x00,0x4F,0xD,0xE,0x0,0x0,0x0,0x0,
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0x9c,0x8E,0x8F,0x28,0x1F,0x96,0xB9,0xA3,0xFF,
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IB, // prepare atc for writing
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INPUT_STATUS_1_COLOR,
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METAOUT+ATCOUT, // program atc registers
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ATT_ADDRESS_PORT,
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VGA_NUM_ATTRIB_CONT_PORTS,0, // count, startindex
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0x00, 0x01, 0x02, 0x03, 0x04, 0x05,
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0x17, 0x38, 0x39, 0x3A, 0x3B, 0x3C,
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0x3D, 0x3E, 0x3F, 0x3F, 0x04, 0x00,
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0x0F, 0x08, 0x00,
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METAOUT+INDXOUT, // program gdc registers
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GRAPH_ADDRESS_PORT,
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VGA_NUM_GRAPH_CONT_PORTS,0, // count, startindex
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0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
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0x0E, 0x00, 0xFF,
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OB,
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DAC_PIXEL_MASK_PORT,
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0xFF,
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IB, // prepare atc for writing
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INPUT_STATUS_1_COLOR,
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OB, // turn video on.
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ATT_ADDRESS_PORT,
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VIDEO_ENABLE,
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EOD
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};
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//
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// 640x400 color text mode (BIOS mode 3) set command string for
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// VGA.
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//
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USHORT VGA_TEXT_1[] = {
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OWM, // begin setmode
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SEQ_ADDRESS_PORT,
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5, // count
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0x100, // start sync reset
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0x0101,0x0302,0x0003,0x0204, // program up sequencer
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OB, // misc. register
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MISC_OUTPUT_REG_WRITE_PORT,
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0xA3,
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OW, // text/graphics bit
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GRAPH_ADDRESS_PORT,
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0x0e06,
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OW, // end sync reset
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SEQ_ADDRESS_PORT,
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IND_SYNC_RESET,
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OB,
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SEQ_DATA_PORT,
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END_SYNC_RESET_VALUE,
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OW, // unprotect crtc 0-7
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CRTC_ADDRESS_PORT_COLOR,
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0x511,
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METAOUT+INDXOUT, // program crtc registers
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CRTC_ADDRESS_PORT_COLOR,
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VGA_NUM_CRTC_PORTS,0, // count, startindex
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0x5F,0x4F,0x50,0x82,0x55,0x81,0xBF,0x1F,0x00,0x4D,0xB,0xC,0x0,0x0,0x0,0x0,
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0x83,0x85,0x5D,0x28,0x1F,0x63,0xBA,0xA3,0xFF,
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IB, // prepare atc for writing
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INPUT_STATUS_1_COLOR,
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METAOUT+ATCOUT, // program atc registers
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ATT_ADDRESS_PORT,
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VGA_NUM_ATTRIB_CONT_PORTS,0, // count, startindex
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0x00, 0x01, 0x02, 0x03, 0x04, 0x05,
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0x17, 0x38, 0x39, 0x3A, 0x3B, 0x3C,
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0x3D, 0x3E, 0x3F, 0x3F, 0x04, 0x00,
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0x0F, 0x00, 0x00,
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METAOUT+INDXOUT, // program gdc registers
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GRAPH_ADDRESS_PORT,
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VGA_NUM_GRAPH_CONT_PORTS,0, // count, startindex
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0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
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0x0E, 0x00, 0xFF,
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OB,
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DAC_PIXEL_MASK_PORT,
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0xFF,
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IB, // prepare atc for writing
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INPUT_STATUS_1_COLOR,
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OB, // turn video on.
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ATT_ADDRESS_PORT,
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VIDEO_ENABLE,
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EOD
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};
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// eVb: 4.2 [END]
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//
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// Video mode table - contains information and commands for initializing each
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// mode. These entries must correspond with those in VIDEO_MODE_VGA. The first
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// entry is commented; the rest follow the same format, but are not so
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// heavily commented.
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//
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// eVb: 4.3 [VGA] - Add VGA, ModeX and SVGA mode instead of Cirrus Modes
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VIDEOMODE ModesVGA[] =
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{
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// Color text mode 3, 720x400, 9x16 char cell (VGA).
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//
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{
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VIDEO_MODE_BANKED | VIDEO_MODE_COLOR, // flags that this mode is a color mode, but not graphics
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4, // four planes
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1, // one bit of colour per plane
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80, 25, // 80x25 text resolution
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720, 400, // 720x400 pixels on screen
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1, // only support one frequency, non-interlaced
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160, 0x10000, // 160 bytes per scan line, 64K of CPU-addressable bitmap
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FALSE,
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0x3, VGA_TEXT_0, // Mode 3, I/O initialization stream
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0xA0000, // Physical address at 0xA0000
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0x18000, 0x8000,
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0x20000, // 2 banks of 64K, 128KB total memory
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720, // 720 pixels per scan line
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FALSE,
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0
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},
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//
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// Color text mode 3, 640x350, 8x14 char cell (EGA).
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//
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{
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VIDEO_MODE_BANKED | VIDEO_MODE_COLOR,
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4, 1,
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80, 25,
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640, 350,
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1,
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160, 0x10000,
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FALSE,
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0x3, VGA_TEXT_1,
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0xA0000,
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0x18000, 0x8000,
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0x20000,
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640,
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FALSE,
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0
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},
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//
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//
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// Standard VGA Color graphics mode 0x12, 640x480 16 colors.
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//
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{
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VIDEO_MODE_BANKED | VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS,
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4, 1,
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80, 30,
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640, 480,
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1,
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80, 0x10000,
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FALSE,
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0x12, VGA_640x480,
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0xA0000,
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0, 0x20000,
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0x20000,
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640,
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FALSE,
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0
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},
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{
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VIDEO_MODE_BANKED | VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS,
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8, 1,
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0, 0,
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320, 200,
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70,
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80, 0x10000,
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FALSE,
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0x3, NULL,
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0xA0000,
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0, 0x20000,
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0x20000,
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320,
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FALSE,
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0
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},
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{
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VIDEO_MODE_BANKED | VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS,
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8, 1,
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0, 0,
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320, 240,
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60,
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80, 0x10000,
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FALSE,
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0x3, NULL,
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0xA0000,
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0, 0x20000,
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0x20000,
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320,
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FALSE,
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0
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},
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{
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VIDEO_MODE_BANKED | VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS,
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8, 1,
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0, 0,
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320, 400,
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70,
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80, 0x10000,
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FALSE,
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0x3, NULL,
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0xA0000,
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0, 0x20000,
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0x20000,
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320,
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FALSE,
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0
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},
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{
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VIDEO_MODE_BANKED | VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS,
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8, 1,
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0, 0,
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320, 480,
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60,
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80, 0x10000,
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FALSE,
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0x3, NULL,
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0xA0000,
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0, 0x20000,
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0x20000,
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320,
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FALSE,
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0
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},
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//
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// 800x600 16 colors.
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//
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{
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VIDEO_MODE_BANKED | VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS,
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4, 1,
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100, 37,
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800, 600,
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1,
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100, 0x10000,
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FALSE,
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(0x102 << 16) | VBE_SET_VBE_MODE, NULL,
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0xA0000,
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0, 0x20000,
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0x20000,
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800,
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FALSE,
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0
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},
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};
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ULONG NumVideoModes = sizeof(ModesVGA) / sizeof(VIDEOMODE);
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PVIDEOMODE VgaModeList;
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// eVb: 4.3 [END]
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//
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//
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// Data used to set the Graphics and Sequence Controllers to put the
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// VGA into a planar state at A0000 for 64K, with plane 2 enabled for
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// reads and writes, so that a font can be loaded, and to disable that mode.
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//
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// Settings to enable planar mode with plane 2 enabled.
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//
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USHORT EnableA000Data[] = {
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OWM,
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SEQ_ADDRESS_PORT,
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1,
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0x0100,
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OWM,
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GRAPH_ADDRESS_PORT,
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3,
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0x0204, // Read Map = plane 2
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0x0005, // Graphics Mode = read mode 0, write mode 0
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0x0406, // Graphics Miscellaneous register = A0000 for 64K, not odd/even,
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// graphics mode
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OWM,
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SEQ_ADDRESS_PORT,
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3,
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0x0402, // Map Mask = write to plane 2 only
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0x0404, // Memory Mode = not odd/even, not full memory, graphics mode
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0x0300, // end sync reset
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EOD
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};
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//
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// Settings to disable the font-loading planar mode.
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//
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USHORT DisableA000Color[] = {
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OWM,
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SEQ_ADDRESS_PORT,
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1,
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0x0100,
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OWM,
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GRAPH_ADDRESS_PORT,
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3,
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0x0004, 0x1005, 0x0E06,
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OWM,
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SEQ_ADDRESS_PORT,
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3,
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0x0302, 0x0204, 0x0300, // end sync reset
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EOD
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};
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