mirror of
https://github.com/reactos/reactos.git
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794 lines
15 KiB
C
794 lines
15 KiB
C
/*
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*
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*/
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#pragma once
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typedef struct _HAL_BIOS_FRAME
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{
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ULONG SegSs;
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ULONG Esp;
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ULONG EFlags;
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ULONG SegCs;
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ULONG Eip;
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PKTRAP_FRAME TrapFrame;
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ULONG CsLimit;
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ULONG CsBase;
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ULONG CsFlags;
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ULONG SsLimit;
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ULONG SsBase;
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ULONG SsFlags;
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ULONG Prefix;
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} HAL_BIOS_FRAME, *PHAL_BIOS_FRAME;
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typedef
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VOID
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(*PHAL_SW_INTERRUPT_HANDLER)(
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VOID
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);
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typedef
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FASTCALL
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VOID
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DECLSPEC_NORETURN
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(*PHAL_SW_INTERRUPT_HANDLER_2ND_ENTRY)(
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IN PKTRAP_FRAME TrapFrame
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);
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#define HAL_APC_REQUEST 0
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#define HAL_DPC_REQUEST 1
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/* CMOS Registers and Ports */
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#define CMOS_CONTROL_PORT (PUCHAR)0x70
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#define CMOS_DATA_PORT (PUCHAR)0x71
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#define RTC_REGISTER_A 0x0A
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#define RTC_REGISTER_B 0x0B
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#define RTC_REG_A_UIP 0x80
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#define RTC_REGISTER_CENTURY 0x32
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/* Usage flags */
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#define IDT_REGISTERED 0x01
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#define IDT_LATCHED 0x02
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#define IDT_READ_ONLY 0x04
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#define IDT_INTERNAL 0x11
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#define IDT_DEVICE 0x21
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/* Conversion functions */
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#define BCD_INT(bcd) \
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(((bcd & 0xF0) >> 4) * 10 + (bcd & 0x0F))
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#define INT_BCD(int) \
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(UCHAR)(((int / 10) << 4) + (int % 10))
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//
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// BIOS Interrupts
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//
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#define VIDEO_SERVICES 0x10
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//
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// Operations for INT 10h (in AH)
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//
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#define SET_VIDEO_MODE 0x00
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//
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// Video Modes for INT10h AH=00 (in AL)
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//
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#define GRAPHICS_MODE_12 0x12 /* 80x30 8x16 640x480 16/256K */
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//
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// Commonly stated as being 1.19318MHz
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//
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// See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
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// P. 471
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//
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// However, the true value is closer to 1.19318181[...]81MHz since this is 1/3rd
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// of the NTSC color subcarrier frequency which runs at 3.57954545[...]45MHz.
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//
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// Note that Windows uses 1.193167MHz which seems to have no basis. However, if
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// one takes the NTSC color subcarrier frequency as being 3.579545 (trimming the
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// infinite series) and divides it by three, one obtains 1.19318167.
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//
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// It may be that the original NT HAL source code introduced a typo and turned
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// 119318167 into 1193167 by ommitting the "18". This is very plausible as the
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// number is quite long.
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//
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#define PIT_FREQUENCY 1193182
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//
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// These ports are controlled by the i8254 Programmable Interrupt Timer (PIT)
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//
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#define TIMER_CHANNEL0_DATA_PORT 0x40
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#define TIMER_CHANNEL1_DATA_PORT 0x41
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#define TIMER_CHANNEL2_DATA_PORT 0x42
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#define TIMER_CONTROL_PORT 0x43
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//
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// Mode 0 - Interrupt On Terminal Count
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// Mode 1 - Hardware Re-triggerable One-Shot
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// Mode 2 - Rate Generator
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// Mode 3 - Square Wave Generator
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// Mode 4 - Software Triggered Strobe
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// Mode 5 - Hardware Triggered Strobe
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//
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typedef enum _TIMER_OPERATING_MODES
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{
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PitOperatingMode0,
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PitOperatingMode1,
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PitOperatingMode2,
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PitOperatingMode3,
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PitOperatingMode4,
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PitOperatingMode5,
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PitOperatingMode2Reserved,
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PitOperatingMode5Reserved
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} TIMER_OPERATING_MODES;
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typedef enum _TIMER_ACCESS_MODES
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{
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PitAccessModeCounterLatch,
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PitAccessModeLow,
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PitAccessModeHigh,
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PitAccessModeLowHigh
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} TIMER_ACCESS_MODES;
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typedef enum _TIMER_CHANNELS
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{
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PitChannel0,
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PitChannel1,
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PitChannel2,
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PitReadBack
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} TIMER_CHANNELS;
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typedef union _TIMER_CONTROL_PORT_REGISTER
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{
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struct
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{
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UCHAR BcdMode:1;
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TIMER_OPERATING_MODES OperatingMode:3;
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TIMER_ACCESS_MODES AccessMode:2;
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TIMER_CHANNELS Channel:2;
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};
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UCHAR Bits;
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} TIMER_CONTROL_PORT_REGISTER, *PTIMER_CONTROL_PORT_REGISTER;
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//
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// See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
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// P. 400
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//
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// This port is controled by the i8255 Programmable Peripheral Interface (PPI)
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//
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#define SYSTEM_CONTROL_PORT_A 0x92
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#define SYSTEM_CONTROL_PORT_B 0x61
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typedef union _SYSTEM_CONTROL_PORT_B_REGISTER
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{
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struct
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{
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UCHAR Timer2GateToSpeaker:1;
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UCHAR SpeakerDataEnable:1;
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UCHAR ParityCheckEnable:1;
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UCHAR ChannelCheckEnable:1;
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UCHAR RefreshRequest:1;
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UCHAR Timer2Output:1;
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UCHAR ChannelCheck:1;
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UCHAR ParityCheck:1;
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};
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UCHAR Bits;
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} SYSTEM_CONTROL_PORT_B_REGISTER, *PSYSTEM_CONTROL_PORT_B_REGISTER;
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//
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// See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
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// P. 396, 397
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//
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// These ports are controlled by the i8259 Programmable Interrupt Controller (PIC)
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//
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#define PIC1_CONTROL_PORT 0x20
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#define PIC1_DATA_PORT 0x21
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#define PIC2_CONTROL_PORT 0xA0
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#define PIC2_DATA_PORT 0xA1
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//
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// Definitions for ICW/OCW Bits
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//
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typedef enum _I8259_ICW1_OPERATING_MODE
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{
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Cascade,
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Single
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} I8259_ICW1_OPERATING_MODE;
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typedef enum _I8259_ICW1_INTERRUPT_MODE
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{
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EdgeTriggered,
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LevelTriggered
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} I8259_ICW1_INTERRUPT_MODE;
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typedef enum _I8259_ICW1_INTERVAL
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{
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Interval8,
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Interval4
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} I8259_ICW1_INTERVAL;
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typedef enum _I8259_ICW4_SYSTEM_MODE
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{
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Mcs8085Mode,
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New8086Mode
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} I8259_ICW4_SYSTEM_MODE;
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typedef enum _I8259_ICW4_EOI_MODE
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{
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NormalEoi,
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AutomaticEoi
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} I8259_ICW4_EOI_MODE;
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typedef enum _I8259_ICW4_BUFFERED_MODE
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{
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NonBuffered,
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NonBuffered2,
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BufferedSlave,
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BufferedMaster
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} I8259_ICW4_BUFFERED_MODE;
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typedef enum _I8259_READ_REQUEST
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{
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InvalidRequest,
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InvalidRequest2,
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ReadIdr,
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ReadIsr
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} I8259_READ_REQUEST;
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typedef enum _I8259_EOI_MODE
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{
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RotateAutoEoiClear,
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NonSpecificEoi,
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InvalidEoiMode,
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SpecificEoi,
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RotateAutoEoiSet,
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RotateNonSpecific,
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SetPriority,
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RotateSpecific
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} I8259_EOI_MODE;
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//
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// Definitions for ICW Registers
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//
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typedef union _I8259_ICW1
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{
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struct
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{
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UCHAR NeedIcw4:1;
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I8259_ICW1_OPERATING_MODE OperatingMode:1;
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I8259_ICW1_INTERVAL Interval:1;
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I8259_ICW1_INTERRUPT_MODE InterruptMode:1;
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UCHAR Init:1;
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UCHAR InterruptVectorAddress:3;
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};
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UCHAR Bits;
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} I8259_ICW1, *PI8259_ICW1;
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typedef union _I8259_ICW2
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{
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struct
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{
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UCHAR Sbz:3;
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UCHAR InterruptVector:5;
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};
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UCHAR Bits;
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} I8259_ICW2, *PI8259_ICW2;
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typedef union _I8259_ICW3
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{
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union
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{
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struct
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{
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UCHAR SlaveIrq0:1;
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UCHAR SlaveIrq1:1;
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UCHAR SlaveIrq2:1;
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UCHAR SlaveIrq3:1;
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UCHAR SlaveIrq4:1;
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UCHAR SlaveIrq5:1;
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UCHAR SlaveIrq6:1;
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UCHAR SlaveIrq7:1;
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};
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struct
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{
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UCHAR SlaveId:3;
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UCHAR Reserved:5;
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};
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};
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UCHAR Bits;
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} I8259_ICW3, *PI8259_ICW3;
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typedef union _I8259_ICW4
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{
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struct
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{
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I8259_ICW4_SYSTEM_MODE SystemMode:1;
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I8259_ICW4_EOI_MODE EoiMode:1;
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I8259_ICW4_BUFFERED_MODE BufferedMode:2;
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UCHAR SpecialFullyNestedMode:1;
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UCHAR Reserved:3;
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};
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UCHAR Bits;
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} I8259_ICW4, *PI8259_ICW4;
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typedef union _I8259_OCW2
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{
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struct
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{
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UCHAR IrqNumber:3;
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UCHAR Sbz:2;
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I8259_EOI_MODE EoiMode:3;
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};
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UCHAR Bits;
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} I8259_OCW2, *PI8259_OCW2;
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typedef union _I8259_OCW3
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{
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struct
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{
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I8259_READ_REQUEST ReadRequest:2;
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UCHAR PollCommand:1;
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UCHAR Sbo:1;
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UCHAR Sbz:1;
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UCHAR SpecialMaskMode:2;
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UCHAR Reserved:1;
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};
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UCHAR Bits;
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} I8259_OCW3, *PI8259_OCW3;
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typedef union _I8259_ISR
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{
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union
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{
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struct
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{
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UCHAR Irq0:1;
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UCHAR Irq1:1;
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UCHAR Irq2:1;
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UCHAR Irq3:1;
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UCHAR Irq4:1;
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UCHAR Irq5:1;
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UCHAR Irq6:1;
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UCHAR Irq7:1;
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};
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};
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UCHAR Bits;
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} I8259_ISR, *PI8259_ISR;
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typedef I8259_ISR I8259_IDR, *PI8259_IDR;
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//
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// See EISA System Architecture 2nd Edition (Tom Shanley, Don Anderson, John Swindle)
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// P. 34, 35
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//
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// These ports are controlled by the i8259A Programmable Interrupt Controller (PIC)
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//
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#define EISA_ELCR_MASTER 0x4D0
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#define EISA_ELCR_SLAVE 0x4D1
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typedef union _EISA_ELCR
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{
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struct
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{
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struct
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{
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UCHAR Irq0Level:1;
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UCHAR Irq1Level:1;
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UCHAR Irq2Level:1;
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UCHAR Irq3Level:1;
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UCHAR Irq4Level:1;
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UCHAR Irq5Level:1;
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UCHAR Irq6Level:1;
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UCHAR Irq7Level:1;
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} Master;
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struct
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{
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UCHAR Irq8Level:1;
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UCHAR Irq9Level:1;
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UCHAR Irq10Level:1;
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UCHAR Irq11Level:1;
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UCHAR Irq12Level:1;
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UCHAR Irq13Level:1;
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UCHAR Irq14Level:1;
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UCHAR Irq15Level:1;
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} Slave;
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};
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USHORT Bits;
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} EISA_ELCR, *PEISA_ELCR;
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typedef struct _PIC_MASK
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{
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union
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{
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struct
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{
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UCHAR Master;
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UCHAR Slave;
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};
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USHORT Both;
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};
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} PIC_MASK, *PPIC_MASK;
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typedef
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BOOLEAN
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__attribute__((regparm(3)))
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(*PHAL_DISMISS_INTERRUPT)(
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IN KIRQL Irql,
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IN ULONG Irq,
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OUT PKIRQL OldIrql
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);
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BOOLEAN
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__attribute__((regparm(3)))
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HalpDismissIrqGeneric(
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IN KIRQL Irql,
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IN ULONG Irq,
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OUT PKIRQL OldIrql
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);
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BOOLEAN
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__attribute__((regparm(3)))
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HalpDismissIrq15(
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IN KIRQL Irql,
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IN ULONG Irq,
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OUT PKIRQL OldIrql
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);
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BOOLEAN
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__attribute__((regparm(3)))
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HalpDismissIrq13(
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IN KIRQL Irql,
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IN ULONG Irq,
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OUT PKIRQL OldIrql
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);
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BOOLEAN
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__attribute__((regparm(3)))
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HalpDismissIrq07(
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IN KIRQL Irql,
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IN ULONG Irq,
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OUT PKIRQL OldIrql
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);
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BOOLEAN
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__attribute__((regparm(3)))
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HalpDismissIrqLevel(
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IN KIRQL Irql,
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IN ULONG Irq,
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OUT PKIRQL OldIrql
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);
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BOOLEAN
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__attribute__((regparm(3)))
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HalpDismissIrq15Level(
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IN KIRQL Irql,
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IN ULONG Irq,
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OUT PKIRQL OldIrql
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);
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BOOLEAN
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__attribute__((regparm(3)))
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HalpDismissIrq13Level(
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IN KIRQL Irql,
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IN ULONG Irq,
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OUT PKIRQL OldIrql
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);
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BOOLEAN
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__attribute__((regparm(3)))
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HalpDismissIrq07Level(
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IN KIRQL Irql,
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IN ULONG Irq,
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OUT PKIRQL OldIrql
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);
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VOID
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HalpHardwareInterruptLevel(
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VOID
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);
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//
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// Mm PTE/PDE to Hal PTE/PDE
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//
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#define HalAddressToPde(x) (PHARDWARE_PTE)MiAddressToPde(x)
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#define HalAddressToPte(x) (PHARDWARE_PTE)MiAddressToPte(x)
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typedef struct _IDTUsageFlags
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{
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UCHAR Flags;
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} IDTUsageFlags;
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typedef struct
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{
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KIRQL Irql;
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UCHAR BusReleativeVector;
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} IDTUsage;
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typedef struct _HalAddressUsage
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{
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struct _HalAddressUsage *Next;
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CM_RESOURCE_TYPE Type;
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UCHAR Flags;
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struct
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{
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ULONG Start;
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ULONG Length;
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} Element[];
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} ADDRESS_USAGE, *PADDRESS_USAGE;
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/* adapter.c */
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PADAPTER_OBJECT NTAPI HalpAllocateAdapterEx(ULONG NumberOfMapRegisters,BOOLEAN IsMaster, BOOLEAN Dma32BitAddresses);
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/* sysinfo.c */
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VOID
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NTAPI
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HalpRegisterVector(IN UCHAR Flags,
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IN ULONG BusVector,
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IN ULONG SystemVector,
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IN KIRQL Irql);
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VOID
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NTAPI
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HalpEnableInterruptHandler(IN UCHAR Flags,
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IN ULONG BusVector,
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IN ULONG SystemVector,
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IN KIRQL Irql,
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IN PVOID Handler,
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IN KINTERRUPT_MODE Mode);
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/* pic.c */
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VOID NTAPI HalpInitializePICs(IN BOOLEAN EnableInterrupts);
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VOID HalpApcInterrupt(VOID);
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VOID HalpDispatchInterrupt(VOID);
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VOID HalpDispatchInterrupt2(VOID);
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VOID FASTCALL DECLSPEC_NORETURN HalpApcInterrupt2ndEntry(IN PKTRAP_FRAME TrapFrame);
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VOID FASTCALL DECLSPEC_NORETURN HalpDispatchInterrupt2ndEntry(IN PKTRAP_FRAME TrapFrame);
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/* timer.c */
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VOID NTAPI HalpInitializeClock(VOID);
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VOID HalpClockInterrupt(VOID);
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VOID HalpProfileInterrupt(VOID);
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VOID
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NTAPI
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HalpCalibrateStallExecution(VOID);
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/* pci.c */
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VOID HalpInitPciBus (VOID);
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/* dma.c */
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VOID HalpInitDma (VOID);
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/* Non-generic initialization */
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VOID HalpInitPhase0 (PLOADER_PARAMETER_BLOCK LoaderBlock);
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VOID HalpInitPhase1(VOID);
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VOID
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NTAPI
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HalpFlushTLB(VOID);
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//
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// KD Support
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//
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VOID
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NTAPI
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HalpCheckPowerButton(
|
|
VOID
|
|
);
|
|
|
|
VOID
|
|
NTAPI
|
|
HalpRegisterKdSupportFunctions(
|
|
VOID
|
|
);
|
|
|
|
NTSTATUS
|
|
NTAPI
|
|
HalpSetupPciDeviceForDebugging(
|
|
IN PVOID LoaderBlock,
|
|
IN OUT PDEBUG_DEVICE_DESCRIPTOR PciDevice
|
|
);
|
|
|
|
NTSTATUS
|
|
NTAPI
|
|
HalpReleasePciDeviceForDebugging(
|
|
IN OUT PDEBUG_DEVICE_DESCRIPTOR PciDevice
|
|
);
|
|
|
|
//
|
|
// Memory routines
|
|
//
|
|
PVOID
|
|
NTAPI
|
|
HalpMapPhysicalMemory64(
|
|
IN PHYSICAL_ADDRESS PhysicalAddress,
|
|
IN ULONG NumberPage
|
|
);
|
|
|
|
VOID
|
|
NTAPI
|
|
HalpUnmapVirtualAddress(
|
|
IN PVOID VirtualAddress,
|
|
IN ULONG NumberPages
|
|
);
|
|
|
|
/* sysinfo.c */
|
|
NTSTATUS
|
|
NTAPI
|
|
HaliQuerySystemInformation(
|
|
IN HAL_QUERY_INFORMATION_CLASS InformationClass,
|
|
IN ULONG BufferSize,
|
|
IN OUT PVOID Buffer,
|
|
OUT PULONG ReturnedLength
|
|
);
|
|
|
|
NTSTATUS
|
|
NTAPI
|
|
HaliSetSystemInformation(
|
|
IN HAL_SET_INFORMATION_CLASS InformationClass,
|
|
IN ULONG BufferSize,
|
|
IN OUT PVOID Buffer
|
|
);
|
|
|
|
//
|
|
// BIOS Routines
|
|
//
|
|
BOOLEAN
|
|
NTAPI
|
|
HalpBiosDisplayReset(
|
|
VOID
|
|
);
|
|
|
|
VOID
|
|
FASTCALL
|
|
HalpExitToV86(
|
|
PKTRAP_FRAME TrapFrame
|
|
);
|
|
|
|
VOID
|
|
DECLSPEC_NORETURN
|
|
HalpRealModeStart(
|
|
VOID
|
|
);
|
|
|
|
//
|
|
// Processor Halt Routine
|
|
//
|
|
VOID
|
|
NTAPI
|
|
HaliHaltSystem(
|
|
VOID
|
|
);
|
|
|
|
//
|
|
// CMOS initialization
|
|
//
|
|
VOID
|
|
NTAPI
|
|
HalpInitializeCmos(
|
|
VOID
|
|
);
|
|
|
|
//
|
|
// Spinlock for protecting CMOS access
|
|
//
|
|
VOID
|
|
NTAPI
|
|
HalpAcquireSystemHardwareSpinLock(
|
|
VOID
|
|
);
|
|
|
|
VOID
|
|
NTAPI
|
|
HalpReleaseCmosSpinLock(
|
|
VOID
|
|
);
|
|
|
|
ULONG
|
|
NTAPI
|
|
HalpAllocPhysicalMemory(
|
|
IN PLOADER_PARAMETER_BLOCK LoaderBlock,
|
|
IN ULONG MaxAddress,
|
|
IN ULONG PageCount,
|
|
IN BOOLEAN Aligned
|
|
);
|
|
|
|
PVOID
|
|
NTAPI
|
|
HalpMapPhysicalMemory64(
|
|
IN PHYSICAL_ADDRESS PhysicalAddress,
|
|
IN ULONG PageCount
|
|
);
|
|
|
|
NTSTATUS
|
|
NTAPI
|
|
HalpOpenRegistryKey(
|
|
IN PHANDLE KeyHandle,
|
|
IN HANDLE RootKey,
|
|
IN PUNICODE_STRING KeyName,
|
|
IN ACCESS_MASK DesiredAccess,
|
|
IN BOOLEAN Create
|
|
);
|
|
|
|
VOID
|
|
NTAPI
|
|
HalpGetNMICrashFlag(
|
|
VOID
|
|
);
|
|
|
|
BOOLEAN
|
|
NTAPI
|
|
HalpGetDebugPortTable(
|
|
VOID
|
|
);
|
|
|
|
VOID
|
|
NTAPI
|
|
HalpReportSerialNumber(
|
|
VOID
|
|
);
|
|
|
|
NTSTATUS
|
|
NTAPI
|
|
HalpMarkAcpiHal(
|
|
VOID
|
|
);
|
|
|
|
VOID
|
|
NTAPI
|
|
HalpBuildAddressMap(
|
|
VOID
|
|
);
|
|
|
|
VOID
|
|
NTAPI
|
|
HalpReportResourceUsage(
|
|
IN PUNICODE_STRING HalName,
|
|
IN INTERFACE_TYPE InterfaceType
|
|
);
|
|
|
|
ULONG
|
|
NTAPI
|
|
HalpIs16BitPortDecodeSupported(
|
|
VOID
|
|
);
|
|
|
|
NTSTATUS
|
|
NTAPI
|
|
HalpQueryAcpiResourceRequirements(
|
|
OUT PIO_RESOURCE_REQUIREMENTS_LIST *Requirements
|
|
);
|
|
|
|
VOID
|
|
FASTCALL
|
|
KeUpdateSystemTime(
|
|
IN PKTRAP_FRAME TrapFrame,
|
|
IN ULONG Increment,
|
|
IN KIRQL OldIrql
|
|
);
|
|
|
|
#ifdef _M_AMD64
|
|
#define KfLowerIrql KeLowerIrql
|
|
#ifndef CONFIG_SMP
|
|
/* On UP builds, spinlocks don't exist at IRQL >= DISPATCH */
|
|
#define KiAcquireSpinLock(SpinLock)
|
|
#define KiReleaseSpinLock(SpinLock)
|
|
#define KfAcquireSpinLock(SpinLock) KfRaiseIrql(DISPATCH_LEVEL);
|
|
#define KfReleaseSpinLock(SpinLock, OldIrql) KeLowerIrql(OldIrql);
|
|
#endif // !CONFIG_SMP
|
|
#endif // _M_AMD64
|
|
|
|
extern BOOLEAN HalpNMIInProgress;
|
|
|
|
extern ADDRESS_USAGE HalpDefaultIoSpace;
|
|
|
|
extern KSPIN_LOCK HalpSystemHardwareLock;
|
|
|
|
extern PADDRESS_USAGE HalpAddressUsageList;
|
|
|
|
extern LARGE_INTEGER HalpPerfCounter;
|
|
|
|
extern KAFFINITY HalpActiveProcessors;
|
|
|
|
extern BOOLEAN HalDisableFirmwareMapper;
|
|
extern PWCHAR HalHardwareIdString;
|
|
extern PWCHAR HalName;
|