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https://github.com/reactos/reactos.git
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182 lines
3.3 KiB
C
182 lines
3.3 KiB
C
#pragma once
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#include "intrin_i.h"
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#define KiServiceExit2 KiExceptionExit
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#define SYNCH_LEVEL DISPATCH_LEVEL
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#define PCR ((KPCR * const)KIP0PCRADDRESS)
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//
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//Lockdown TLB entries
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//
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#define PCR_ENTRY 0
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#define PDR_ENTRY 2
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//
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// BKPT is 4 bytes long
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//
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#define KD_BREAKPOINT_TYPE ULONG
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#define KD_BREAKPOINT_SIZE sizeof(ULONG)
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#define KD_BREAKPOINT_VALUE 0xDEFE
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//
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// Maximum IRQs
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//
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#define MAXIMUM_VECTOR 16
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//
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// Macros for getting and setting special purpose registers in portable code
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//
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#define KeGetContextPc(Context) \
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((Context)->Pc)
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#define KeSetContextPc(Context, ProgramCounter) \
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((Context)->Pc = (ProgramCounter))
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#define KeGetTrapFramePc(TrapFrame) \
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((TrapFrame)->Pc)
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#define KeGetContextReturnRegister(Context) \
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((Context)->R0)
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#define KeSetContextReturnRegister(Context, ReturnValue) \
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((Context)->R0 = (ReturnValue))
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//
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// Macro to get trap and exception frame from a thread stack
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//
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#define KeGetTrapFrame(Thread) \
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(PKTRAP_FRAME)((ULONG_PTR)((Thread)->InitialStack) - \
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sizeof(KTRAP_FRAME))
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#define KeGetExceptionFrame(Thread) \
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(PKEXCEPTION_FRAME)((ULONG_PTR)KeGetTrapFrame(Thread) - \
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sizeof(KEXCEPTION_FRAME))
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//
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// Macro to get context switches from the PRCB
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// All architectures but x86 have it in the PRCB's KeContextSwitches
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//
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#define KeGetContextSwitches(Prcb) \
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(Prcb)->KeContextSwitches
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//
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// Macro to get the second level cache size field name which differs between
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// CISC and RISC architectures, as the former has unified I/D cache
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//
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#define KiGetSecondLevelDCacheSize() ((PKIPCR)KeGetPcr())->SecondLevelDcacheSize
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//
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// Returns the Interrupt State from a Trap Frame.
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// ON = TRUE, OFF = FALSE
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//
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#define KeGetTrapFrameInterruptState(TrapFrame) 0
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FORCEINLINE
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BOOLEAN
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KeDisableInterrupts(VOID)
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{
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ARM_STATUS_REGISTER Flags;
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//
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// Get current interrupt state and disable interrupts
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//
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Flags = KeArmStatusRegisterGet();
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_disable();
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//
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// Return previous interrupt state
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//
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return Flags.IrqDisable;
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}
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FORCEINLINE
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VOID
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KeRestoreInterrupts(BOOLEAN WereEnabled)
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{
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if (WereEnabled) _enable();
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}
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//
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// Invalidates the TLB entry for a specified address
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//
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FORCEINLINE
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VOID
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KeInvalidateTlbEntry(IN PVOID Address)
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{
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/* Invalidate the TLB entry for this address */
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KeArmInvalidateTlbEntry(Address);
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}
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FORCEINLINE
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VOID
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KeFlushProcessTb(VOID)
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{
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KeArmFlushTlb();
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}
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FORCEINLINE
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VOID
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KeSweepICache(IN PVOID BaseAddress,
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IN SIZE_T FlushSize)
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{
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//
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// Always sweep the whole cache
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//
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UNREFERENCED_PARAMETER(BaseAddress);
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UNREFERENCED_PARAMETER(FlushSize);
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_MoveToCoprocessor(0, CP15_ICIALLU);
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}
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FORCEINLINE
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VOID
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KiRundownThread(IN PKTHREAD Thread)
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{
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/* FIXME */
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}
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VOID
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KiPassiveRelease(
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VOID
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);
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VOID
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KiSystemService(IN PKTHREAD Thread,
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IN PKTRAP_FRAME TrapFrame,
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IN ULONG Instruction);
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VOID
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KiApcInterrupt(
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VOID
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);
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#include "mm.h"
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VOID
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KeFlushTb(
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VOID
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);
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//
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// Cache clean and flush
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//
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VOID
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HalSweepDcache(
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VOID
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);
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VOID
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HalSweepIcache(
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VOID
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);
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#define Ki386PerfEnd()
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#define KiEndInterrupt(x,y)
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#define KiGetLinkedTrapFrame(x) \
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(PKTRAP_FRAME)((x)->TrapFrame)
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#define KiGetPreviousMode(tf) \
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((tf->Cpsr & CPSRM_MASK) == CPSRM_USER) ? UserMode: KernelMode
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