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![Aman Priyadarshi](/assets/img/avatar_default.png)
- Driver loaded successfully - Added Debug stubs svn path=/branches/GSoC_2016/AHCI/; revision=71511
215 lines
6.6 KiB
C
215 lines
6.6 KiB
C
/*
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* PROJECT: ReactOS Kernel
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* LICENSE: GNU GPLv2 only as published by the Free Software Foundation
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* PURPOSE: To Implement AHCI Miniport driver targeting storport NT 5.2
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* PROGRAMMERS: Aman Priyadarshi (aman.eureka@gmail.com)
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*/
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#include "miniport.h"
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#include "storport.h"
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#define AHCI_POOL_TAG 'ahci'
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typedef struct _AHCI_FIS_DMA_SETUP
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{
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ULONG ULONG0_1; // FIS_TYPE_DMA_SETUP
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// Port multiplier
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// Reserved
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// Data transfer direction, 1 - device to host
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// Interrupt bit
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// Auto-activate. Specifies if DMA Activate FIS is needed
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UCHAR Reserved[2]; // Reserved
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ULONG DmaBufferLow; // DMA Buffer Identifier. Used to Identify DMA buffer in host memory. SATA Spec says host specific and not in Spec. Trying AHCI spec might work.
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ULONG DmaBufferHigh;
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ULONG Reserved2; //More reserved
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ULONG DmaBufferOffset; //Byte offset into buffer. First 2 bits must be 0
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ULONG TranferCount; //Number of bytes to transfer. Bit 0 must be 0
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ULONG Reserved3; //Reserved
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} AHCI_FIS_DMA_SETUP;
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typedef struct _AHCI_PIO_SETUP_FIS
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{
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UCHAR FisType; //0x5F
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UCHAR Reserved1 :5;
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UCHAR D :1; // 1 is write (device to host)
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UCHAR I :1;
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UCHAR Reserved2 :1;
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UCHAR Status;
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UCHAR Error;
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UCHAR SectorNumber;
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UCHAR CylLow;
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UCHAR CylHigh;
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UCHAR Dev_Head;
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UCHAR SectorNumb_Exp;
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UCHAR CylLow_Exp;
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UCHAR CylHigh_Exp;
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UCHAR Reserved3;
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UCHAR SectorCount;
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UCHAR SectorCount_Exp;
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UCHAR Reserved4;
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UCHAR E_Status;
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USHORT TransferCount;
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UCHAR Reserved5[2];
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} AHCI_PIO_SETUP_FIS;
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typedef struct _AHCI_D2H_REGISTER_FIS
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{
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UCHAR FisType; // 0x34
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UCHAR Reserved1 :6;
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UCHAR I:1;
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UCHAR Reserved2 :1;
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UCHAR Status;
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UCHAR Error;
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UCHAR SectorNumber;
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UCHAR CylLow;
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UCHAR CylHigh;
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UCHAR Dev_Head;
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UCHAR SectorNum_Exp;
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UCHAR CylLow_Exp;
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UCHAR CylHigh_Exp;
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UCHAR Reserved;
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UCHAR SectorCount;
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UCHAR SectorCount_Exp;
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UCHAR Reserved3[2];
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UCHAR Reserved4[4];
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} AHCI_D2H_REGISTER_FIS;
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typedef struct _AHCI_SET_DEVICE_BITS_FIS {
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UCHAR FisType; //0xA1
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UCHAR PMPort: 4;
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UCHAR Reserved1 :2;
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UCHAR I :1;
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UCHAR N :1;
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UCHAR Status_Lo :3;
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UCHAR Reserved2 :1;
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UCHAR Status_Hi :3;
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UCHAR Reserved3 :1;
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UCHAR Error;
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UCHAR Reserved5[4];
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} AHCI_SET_DEVICE_BITS_FIS;
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// 4.2.2
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typedef struct _AHCI_COMMAND_HEADER
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{
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ULONG HEADER_DESCRIPTION; // DW 0
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ULONG PRDBC; // DW 1
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ULONG CTBA0; // DW 2
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ULONG CTBA_U0; // DW 3
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ULONG Reserved[4]; // DW 4-7
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} AHCI_COMMAND_HEADER, *PAHCI_COMMAND_HEADER;
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// Received FIS
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typedef struct _AHCI_RECEIVED_FIS
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{
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AHCI_FIS_DMA_SETUP DmaSetupFIS; // 0x00 -- DMA Setup FIS
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ULONG pad0; // 4 BYTE padding
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AHCI_PIO_SETUP_FIS PioSetupFIS; // 0x20 -- PIO Setup FIS
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ULONG pad1[3]; // 12 BYTE padding
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AHCI_D2H_REGISTER_FIS RegisterFIS; // 0x40 -- Register – Device to Host FIS
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ULONG pad2; // 4 BYTE padding
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AHCI_SET_DEVICE_BITS_FIS SetDeviceFIS; // 0x58 -- Set Device Bit FIS
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ULONG UnknowFIS[16]; // 0x60 -- Unknown FIS
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ULONG Reserved[24]; // 0xA0 -- Reserved
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} AHCI_RECEIVED_FIS, *PAHCI_RECEIVED_FIS;
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typedef struct _AHCI_PORT
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{
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ULONG CLB; // 0x00, command list base address, 1K-byte aligned
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ULONG CLBU; // 0x04, command list base address upper 32 bits
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ULONG FB; // 0x08, FIS base address, 256-byte aligned
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ULONG FBU; // 0x0C, FIS base address upper 32 bits
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ULONG IS; // 0x10, interrupt status
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ULONG IE; // 0x14, interrupt enable
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ULONG CMD; // 0x18, command and status
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ULONG RSV0; // 0x1C, Reserved
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ULONG TFD; // 0x20, task file data
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ULONG SIG; // 0x24, signature
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ULONG SSTS; // 0x28, SATA status (SCR0:SStatus)
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ULONG SCTL; // 0x2C, SATA control (SCR2:SControl)
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ULONG SERR; // 0x30, SATA error (SCR1:SError)
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ULONG SACT; // 0x34, SATA active (SCR3:SActive)
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ULONG CI; // 0x38, command issue
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ULONG SNTF; // 0x3C, SATA notification (SCR4:SNotification)
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ULONG FBS; // 0x40, FIS-based switch control
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ULONG RSV1[11]; // 0x44 ~ 0x6F, Reserved
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ULONG Vendor[4]; // 0x70 ~ 0x7F, vendor specific
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} AHCI_PORT, *PAHCI_PORT;
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typedef struct _AHCI_MEMORY_REGISTERS
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{
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// 0x00 - 0x2B, Generic Host Control
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ULONG CAP; // 0x00, Host capability
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ULONG GHC; // 0x04, Global host control
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ULONG IS; // 0x08, Interrupt status
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ULONG PI; // 0x0C, Port implemented
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ULONG VS; // 0x10, Version
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ULONG CCC_CTL; // 0x14, Command completion coalescing control
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ULONG CCC_PTS; // 0x18, Command completion coalescing ports
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ULONG EM_LOC; // 0x1C, Enclosure management location
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ULONG EM_CTL; // 0x20, Enclosure management control
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ULONG CAP2; // 0x24, Host capabilities extended
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ULONG BOHC; // 0x28, BIOS/OS handoff control and status
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// 0x2C - 0x9F, Reserved
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ULONG Reserved[0xA0-0x2C];
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// 0xA0 - 0xFF, Vendor specific registers
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ULONG VendorSpecific[0x100-0xA0];
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AHCI_PORT PortList[32];//1~32
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} AHCI_MEMORY_REGISTERS, *PAHCI_MEMORY_REGISTERS;
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struct _AHCI_ADAPTER_EXTENSION;
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typedef struct _AHCI_PORT_EXTENSION
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{
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ULONG PortNumber;
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struct _AHCI_ADAPTER_EXTENSION* AdapterExtension;
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PAHCI_COMMAND_HEADER CommandList;
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PAHCI_RECEIVED_FIS ReceivedFIS;
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PAHCI_PORT Port;
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} AHCI_PORT_EXTENSION, *PAHCI_PORT_EXTENSION;
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typedef struct _AHCI_ADAPTER_EXTENSION
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{
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ULONG AdapterNumber;
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ULONG SystemIoBusNumber;
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ULONG SlotNumber;
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ULONG AhciBaseAddress;
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ULONG IS; // Interrupt status
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ULONG PortImplemented;
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USHORT VendorID;
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USHORT DeviceID;
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USHORT RevisionID;
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ULONG Version;
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ULONG CAP;
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ULONG CAP2;
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PVOID NonCachedExtension;
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PAHCI_MEMORY_REGISTERS ABAR_Address;
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PAHCI_PORT_EXTENSION PortExtension[32];
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} AHCI_ADAPTER_EXTENSION, *PAHCI_ADAPTER_EXTENSION;
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typedef struct _AHCI_SRB_EXTENSION
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{
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ULONG Reserved[4];
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} AHCI_SRB_EXTENSION;
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