mirror of
https://github.com/reactos/reactos.git
synced 2024-08-16 08:29:38 +00:00
841 lines
27 KiB
C
841 lines
27 KiB
C
/*
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* PROJECT: ReactOS Kernel
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* LICENSE: GPL - See COPYING in the top level directory
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* FILE: ntoskrnl/ke/i386/kiinit.c
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* PURPOSE: Kernel Initialization for x86 CPUs
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* PROGRAMMERS: Alex Ionescu (alex.ionescu@reactos.org)
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*/
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/* INCLUDES *****************************************************************/
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#include <ntoskrnl.h>
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#define NDEBUG
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#include <debug.h>
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#include "internal/i386/trap_x.h"
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/* GLOBALS *******************************************************************/
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/* Boot and double-fault/NMI/DPC stack */
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UCHAR DECLSPEC_ALIGN(PAGE_SIZE) P0BootStackData[KERNEL_STACK_SIZE] = {0};
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UCHAR DECLSPEC_ALIGN(PAGE_SIZE) KiDoubleFaultStackData[KERNEL_STACK_SIZE] = {0};
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ULONG_PTR P0BootStack = (ULONG_PTR)&P0BootStackData[KERNEL_STACK_SIZE];
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ULONG_PTR KiDoubleFaultStack = (ULONG_PTR)&KiDoubleFaultStackData[KERNEL_STACK_SIZE];
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/* Spinlocks used only on X86 */
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KSPIN_LOCK KiFreezeExecutionLock;
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KSPIN_LOCK Ki486CompatibilityLock;
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/* Perf */
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ULONG ProcessCount;
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ULONGLONG BootCycles, BootCyclesEnd;
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/* FUNCTIONS *****************************************************************/
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INIT_FUNCTION
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VOID
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NTAPI
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KiInitMachineDependent(VOID)
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{
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ULONG CpuCount;
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BOOLEAN FbCaching = FALSE;
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NTSTATUS Status;
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ULONG ReturnLength;
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ULONG i, Affinity, Sample = 0;
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PFX_SAVE_AREA FxSaveArea;
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ULONG MXCsrMask = 0xFFBF;
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CPU_INFO CpuInfo;
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KI_SAMPLE_MAP Samples[10];
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PKI_SAMPLE_MAP CurrentSample = Samples;
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LARGE_IDENTITY_MAP IdentityMap;
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/* Check for large page support */
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if (KeFeatureBits & KF_LARGE_PAGE)
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{
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/* Do an IPI to enable it on all CPUs */
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if (Ki386CreateIdentityMap(&IdentityMap, Ki386EnableCurrentLargePage, 2))
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KeIpiGenericCall(Ki386EnableTargetLargePage, (ULONG_PTR)&IdentityMap);
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/* Free the pages allocated for identity map */
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Ki386FreeIdentityMap(&IdentityMap);
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}
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/* Check for global page support */
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if (KeFeatureBits & KF_GLOBAL_PAGE)
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{
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/* Do an IPI to enable it on all CPUs */
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CpuCount = KeNumberProcessors;
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KeIpiGenericCall(Ki386EnableGlobalPage, (ULONG_PTR)&CpuCount);
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}
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/* Check for PAT and/or MTRR support */
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if (KeFeatureBits & (KF_PAT | KF_MTRR))
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{
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/* Query the HAL to make sure we can use it */
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Status = HalQuerySystemInformation(HalFrameBufferCachingInformation,
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sizeof(BOOLEAN),
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&FbCaching,
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&ReturnLength);
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if ((NT_SUCCESS(Status)) && (FbCaching))
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{
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/* We can't, disable it */
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KeFeatureBits &= ~(KF_PAT | KF_MTRR);
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}
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}
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/* Check for PAT support and enable it */
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if (KeFeatureBits & KF_PAT) KiInitializePAT();
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/* Assume no errata for now */
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SharedUserData->ProcessorFeatures[PF_FLOATING_POINT_PRECISION_ERRATA] = 0;
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/* Check if we have an NPX */
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if (KeI386NpxPresent)
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{
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/* Loop every CPU */
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i = KeActiveProcessors;
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for (Affinity = 1; i; Affinity <<= 1)
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{
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/* Check if this is part of the set */
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if (i & Affinity)
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{
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/* Run on this CPU */
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i &= ~Affinity;
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KeSetSystemAffinityThread(Affinity);
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/* Detect FPU errata */
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if (KiIsNpxErrataPresent())
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{
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/* Disable NPX support */
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KeI386NpxPresent = FALSE;
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SharedUserData->
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ProcessorFeatures[PF_FLOATING_POINT_PRECISION_ERRATA] =
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TRUE;
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break;
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}
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}
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}
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}
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/* If there's no NPX, then we're emulating the FPU */
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SharedUserData->ProcessorFeatures[PF_FLOATING_POINT_EMULATED] =
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!KeI386NpxPresent;
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/* Check if there's no NPX, so that we can disable associated features */
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if (!KeI386NpxPresent)
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{
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/* Remove NPX-related bits */
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KeFeatureBits &= ~(KF_XMMI64 | KF_XMMI | KF_FXSR | KF_MMX);
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/* Disable kernel flags */
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KeI386FxsrPresent = KeI386XMMIPresent = FALSE;
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/* Disable processor features that might've been set until now */
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SharedUserData->ProcessorFeatures[PF_FLOATING_POINT_PRECISION_ERRATA] =
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SharedUserData->ProcessorFeatures[PF_XMMI64_INSTRUCTIONS_AVAILABLE] =
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SharedUserData->ProcessorFeatures[PF_XMMI_INSTRUCTIONS_AVAILABLE] =
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SharedUserData->ProcessorFeatures[PF_3DNOW_INSTRUCTIONS_AVAILABLE] =
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SharedUserData->ProcessorFeatures[PF_MMX_INSTRUCTIONS_AVAILABLE] = 0;
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}
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/* Check for CR4 support */
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if (KeFeatureBits & KF_CR4)
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{
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/* Do an IPI call to enable the Debug Exceptions */
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CpuCount = KeNumberProcessors;
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KeIpiGenericCall(Ki386EnableDE, (ULONG_PTR)&CpuCount);
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}
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/* Check if FXSR was found */
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if (KeFeatureBits & KF_FXSR)
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{
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/* Do an IPI call to enable the FXSR */
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CpuCount = KeNumberProcessors;
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KeIpiGenericCall(Ki386EnableFxsr, (ULONG_PTR)&CpuCount);
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/* Check if XMM was found too */
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if (KeFeatureBits & KF_XMMI)
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{
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/* Do an IPI call to enable XMMI exceptions */
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CpuCount = KeNumberProcessors;
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KeIpiGenericCall(Ki386EnableXMMIExceptions, (ULONG_PTR)&CpuCount);
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/* FIXME: Implement and enable XMM Page Zeroing for Mm */
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/* Patch the RtlPrefetchMemoryNonTemporal routine to enable it */
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*(PCHAR)RtlPrefetchMemoryNonTemporal = 0x90; // NOP
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}
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}
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/* Check for, and enable SYSENTER support */
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KiRestoreFastSyscallReturnState();
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/* Loop every CPU */
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i = KeActiveProcessors;
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for (Affinity = 1; i; Affinity <<= 1)
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{
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/* Check if this is part of the set */
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if (i & Affinity)
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{
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/* Run on this CPU */
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i &= ~Affinity;
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KeSetSystemAffinityThread(Affinity);
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/* Reset MHz to 0 for this CPU */
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KeGetCurrentPrcb()->MHz = 0;
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/* Check if we can use RDTSC */
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if (KeFeatureBits & KF_RDTSC)
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{
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/* Start sampling loop */
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for (;;)
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{
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/* Do a dummy CPUID to start the sample */
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KiCpuId(&CpuInfo, 0);
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/* Fill out the starting data */
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CurrentSample->PerfStart = KeQueryPerformanceCounter(NULL);
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CurrentSample->TSCStart = __rdtsc();
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CurrentSample->PerfFreq.QuadPart = -50000;
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/* Sleep for this sample */
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KeDelayExecutionThread(KernelMode,
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FALSE,
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&CurrentSample->PerfFreq);
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/* Do another dummy CPUID */
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KiCpuId(&CpuInfo, 0);
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/* Fill out the ending data */
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CurrentSample->PerfEnd =
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KeQueryPerformanceCounter(&CurrentSample->PerfFreq);
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CurrentSample->TSCEnd = __rdtsc();
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/* Calculate the differences */
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CurrentSample->PerfDelta = CurrentSample->PerfEnd.QuadPart -
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CurrentSample->PerfStart.QuadPart;
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CurrentSample->TSCDelta = CurrentSample->TSCEnd -
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CurrentSample->TSCStart;
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/* Compute CPU Speed */
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CurrentSample->MHz = (ULONG)((CurrentSample->TSCDelta *
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CurrentSample->
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PerfFreq.QuadPart + 500000) /
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(CurrentSample->PerfDelta *
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1000000));
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/* Check if this isn't the first sample */
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if (Sample)
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{
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/* Check if we got a good precision within 1MHz */
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if ((CurrentSample->MHz == CurrentSample[-1].MHz) ||
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(CurrentSample->MHz == CurrentSample[-1].MHz + 1) ||
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(CurrentSample->MHz == CurrentSample[-1].MHz - 1))
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{
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/* We did, stop sampling */
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break;
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}
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}
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/* Move on */
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CurrentSample++;
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Sample++;
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if (Sample == RTL_NUMBER_OF(Samples))
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{
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/* No luck. Average the samples and be done */
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ULONG TotalMHz = 0;
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while (Sample--)
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{
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TotalMHz += Samples[Sample].MHz;
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}
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CurrentSample[-1].MHz = TotalMHz / RTL_NUMBER_OF(Samples);
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DPRINT1("Sampling CPU frequency failed. Using average of %lu MHz\n", CurrentSample[-1].MHz);
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break;
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}
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}
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/* Save the CPU Speed */
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KeGetCurrentPrcb()->MHz = CurrentSample[-1].MHz;
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}
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/* Check if we have MTRR */
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if (KeFeatureBits & KF_MTRR)
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{
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/* Then manually initialize MTRR for the CPU */
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KiInitializeMTRR(i ? FALSE : TRUE);
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}
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/* Check if we have AMD MTRR and initialize it for the CPU */
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if (KeFeatureBits & KF_AMDK6MTRR) KiAmdK6InitializeMTRR();
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/* Check if this is a buggy Pentium and apply the fixup if so */
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if (KiI386PentiumLockErrataPresent) KiI386PentiumLockErrataFixup();
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/* Check if the CPU supports FXSR */
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if (KeFeatureBits & KF_FXSR)
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{
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/* Get the current thread NPX state */
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FxSaveArea = KiGetThreadNpxArea(KeGetCurrentThread());
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/* Clear initial MXCsr mask */
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FxSaveArea->U.FxArea.MXCsrMask = 0;
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/* Save the current NPX State */
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Ke386SaveFpuState(FxSaveArea);
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/* Check if the current mask doesn't match the reserved bits */
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if (FxSaveArea->U.FxArea.MXCsrMask != 0)
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{
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/* Then use whatever it's holding */
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MXCsrMask = FxSaveArea->U.FxArea.MXCsrMask;
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}
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/* Check if nobody set the kernel-wide mask */
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if (!KiMXCsrMask)
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{
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/* Then use the one we calculated above */
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KiMXCsrMask = MXCsrMask;
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}
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else
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{
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/* Was it set to the same value we found now? */
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if (KiMXCsrMask != MXCsrMask)
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{
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/* No, something is definitely wrong */
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KeBugCheckEx(MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED,
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KF_FXSR,
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KiMXCsrMask,
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MXCsrMask,
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0);
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}
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}
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/* Now set the kernel mask */
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KiMXCsrMask &= MXCsrMask;
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}
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}
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}
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/* Return affinity back to where it was */
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KeRevertToUserAffinityThread();
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/* NT allows limiting the duration of an ISR with a registry key */
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if (KiTimeLimitIsrMicroseconds)
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{
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/* FIXME: TODO */
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DPRINT1("ISR Time Limit not yet supported\n");
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}
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/* Set CR0 features based on detected CPU */
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KiSetCR0Bits();
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}
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INIT_FUNCTION
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VOID
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NTAPI
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KiInitializePcr(IN ULONG ProcessorNumber,
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IN PKIPCR Pcr,
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IN PKIDTENTRY Idt,
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IN PKGDTENTRY Gdt,
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IN PKTSS Tss,
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IN PKTHREAD IdleThread,
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IN PVOID DpcStack)
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{
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/* Setup the TIB */
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Pcr->NtTib.ExceptionList = EXCEPTION_CHAIN_END;
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Pcr->NtTib.StackBase = 0;
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Pcr->NtTib.StackLimit = 0;
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Pcr->NtTib.Self = NULL;
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/* Set the Current Thread */
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Pcr->PrcbData.CurrentThread = IdleThread;
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/* Set pointers to ourselves */
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Pcr->SelfPcr = (PKPCR)Pcr;
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Pcr->Prcb = &Pcr->PrcbData;
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/* Set the PCR Version */
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Pcr->MajorVersion = PCR_MAJOR_VERSION;
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Pcr->MinorVersion = PCR_MINOR_VERSION;
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/* Set the PCRB Version */
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Pcr->PrcbData.MajorVersion = 1;
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Pcr->PrcbData.MinorVersion = 1;
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/* Set the Build Type */
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Pcr->PrcbData.BuildType = 0;
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#ifndef CONFIG_SMP
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Pcr->PrcbData.BuildType |= PRCB_BUILD_UNIPROCESSOR;
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#endif
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#if DBG
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Pcr->PrcbData.BuildType |= PRCB_BUILD_DEBUG;
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#endif
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/* Set the Processor Number and current Processor Mask */
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Pcr->PrcbData.Number = (UCHAR)ProcessorNumber;
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Pcr->PrcbData.SetMember = 1 << ProcessorNumber;
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/* Set the PRCB for this Processor */
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KiProcessorBlock[ProcessorNumber] = Pcr->Prcb;
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/* Start us out at PASSIVE_LEVEL */
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Pcr->Irql = PASSIVE_LEVEL;
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/* Set the GDI, IDT, TSS and DPC Stack */
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Pcr->GDT = (PVOID)Gdt;
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Pcr->IDT = Idt;
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Pcr->TSS = Tss;
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Pcr->TssCopy = Tss;
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Pcr->PrcbData.DpcStack = DpcStack;
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/* Setup the processor set */
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Pcr->PrcbData.MultiThreadProcessorSet = Pcr->PrcbData.SetMember;
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}
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INIT_FUNCTION
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VOID
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NTAPI
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KiInitializeKernel(IN PKPROCESS InitProcess,
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IN PKTHREAD InitThread,
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IN PVOID IdleStack,
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IN PKPRCB Prcb,
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IN CCHAR Number,
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IN PLOADER_PARAMETER_BLOCK LoaderBlock)
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{
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BOOLEAN NpxPresent;
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ULONG FeatureBits;
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ULONG PageDirectory[2];
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PVOID DpcStack;
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ULONG Vendor[3];
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KIRQL DummyIrql;
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/* Detect and set the CPU Type */
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KiSetProcessorType();
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/* Check if an FPU is present */
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NpxPresent = KiIsNpxPresent();
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/* Initialize the Power Management Support for this PRCB */
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PoInitializePrcb(Prcb);
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/* Bugcheck if this is a 386 CPU */
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if (Prcb->CpuType == 3) KeBugCheckEx(UNSUPPORTED_PROCESSOR, 0x386, 0, 0, 0);
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/* Get the processor features for the CPU */
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FeatureBits = KiGetFeatureBits();
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/* Set the default NX policy (opt-in) */
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SharedUserData->NXSupportPolicy = NX_SUPPORT_POLICY_OPTIN;
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/* Check if NPX is always on */
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if (strstr(KeLoaderBlock->LoadOptions, "NOEXECUTE=ALWAYSON"))
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{
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/* Set it always on */
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SharedUserData->NXSupportPolicy = NX_SUPPORT_POLICY_ALWAYSON;
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FeatureBits |= KF_NX_ENABLED;
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}
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else if (strstr(KeLoaderBlock->LoadOptions, "NOEXECUTE=OPTOUT"))
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{
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/* Set it in opt-out mode */
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SharedUserData->NXSupportPolicy = NX_SUPPORT_POLICY_OPTOUT;
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FeatureBits |= KF_NX_ENABLED;
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}
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else if ((strstr(KeLoaderBlock->LoadOptions, "NOEXECUTE=OPTIN")) ||
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(strstr(KeLoaderBlock->LoadOptions, "NOEXECUTE")))
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{
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/* Set the feature bits */
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FeatureBits |= KF_NX_ENABLED;
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}
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else if ((strstr(KeLoaderBlock->LoadOptions, "NOEXECUTE=ALWAYSOFF")) ||
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(strstr(KeLoaderBlock->LoadOptions, "EXECUTE")))
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{
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/* Set disabled mode */
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SharedUserData->NXSupportPolicy = NX_SUPPORT_POLICY_ALWAYSOFF;
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FeatureBits |= KF_NX_DISABLED;
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}
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/* Save feature bits */
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Prcb->FeatureBits = FeatureBits;
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/* Save CPU state */
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KiSaveProcessorControlState(&Prcb->ProcessorState);
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/* Get cache line information for this CPU */
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KiGetCacheInformation();
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/* Initialize spinlocks and DPC data */
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KiInitSpinLocks(Prcb, Number);
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/* Check if this is the Boot CPU */
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if (!Number)
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{
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/* Set Node Data */
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KeNodeBlock[0] = &KiNode0;
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Prcb->ParentNode = KeNodeBlock[0];
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KeNodeBlock[0]->ProcessorMask = Prcb->SetMember;
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/* Set boot-level flags */
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KeI386NpxPresent = NpxPresent;
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KeI386CpuType = Prcb->CpuType;
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KeI386CpuStep = Prcb->CpuStep;
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KeProcessorArchitecture = PROCESSOR_ARCHITECTURE_INTEL;
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KeProcessorLevel = (USHORT)Prcb->CpuType;
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if (Prcb->CpuID) KeProcessorRevision = Prcb->CpuStep;
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KeFeatureBits = FeatureBits;
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KeI386FxsrPresent = (KeFeatureBits & KF_FXSR) ? TRUE : FALSE;
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KeI386XMMIPresent = (KeFeatureBits & KF_XMMI) ? TRUE : FALSE;
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/* Detect 8-byte compare exchange support */
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if (!(KeFeatureBits & KF_CMPXCHG8B))
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{
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/* Copy the vendor string */
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RtlCopyMemory(Vendor, Prcb->VendorString, sizeof(Vendor));
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/* Bugcheck the system. Windows *requires* this */
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KeBugCheckEx(UNSUPPORTED_PROCESSOR,
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(1 << 24 ) | (Prcb->CpuType << 16) | Prcb->CpuStep,
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Vendor[0],
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Vendor[1],
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Vendor[2]);
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}
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/* Set the current MP Master KPRCB to the Boot PRCB */
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Prcb->MultiThreadSetMaster = Prcb;
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/* Lower to APC_LEVEL */
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KeLowerIrql(APC_LEVEL);
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/* Initialize some spinlocks */
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KeInitializeSpinLock(&KiFreezeExecutionLock);
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KeInitializeSpinLock(&Ki486CompatibilityLock);
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/* Initialize portable parts of the OS */
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KiInitSystem();
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/* Initialize the Idle Process and the Process Listhead */
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InitializeListHead(&KiProcessListHead);
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PageDirectory[0] = 0;
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PageDirectory[1] = 0;
|
|
KeInitializeProcess(InitProcess,
|
|
0,
|
|
0xFFFFFFFF,
|
|
PageDirectory,
|
|
FALSE);
|
|
InitProcess->QuantumReset = MAXCHAR;
|
|
}
|
|
else
|
|
{
|
|
/* FIXME */
|
|
DPRINT1("SMP Boot support not yet present\n");
|
|
}
|
|
|
|
/* Setup the Idle Thread */
|
|
KeInitializeThread(InitProcess,
|
|
InitThread,
|
|
NULL,
|
|
NULL,
|
|
NULL,
|
|
NULL,
|
|
NULL,
|
|
IdleStack);
|
|
InitThread->NextProcessor = Number;
|
|
InitThread->Priority = HIGH_PRIORITY;
|
|
InitThread->State = Running;
|
|
InitThread->Affinity = 1 << Number;
|
|
InitThread->WaitIrql = DISPATCH_LEVEL;
|
|
InitProcess->ActiveProcessors = 1 << Number;
|
|
|
|
/* HACK for MmUpdatePageDir */
|
|
((PETHREAD)InitThread)->ThreadsProcess = (PEPROCESS)InitProcess;
|
|
|
|
/* Set basic CPU Features that user mode can read */
|
|
SharedUserData->ProcessorFeatures[PF_MMX_INSTRUCTIONS_AVAILABLE] =
|
|
(KeFeatureBits & KF_MMX) ? TRUE: FALSE;
|
|
SharedUserData->ProcessorFeatures[PF_COMPARE_EXCHANGE_DOUBLE] =
|
|
(KeFeatureBits & KF_CMPXCHG8B) ? TRUE: FALSE;
|
|
SharedUserData->ProcessorFeatures[PF_XMMI_INSTRUCTIONS_AVAILABLE] =
|
|
((KeFeatureBits & KF_FXSR) && (KeFeatureBits & KF_XMMI)) ? TRUE: FALSE;
|
|
SharedUserData->ProcessorFeatures[PF_XMMI64_INSTRUCTIONS_AVAILABLE] =
|
|
((KeFeatureBits & KF_FXSR) && (KeFeatureBits & KF_XMMI64)) ? TRUE: FALSE;
|
|
SharedUserData->ProcessorFeatures[PF_3DNOW_INSTRUCTIONS_AVAILABLE] =
|
|
(KeFeatureBits & KF_3DNOW) ? TRUE: FALSE;
|
|
SharedUserData->ProcessorFeatures[PF_RDTSC_INSTRUCTION_AVAILABLE] =
|
|
(KeFeatureBits & KF_RDTSC) ? TRUE: FALSE;
|
|
|
|
/* Set up the thread-related fields in the PRCB */
|
|
Prcb->CurrentThread = InitThread;
|
|
Prcb->NextThread = NULL;
|
|
Prcb->IdleThread = InitThread;
|
|
|
|
/* Initialize the Kernel Executive */
|
|
ExpInitializeExecutive(Number, LoaderBlock);
|
|
|
|
/* Only do this on the boot CPU */
|
|
if (!Number)
|
|
{
|
|
/* Calculate the time reciprocal */
|
|
KiTimeIncrementReciprocal =
|
|
KiComputeReciprocal(KeMaximumIncrement,
|
|
&KiTimeIncrementShiftCount);
|
|
|
|
/* Update DPC Values in case they got updated by the executive */
|
|
Prcb->MaximumDpcQueueDepth = KiMaximumDpcQueueDepth;
|
|
Prcb->MinimumDpcRate = KiMinimumDpcRate;
|
|
Prcb->AdjustDpcThreshold = KiAdjustDpcThreshold;
|
|
|
|
/* Allocate the DPC Stack */
|
|
DpcStack = MmCreateKernelStack(FALSE, 0);
|
|
if (!DpcStack) KeBugCheckEx(NO_PAGES_AVAILABLE, 1, 0, 0, 0);
|
|
Prcb->DpcStack = DpcStack;
|
|
|
|
/* Allocate the IOPM save area */
|
|
Ki386IopmSaveArea = ExAllocatePoolWithTag(PagedPool,
|
|
IOPM_SIZE,
|
|
' eK');
|
|
if (!Ki386IopmSaveArea)
|
|
{
|
|
/* Bugcheck. We need this for V86/VDM support. */
|
|
KeBugCheckEx(NO_PAGES_AVAILABLE, 2, IOPM_SIZE, 0, 0);
|
|
}
|
|
}
|
|
|
|
/* Raise to Dispatch */
|
|
KeRaiseIrql(DISPATCH_LEVEL, &DummyIrql);
|
|
|
|
/* Set the Idle Priority to 0. This will jump into Phase 1 */
|
|
KeSetPriorityThread(InitThread, 0);
|
|
|
|
/* If there's no thread scheduled, put this CPU in the Idle summary */
|
|
KiAcquirePrcbLock(Prcb);
|
|
if (!Prcb->NextThread) KiIdleSummary |= 1 << Number;
|
|
KiReleasePrcbLock(Prcb);
|
|
|
|
/* Raise back to HIGH_LEVEL and clear the PRCB for the loader block */
|
|
KeRaiseIrql(HIGH_LEVEL, &DummyIrql);
|
|
LoaderBlock->Prcb = 0;
|
|
}
|
|
|
|
INIT_FUNCTION
|
|
VOID
|
|
FASTCALL
|
|
KiGetMachineBootPointers(IN PKGDTENTRY *Gdt,
|
|
IN PKIDTENTRY *Idt,
|
|
IN PKIPCR *Pcr,
|
|
IN PKTSS *Tss)
|
|
{
|
|
KDESCRIPTOR GdtDescriptor, IdtDescriptor;
|
|
KGDTENTRY TssSelector, PcrSelector;
|
|
USHORT Tr, Fs;
|
|
|
|
/* Get GDT and IDT descriptors */
|
|
Ke386GetGlobalDescriptorTable(&GdtDescriptor.Limit);
|
|
__sidt(&IdtDescriptor.Limit);
|
|
|
|
/* Save IDT and GDT */
|
|
*Gdt = (PKGDTENTRY)GdtDescriptor.Base;
|
|
*Idt = (PKIDTENTRY)IdtDescriptor.Base;
|
|
|
|
/* Get TSS and FS Selectors */
|
|
Tr = Ke386GetTr();
|
|
Fs = Ke386GetFs();
|
|
|
|
/* Get PCR Selector, mask it and get its GDT Entry */
|
|
PcrSelector = *(PKGDTENTRY)((ULONG_PTR)*Gdt + (Fs & ~RPL_MASK));
|
|
|
|
/* Get the KPCR itself */
|
|
*Pcr = (PKIPCR)(ULONG_PTR)(PcrSelector.BaseLow |
|
|
PcrSelector.HighWord.Bytes.BaseMid << 16 |
|
|
PcrSelector.HighWord.Bytes.BaseHi << 24);
|
|
|
|
/* Get TSS Selector, mask it and get its GDT Entry */
|
|
TssSelector = *(PKGDTENTRY)((ULONG_PTR)*Gdt + (Tr & ~RPL_MASK));
|
|
|
|
/* Get the KTSS itself */
|
|
*Tss = (PKTSS)(ULONG_PTR)(TssSelector.BaseLow |
|
|
TssSelector.HighWord.Bytes.BaseMid << 16 |
|
|
TssSelector.HighWord.Bytes.BaseHi << 24);
|
|
}
|
|
|
|
INIT_FUNCTION
|
|
VOID
|
|
NTAPI
|
|
KiSystemStartupBootStack(VOID)
|
|
{
|
|
PKTHREAD Thread;
|
|
|
|
/* Initialize the kernel for the current CPU */
|
|
KiInitializeKernel(&KiInitialProcess.Pcb,
|
|
(PKTHREAD)KeLoaderBlock->Thread,
|
|
(PVOID)(KeLoaderBlock->KernelStack & ~3),
|
|
(PKPRCB)__readfsdword(KPCR_PRCB),
|
|
KeNumberProcessors - 1,
|
|
KeLoaderBlock);
|
|
|
|
/* Set the priority of this thread to 0 */
|
|
Thread = KeGetCurrentThread();
|
|
Thread->Priority = 0;
|
|
|
|
/* Force interrupts enabled and lower IRQL back to DISPATCH_LEVEL */
|
|
_enable();
|
|
KeLowerIrql(DISPATCH_LEVEL);
|
|
|
|
/* Set the right wait IRQL */
|
|
Thread->WaitIrql = DISPATCH_LEVEL;
|
|
|
|
/* Jump into the idle loop */
|
|
KiIdleLoop();
|
|
}
|
|
|
|
static
|
|
VOID
|
|
KiMarkPageAsReadOnly(
|
|
PVOID Address)
|
|
{
|
|
PHARDWARE_PTE PointerPte;
|
|
|
|
/* Make sure the address is page aligned */
|
|
ASSERT(ALIGN_DOWN_POINTER_BY(Address, PAGE_SIZE) == Address);
|
|
|
|
/* Get the PTE address */
|
|
PointerPte = ((PHARDWARE_PTE)PTE_BASE) + ((ULONG_PTR)Address / PAGE_SIZE);
|
|
ASSERT(PointerPte->Valid);
|
|
ASSERT(PointerPte->Write);
|
|
|
|
/* Set as read-only */
|
|
PointerPte->Write = 0;
|
|
|
|
/* Flush the TLB entry */
|
|
__invlpg(Address);
|
|
}
|
|
|
|
INIT_FUNCTION
|
|
VOID
|
|
NTAPI
|
|
KiSystemStartup(IN PLOADER_PARAMETER_BLOCK LoaderBlock)
|
|
{
|
|
ULONG Cpu;
|
|
PKTHREAD InitialThread;
|
|
ULONG InitialStack;
|
|
PKGDTENTRY Gdt;
|
|
PKIDTENTRY Idt;
|
|
KIDTENTRY NmiEntry, DoubleFaultEntry;
|
|
PKTSS Tss;
|
|
PKIPCR Pcr;
|
|
KIRQL DummyIrql;
|
|
|
|
/* Boot cycles timestamp */
|
|
BootCycles = __rdtsc();
|
|
|
|
/* Save the loader block and get the current CPU */
|
|
KeLoaderBlock = LoaderBlock;
|
|
Cpu = KeNumberProcessors;
|
|
if (!Cpu)
|
|
{
|
|
/* If this is the boot CPU, set FS and the CPU Number*/
|
|
Ke386SetFs(KGDT_R0_PCR);
|
|
__writefsdword(KPCR_PROCESSOR_NUMBER, Cpu);
|
|
|
|
/* Set the initial stack and idle thread as well */
|
|
LoaderBlock->KernelStack = (ULONG_PTR)P0BootStack;
|
|
LoaderBlock->Thread = (ULONG_PTR)&KiInitialThread;
|
|
}
|
|
|
|
/* Save the initial thread and stack */
|
|
InitialStack = LoaderBlock->KernelStack;
|
|
InitialThread = (PKTHREAD)LoaderBlock->Thread;
|
|
|
|
/* Clean the APC List Head */
|
|
InitializeListHead(&InitialThread->ApcState.ApcListHead[KernelMode]);
|
|
|
|
/* Initialize the machine type */
|
|
KiInitializeMachineType();
|
|
|
|
/* Skip initial setup if this isn't the Boot CPU */
|
|
if (Cpu) goto AppCpuInit;
|
|
|
|
/* Get GDT, IDT, PCR and TSS pointers */
|
|
KiGetMachineBootPointers(&Gdt, &Idt, &Pcr, &Tss);
|
|
|
|
/* Setup the TSS descriptors and entries */
|
|
Ki386InitializeTss(Tss, Idt, Gdt);
|
|
|
|
/* Initialize the PCR */
|
|
RtlZeroMemory(Pcr, PAGE_SIZE);
|
|
KiInitializePcr(Cpu,
|
|
Pcr,
|
|
Idt,
|
|
Gdt,
|
|
Tss,
|
|
InitialThread,
|
|
(PVOID)KiDoubleFaultStack);
|
|
|
|
/* Set us as the current process */
|
|
InitialThread->ApcState.Process = &KiInitialProcess.Pcb;
|
|
|
|
/* Clear DR6/7 to cleanup bootloader debugging */
|
|
__writefsdword(KPCR_TEB, 0);
|
|
__writefsdword(KPCR_DR6, 0);
|
|
__writefsdword(KPCR_DR7, 0);
|
|
|
|
/* Setup the IDT */
|
|
KeInitExceptions();
|
|
|
|
/* Load Ring 3 selectors for DS/ES */
|
|
Ke386SetDs(KGDT_R3_DATA | RPL_MASK);
|
|
Ke386SetEs(KGDT_R3_DATA | RPL_MASK);
|
|
|
|
/* Save NMI and double fault traps */
|
|
RtlCopyMemory(&NmiEntry, &Idt[2], sizeof(KIDTENTRY));
|
|
RtlCopyMemory(&DoubleFaultEntry, &Idt[8], sizeof(KIDTENTRY));
|
|
|
|
/* Copy kernel's trap handlers */
|
|
RtlCopyMemory(Idt,
|
|
(PVOID)KiIdtDescriptor.Base,
|
|
KiIdtDescriptor.Limit + 1);
|
|
|
|
/* Restore NMI and double fault */
|
|
RtlCopyMemory(&Idt[2], &NmiEntry, sizeof(KIDTENTRY));
|
|
RtlCopyMemory(&Idt[8], &DoubleFaultEntry, sizeof(KIDTENTRY));
|
|
|
|
AppCpuInit:
|
|
/* Loop until we can release the freeze lock */
|
|
do
|
|
{
|
|
/* Loop until execution can continue */
|
|
while (*(volatile PKSPIN_LOCK*)&KiFreezeExecutionLock == (PVOID)1);
|
|
} while(InterlockedBitTestAndSet((PLONG)&KiFreezeExecutionLock, 0));
|
|
|
|
/* Setup CPU-related fields */
|
|
__writefsdword(KPCR_NUMBER, Cpu);
|
|
__writefsdword(KPCR_SET_MEMBER, 1 << Cpu);
|
|
__writefsdword(KPCR_SET_MEMBER_COPY, 1 << Cpu);
|
|
__writefsdword(KPCR_PRCB_SET_MEMBER, 1 << Cpu);
|
|
|
|
/* Initialize the Processor with HAL */
|
|
HalInitializeProcessor(Cpu, KeLoaderBlock);
|
|
|
|
/* Set active processors */
|
|
KeActiveProcessors |= __readfsdword(KPCR_SET_MEMBER);
|
|
KeNumberProcessors++;
|
|
|
|
/* Check if this is the boot CPU */
|
|
if (!Cpu)
|
|
{
|
|
/* Initialize debugging system */
|
|
KdInitSystem(0, KeLoaderBlock);
|
|
|
|
/* Check for break-in */
|
|
if (KdPollBreakIn()) DbgBreakPointWithStatus(DBG_STATUS_CONTROL_C);
|
|
|
|
/* Make the lowest page of the boot and double fault stack read-only */
|
|
KiMarkPageAsReadOnly(P0BootStackData);
|
|
KiMarkPageAsReadOnly(KiDoubleFaultStackData);
|
|
}
|
|
|
|
/* Raise to HIGH_LEVEL */
|
|
KeRaiseIrql(HIGH_LEVEL, &DummyIrql);
|
|
|
|
/* Switch to new kernel stack and start kernel bootstrapping */
|
|
KiSwitchToBootStack(InitialStack & ~3);
|
|
}
|