mirror of
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a7fddf9c07
svn path=/trunk/; revision=29689
74 lines
2.3 KiB
C
74 lines
2.3 KiB
C
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#ifndef __ANY_OP_H__
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#define __ANY_OP_H__
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#define OP_ANY_mov 0x00000000
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#define OP_ANY_ret 0x00000001
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/* We are using same abi as PPC
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* eax = register 3
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* edx = register 4
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* esp = register 1
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* ebp = register 31
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* ecx = 8
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* ebx = 9
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* esi = 10
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* edi = 11
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* mmx/sse/fpu 0 = 12
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* mmx/sse/fpu 1 = 14
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* mmx/sse/fpu 2 = 16
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* mmx/sse/fpu 3 = 18
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* mmx/sse/fpu 4 = 20
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* mmx/sse/fpu 5 = 22
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* mmx/sse/fpu 6 = 24
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* mmx/sse/fpu 7 = 28
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*/
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typedef struct _BrainAnalys
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{
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CPU_UNINT op; /* one tranlator for any cpu type set our own opcode */
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CPU_INT type; /* 1 = source are memmory, 2 source are register */
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/* 4 = dest are memmory, 8 dest are register */
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/* 16 = source are imm */
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/* 32 = soucre -xx(r1) or [eax-xx] */
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/* 64 = dest -xx(r1) or [eax-xx] */
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/* 128 = update form the src be update with dest */
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CPU_INT src_size; /* who many bits are src not vaild for reg*/
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CPU_INT dst_size; /* who many bits are dst not vaild for reg*/
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CPU_UNINT64 src;
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CPU_UNINT64 dst;
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CPU_INT src_extra; /* if type == 32 are set */
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CPU_INT dst_extra; /* if type == 32 are set */
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CPU_UNINT memAdr; /* where are we in the current memory pos + baseaddress */
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CPU_INT row; /* 0 = no row,
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* 1 = row is bcc (conditions),
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* 2 = row is jsr (Call)
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*/
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/* try translate the Adress to a name */
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CPU_BYTE* ptr_next; /* hook next one */
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CPU_BYTE* ptr_prev; /* hook previus one */
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} MYBrainAnalys, *PMYBrainAnalys;
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extern PMYBrainAnalys pMyBrainAnalys; /* current working address */
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extern PMYBrainAnalys pStartMyBrainAnalys; /* start address */
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CPU_INT ConvertToIA32Process( FILE *outfp,
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PMYBrainAnalys pMystart,
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PMYBrainAnalys pMyend, CPU_INT regbits,
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CPU_INT HowManyRegInUse,
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CPU_INT *RegTableCount);
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CPU_INT ConvertToPPCProcess( FILE *outfp,
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PMYBrainAnalys pMystart,
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PMYBrainAnalys pMyend, CPU_INT regbits,
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CPU_INT HowManyRegInUse,
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CPU_INT *RegTableCount);
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#endif
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