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2b9941e7cb
We must not do anything on PDO removal, especially not deleting it. We are allowed to delete it, only once we successfully completed a IRP_MN_QUERY_DEVICE_RELATIONS without with PDO.
1660 lines
53 KiB
C
1660 lines
53 KiB
C
/*
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* PROJECT: ReactOS PCI bus driver
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* FILE: pdo.c
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* PURPOSE: Child device object dispatch routines
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* PROGRAMMERS: Casper S. Hornstrup (chorns@users.sourceforge.net)
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* UPDATE HISTORY:
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* 10-09-2001 CSH Created
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*/
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#include "pci.h"
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#include <initguid.h>
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#include <wdmguid.h>
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#define NDEBUG
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#include <debug.h>
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#if 0
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#define DBGPRINT(...) DbgPrint(__VA_ARGS__)
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#else
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#define DBGPRINT(...)
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#endif
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#define PCI_ADDRESS_MEMORY_ADDRESS_MASK_64 0xfffffffffffffff0ull
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#define PCI_ADDRESS_IO_ADDRESS_MASK_64 0xfffffffffffffffcull
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/*** PRIVATE *****************************************************************/
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static NTSTATUS
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PdoQueryDeviceText(
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IN PDEVICE_OBJECT DeviceObject,
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IN PIRP Irp,
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PIO_STACK_LOCATION IrpSp)
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{
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PPDO_DEVICE_EXTENSION DeviceExtension;
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UNICODE_STRING String;
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NTSTATUS Status;
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DPRINT("Called\n");
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DeviceExtension = (PPDO_DEVICE_EXTENSION)DeviceObject->DeviceExtension;
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switch (IrpSp->Parameters.QueryDeviceText.DeviceTextType)
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{
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case DeviceTextDescription:
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Status = PciDuplicateUnicodeString(RTL_DUPLICATE_UNICODE_STRING_NULL_TERMINATE,
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&DeviceExtension->DeviceDescription,
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&String);
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DPRINT("DeviceTextDescription\n");
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Irp->IoStatus.Information = (ULONG_PTR)String.Buffer;
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break;
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case DeviceTextLocationInformation:
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Status = PciDuplicateUnicodeString(RTL_DUPLICATE_UNICODE_STRING_NULL_TERMINATE,
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&DeviceExtension->DeviceLocation,
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&String);
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DPRINT("DeviceTextLocationInformation\n");
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Irp->IoStatus.Information = (ULONG_PTR)String.Buffer;
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break;
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default:
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Irp->IoStatus.Information = 0;
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Status = STATUS_INVALID_PARAMETER;
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break;
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}
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return Status;
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}
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static NTSTATUS
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PdoQueryId(
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IN PDEVICE_OBJECT DeviceObject,
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IN PIRP Irp,
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PIO_STACK_LOCATION IrpSp)
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{
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PPDO_DEVICE_EXTENSION DeviceExtension;
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UNICODE_STRING String;
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NTSTATUS Status;
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DPRINT("Called\n");
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DeviceExtension = (PPDO_DEVICE_EXTENSION)DeviceObject->DeviceExtension;
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// Irp->IoStatus.Information = 0;
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Status = STATUS_SUCCESS;
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RtlInitUnicodeString(&String, NULL);
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switch (IrpSp->Parameters.QueryId.IdType)
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{
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case BusQueryDeviceID:
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Status = PciDuplicateUnicodeString(RTL_DUPLICATE_UNICODE_STRING_NULL_TERMINATE,
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&DeviceExtension->DeviceID,
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&String);
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DPRINT("DeviceID: %S\n", String.Buffer);
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Irp->IoStatus.Information = (ULONG_PTR)String.Buffer;
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break;
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case BusQueryHardwareIDs:
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Status = PciDuplicateUnicodeString(RTL_DUPLICATE_UNICODE_STRING_NULL_TERMINATE,
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&DeviceExtension->HardwareIDs,
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&String);
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Irp->IoStatus.Information = (ULONG_PTR)String.Buffer;
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break;
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case BusQueryCompatibleIDs:
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Status = PciDuplicateUnicodeString(RTL_DUPLICATE_UNICODE_STRING_NULL_TERMINATE,
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&DeviceExtension->CompatibleIDs,
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&String);
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Irp->IoStatus.Information = (ULONG_PTR)String.Buffer;
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break;
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case BusQueryInstanceID:
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Status = PciDuplicateUnicodeString(RTL_DUPLICATE_UNICODE_STRING_NULL_TERMINATE,
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&DeviceExtension->InstanceID,
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&String);
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DPRINT("InstanceID: %S\n", String.Buffer);
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Irp->IoStatus.Information = (ULONG_PTR)String.Buffer;
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break;
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case BusQueryDeviceSerialNumber:
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default:
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Status = STATUS_NOT_IMPLEMENTED;
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}
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return Status;
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}
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static NTSTATUS
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PdoQueryBusInformation(
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IN PDEVICE_OBJECT DeviceObject,
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IN PIRP Irp,
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PIO_STACK_LOCATION IrpSp)
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{
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PPDO_DEVICE_EXTENSION DeviceExtension;
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PPNP_BUS_INFORMATION BusInformation;
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UNREFERENCED_PARAMETER(IrpSp);
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DPRINT("Called\n");
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DeviceExtension = (PPDO_DEVICE_EXTENSION)DeviceObject->DeviceExtension;
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BusInformation = ExAllocatePoolWithTag(PagedPool, sizeof(PNP_BUS_INFORMATION), TAG_PCI);
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Irp->IoStatus.Information = (ULONG_PTR)BusInformation;
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if (BusInformation != NULL)
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{
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BusInformation->BusTypeGuid = GUID_BUS_TYPE_PCI;
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BusInformation->LegacyBusType = PCIBus;
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BusInformation->BusNumber = DeviceExtension->PciDevice->BusNumber;
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return STATUS_SUCCESS;
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}
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return STATUS_INSUFFICIENT_RESOURCES;
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}
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static NTSTATUS
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PdoQueryCapabilities(
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IN PDEVICE_OBJECT DeviceObject,
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IN PIRP Irp,
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PIO_STACK_LOCATION IrpSp)
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{
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PPDO_DEVICE_EXTENSION DeviceExtension;
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PDEVICE_CAPABILITIES DeviceCapabilities;
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ULONG DeviceNumber, FunctionNumber;
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UNREFERENCED_PARAMETER(Irp);
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DPRINT("Called\n");
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DeviceExtension = (PPDO_DEVICE_EXTENSION)DeviceObject->DeviceExtension;
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DeviceCapabilities = IrpSp->Parameters.DeviceCapabilities.Capabilities;
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if (DeviceCapabilities->Version != 1)
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return STATUS_UNSUCCESSFUL;
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DeviceNumber = DeviceExtension->PciDevice->SlotNumber.u.bits.DeviceNumber;
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FunctionNumber = DeviceExtension->PciDevice->SlotNumber.u.bits.FunctionNumber;
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DeviceCapabilities->UniqueID = FALSE;
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DeviceCapabilities->Address = ((DeviceNumber << 16) & 0xFFFF0000) + (FunctionNumber & 0xFFFF);
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DeviceCapabilities->UINumber = MAXULONG; /* FIXME */
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return STATUS_SUCCESS;
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}
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static BOOLEAN
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PdoReadPciBar(PPDO_DEVICE_EXTENSION DeviceExtension,
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ULONG Offset,
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PULONG OriginalValue,
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PULONG NewValue)
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{
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ULONG Size;
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ULONG AllOnes;
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/* Read the original value */
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Size = HalGetBusDataByOffset(PCIConfiguration,
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DeviceExtension->PciDevice->BusNumber,
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DeviceExtension->PciDevice->SlotNumber.u.AsULONG,
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OriginalValue,
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Offset,
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sizeof(ULONG));
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if (Size != sizeof(ULONG))
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{
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DPRINT1("Wrong size %lu\n", Size);
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return FALSE;
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}
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/* Write all ones to determine which bits are held to zero */
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AllOnes = MAXULONG;
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Size = HalSetBusDataByOffset(PCIConfiguration,
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DeviceExtension->PciDevice->BusNumber,
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DeviceExtension->PciDevice->SlotNumber.u.AsULONG,
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&AllOnes,
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Offset,
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sizeof(ULONG));
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if (Size != sizeof(ULONG))
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{
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DPRINT1("Wrong size %lu\n", Size);
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return FALSE;
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}
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/* Get the range length */
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Size = HalGetBusDataByOffset(PCIConfiguration,
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DeviceExtension->PciDevice->BusNumber,
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DeviceExtension->PciDevice->SlotNumber.u.AsULONG,
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NewValue,
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Offset,
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sizeof(ULONG));
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if (Size != sizeof(ULONG))
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{
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DPRINT1("Wrong size %lu\n", Size);
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return FALSE;
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}
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/* Restore original value */
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Size = HalSetBusDataByOffset(PCIConfiguration,
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DeviceExtension->PciDevice->BusNumber,
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DeviceExtension->PciDevice->SlotNumber.u.AsULONG,
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OriginalValue,
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Offset,
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sizeof(ULONG));
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if (Size != sizeof(ULONG))
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{
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DPRINT1("Wrong size %lu\n", Size);
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return FALSE;
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}
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return TRUE;
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}
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static BOOLEAN
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PdoGetRangeLength(PPDO_DEVICE_EXTENSION DeviceExtension,
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UCHAR Bar,
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PULONGLONG Base,
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PULONGLONG Length,
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PULONG Flags,
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PUCHAR NextBar,
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PULONGLONG MaximumAddress)
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{
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union {
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struct {
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ULONG Bar0;
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ULONG Bar1;
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} Bars;
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ULONGLONG Bar;
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} OriginalValue;
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union {
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struct {
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ULONG Bar0;
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ULONG Bar1;
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} Bars;
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ULONGLONG Bar;
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} NewValue;
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ULONG Offset;
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/* Compute the offset of this BAR in PCI config space */
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Offset = 0x10 + Bar * 4;
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/* Assume this is a 32-bit BAR until we find wrong */
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*NextBar = Bar + 1;
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/* Initialize BAR values to zero */
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OriginalValue.Bar = 0ULL;
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NewValue.Bar = 0ULL;
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/* Read the first BAR */
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if (!PdoReadPciBar(DeviceExtension, Offset,
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&OriginalValue.Bars.Bar0,
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&NewValue.Bars.Bar0))
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{
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return FALSE;
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}
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/* Check if this is a memory BAR */
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if (!(OriginalValue.Bars.Bar0 & PCI_ADDRESS_IO_SPACE))
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{
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/* Write the maximum address if the caller asked for it */
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if (MaximumAddress != NULL)
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{
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if ((OriginalValue.Bars.Bar0 & PCI_ADDRESS_MEMORY_TYPE_MASK) == PCI_TYPE_32BIT)
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{
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*MaximumAddress = 0x00000000FFFFFFFFULL;
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}
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else if ((OriginalValue.Bars.Bar0 & PCI_ADDRESS_MEMORY_TYPE_MASK) == PCI_TYPE_20BIT)
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{
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*MaximumAddress = 0x00000000000FFFFFULL;
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}
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else if ((OriginalValue.Bars.Bar0 & PCI_ADDRESS_MEMORY_TYPE_MASK) == PCI_TYPE_64BIT)
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{
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*MaximumAddress = 0xFFFFFFFFFFFFFFFFULL;
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}
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}
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/* Check if this is a 64-bit BAR */
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if ((OriginalValue.Bars.Bar0 & PCI_ADDRESS_MEMORY_TYPE_MASK) == PCI_TYPE_64BIT)
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{
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/* We've now consumed the next BAR too */
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*NextBar = Bar + 2;
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/* Read the next BAR */
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if (!PdoReadPciBar(DeviceExtension, Offset + 4,
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&OriginalValue.Bars.Bar1,
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&NewValue.Bars.Bar1))
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{
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return FALSE;
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}
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}
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}
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else
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{
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/* Write the maximum I/O port address */
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if (MaximumAddress != NULL)
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{
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*MaximumAddress = 0x00000000FFFFFFFFULL;
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}
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}
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if (NewValue.Bar == 0)
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{
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DPRINT("Unused address register\n");
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*Base = 0;
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*Length = 0;
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*Flags = 0;
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return TRUE;
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}
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*Base = ((OriginalValue.Bar & PCI_ADDRESS_IO_SPACE)
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? (OriginalValue.Bar & PCI_ADDRESS_IO_ADDRESS_MASK_64)
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: (OriginalValue.Bar & PCI_ADDRESS_MEMORY_ADDRESS_MASK_64));
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*Length = ~((NewValue.Bar & PCI_ADDRESS_IO_SPACE)
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? (NewValue.Bar & PCI_ADDRESS_IO_ADDRESS_MASK_64)
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: (NewValue.Bar & PCI_ADDRESS_MEMORY_ADDRESS_MASK_64)) + 1;
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*Flags = (NewValue.Bar & PCI_ADDRESS_IO_SPACE)
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? (NewValue.Bar & ~PCI_ADDRESS_IO_ADDRESS_MASK_64)
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: (NewValue.Bar & ~PCI_ADDRESS_MEMORY_ADDRESS_MASK_64);
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return TRUE;
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}
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static NTSTATUS
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PdoQueryResourceRequirements(
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IN PDEVICE_OBJECT DeviceObject,
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IN PIRP Irp,
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PIO_STACK_LOCATION IrpSp)
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{
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PPDO_DEVICE_EXTENSION DeviceExtension;
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PCI_COMMON_CONFIG PciConfig;
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PIO_RESOURCE_REQUIREMENTS_LIST ResourceList;
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PIO_RESOURCE_DESCRIPTOR Descriptor;
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ULONG Size;
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ULONG ResCount = 0;
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ULONG ListSize;
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UCHAR Bar;
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ULONGLONG Base;
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ULONGLONG Length;
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ULONG Flags;
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ULONGLONG MaximumAddress;
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UNREFERENCED_PARAMETER(IrpSp);
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DPRINT("PdoQueryResourceRequirements() called\n");
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DeviceExtension = (PPDO_DEVICE_EXTENSION)DeviceObject->DeviceExtension;
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/* Get PCI configuration space */
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Size= HalGetBusData(PCIConfiguration,
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DeviceExtension->PciDevice->BusNumber,
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DeviceExtension->PciDevice->SlotNumber.u.AsULONG,
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&PciConfig,
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PCI_COMMON_HDR_LENGTH);
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DPRINT("Size %lu\n", Size);
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if (Size < PCI_COMMON_HDR_LENGTH)
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{
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Irp->IoStatus.Information = 0;
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return STATUS_UNSUCCESSFUL;
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}
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DPRINT("Command register: 0x%04hx\n", PciConfig.Command);
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/* Count required resource descriptors */
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ResCount = 0;
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if (PCI_CONFIGURATION_TYPE(&PciConfig) == PCI_DEVICE_TYPE)
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{
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for (Bar = 0; Bar < PCI_TYPE0_ADDRESSES;)
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{
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if (!PdoGetRangeLength(DeviceExtension,
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Bar,
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&Base,
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&Length,
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&Flags,
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&Bar,
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NULL))
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break;
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if (Length != 0)
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ResCount += 2;
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}
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/* FIXME: Check ROM address */
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if (PciConfig.u.type0.InterruptPin != 0)
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ResCount++;
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}
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else if (PCI_CONFIGURATION_TYPE(&PciConfig) == PCI_BRIDGE_TYPE)
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{
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for (Bar = 0; Bar < PCI_TYPE1_ADDRESSES;)
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{
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if (!PdoGetRangeLength(DeviceExtension,
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Bar,
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&Base,
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&Length,
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&Flags,
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&Bar,
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NULL))
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break;
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if (Length != 0)
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ResCount += 2;
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}
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if (DeviceExtension->PciDevice->PciConfig.BaseClass == PCI_CLASS_BRIDGE_DEV)
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ResCount++;
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}
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else if (PCI_CONFIGURATION_TYPE(&PciConfig) == PCI_CARDBUS_BRIDGE_TYPE)
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{
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/* FIXME: Count Cardbus bridge resources */
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}
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else
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{
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DPRINT1("Unsupported header type %d\n", PCI_CONFIGURATION_TYPE(&PciConfig));
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}
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if (ResCount == 0)
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{
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Irp->IoStatus.Information = 0;
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return STATUS_SUCCESS;
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}
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/* Calculate the resource list size */
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ListSize = FIELD_OFFSET(IO_RESOURCE_REQUIREMENTS_LIST, List[0].Descriptors) +
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ResCount * sizeof(IO_RESOURCE_DESCRIPTOR);
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DPRINT("ListSize %lu (0x%lx)\n", ListSize, ListSize);
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/* Allocate the resource requirements list */
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ResourceList = ExAllocatePoolWithTag(PagedPool,
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ListSize,
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TAG_PCI);
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if (ResourceList == NULL)
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{
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Irp->IoStatus.Information = 0;
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return STATUS_INSUFFICIENT_RESOURCES;
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}
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RtlZeroMemory(ResourceList, ListSize);
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ResourceList->ListSize = ListSize;
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ResourceList->InterfaceType = PCIBus;
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ResourceList->BusNumber = DeviceExtension->PciDevice->BusNumber;
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ResourceList->SlotNumber = DeviceExtension->PciDevice->SlotNumber.u.AsULONG;
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ResourceList->AlternativeLists = 1;
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ResourceList->List[0].Version = 1;
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ResourceList->List[0].Revision = 1;
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ResourceList->List[0].Count = ResCount;
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Descriptor = &ResourceList->List[0].Descriptors[0];
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if (PCI_CONFIGURATION_TYPE(&PciConfig) == PCI_DEVICE_TYPE)
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{
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for (Bar = 0; Bar < PCI_TYPE0_ADDRESSES;)
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{
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if (!PdoGetRangeLength(DeviceExtension,
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Bar,
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&Base,
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&Length,
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&Flags,
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&Bar,
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&MaximumAddress))
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{
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DPRINT1("PdoGetRangeLength() failed\n");
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break;
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}
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if (Length == 0)
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{
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DPRINT("Unused address register\n");
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continue;
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}
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/* Set preferred descriptor */
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Descriptor->Option = IO_RESOURCE_PREFERRED;
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if (Flags & PCI_ADDRESS_IO_SPACE)
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{
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Descriptor->Type = CmResourceTypePort;
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Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
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Descriptor->Flags = CM_RESOURCE_PORT_IO |
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CM_RESOURCE_PORT_16_BIT_DECODE |
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CM_RESOURCE_PORT_POSITIVE_DECODE;
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Descriptor->u.Port.Length = Length;
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Descriptor->u.Port.Alignment = 1;
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Descriptor->u.Port.MinimumAddress.QuadPart = Base;
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Descriptor->u.Port.MaximumAddress.QuadPart = Base + Length - 1;
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}
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else
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{
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Descriptor->Type = CmResourceTypeMemory;
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Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
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Descriptor->Flags = CM_RESOURCE_MEMORY_READ_WRITE |
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(Flags & PCI_ADDRESS_MEMORY_PREFETCHABLE) ? CM_RESOURCE_MEMORY_PREFETCHABLE : 0;
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Descriptor->u.Memory.Length = Length;
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Descriptor->u.Memory.Alignment = 1;
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Descriptor->u.Memory.MinimumAddress.QuadPart = Base;
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Descriptor->u.Memory.MaximumAddress.QuadPart = Base + Length - 1;
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}
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Descriptor++;
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/* Set alternative descriptor */
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Descriptor->Option = IO_RESOURCE_ALTERNATIVE;
|
|
if (Flags & PCI_ADDRESS_IO_SPACE)
|
|
{
|
|
Descriptor->Type = CmResourceTypePort;
|
|
Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
|
|
Descriptor->Flags = CM_RESOURCE_PORT_IO |
|
|
CM_RESOURCE_PORT_16_BIT_DECODE |
|
|
CM_RESOURCE_PORT_POSITIVE_DECODE;
|
|
|
|
Descriptor->u.Port.Length = Length;
|
|
Descriptor->u.Port.Alignment = Length;
|
|
Descriptor->u.Port.MinimumAddress.QuadPart = 0;
|
|
Descriptor->u.Port.MaximumAddress.QuadPart = MaximumAddress;
|
|
}
|
|
else
|
|
{
|
|
Descriptor->Type = CmResourceTypeMemory;
|
|
Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
|
|
Descriptor->Flags = CM_RESOURCE_MEMORY_READ_WRITE |
|
|
(Flags & PCI_ADDRESS_MEMORY_PREFETCHABLE) ? CM_RESOURCE_MEMORY_PREFETCHABLE : 0;
|
|
|
|
Descriptor->u.Memory.Length = Length;
|
|
Descriptor->u.Memory.Alignment = Length;
|
|
Descriptor->u.Port.MinimumAddress.QuadPart = 0;
|
|
Descriptor->u.Port.MaximumAddress.QuadPart = MaximumAddress;
|
|
}
|
|
Descriptor++;
|
|
}
|
|
|
|
/* FIXME: Check ROM address */
|
|
|
|
if (PciConfig.u.type0.InterruptPin != 0)
|
|
{
|
|
Descriptor->Option = 0; /* Required */
|
|
Descriptor->Type = CmResourceTypeInterrupt;
|
|
Descriptor->ShareDisposition = CmResourceShareShared;
|
|
Descriptor->Flags = CM_RESOURCE_INTERRUPT_LEVEL_SENSITIVE;
|
|
|
|
Descriptor->u.Interrupt.MinimumVector = 0;
|
|
Descriptor->u.Interrupt.MaximumVector = 0xFF;
|
|
}
|
|
}
|
|
else if (PCI_CONFIGURATION_TYPE(&PciConfig) == PCI_BRIDGE_TYPE)
|
|
{
|
|
for (Bar = 0; Bar < PCI_TYPE1_ADDRESSES;)
|
|
{
|
|
if (!PdoGetRangeLength(DeviceExtension,
|
|
Bar,
|
|
&Base,
|
|
&Length,
|
|
&Flags,
|
|
&Bar,
|
|
&MaximumAddress))
|
|
{
|
|
DPRINT1("PdoGetRangeLength() failed\n");
|
|
break;
|
|
}
|
|
|
|
if (Length == 0)
|
|
{
|
|
DPRINT("Unused address register\n");
|
|
continue;
|
|
}
|
|
|
|
/* Set preferred descriptor */
|
|
Descriptor->Option = IO_RESOURCE_PREFERRED;
|
|
if (Flags & PCI_ADDRESS_IO_SPACE)
|
|
{
|
|
Descriptor->Type = CmResourceTypePort;
|
|
Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
|
|
Descriptor->Flags = CM_RESOURCE_PORT_IO |
|
|
CM_RESOURCE_PORT_16_BIT_DECODE |
|
|
CM_RESOURCE_PORT_POSITIVE_DECODE;
|
|
|
|
Descriptor->u.Port.Length = Length;
|
|
Descriptor->u.Port.Alignment = 1;
|
|
Descriptor->u.Port.MinimumAddress.QuadPart = Base;
|
|
Descriptor->u.Port.MaximumAddress.QuadPart = Base + Length - 1;
|
|
}
|
|
else
|
|
{
|
|
Descriptor->Type = CmResourceTypeMemory;
|
|
Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
|
|
Descriptor->Flags = CM_RESOURCE_MEMORY_READ_WRITE |
|
|
(Flags & PCI_ADDRESS_MEMORY_PREFETCHABLE) ? CM_RESOURCE_MEMORY_PREFETCHABLE : 0;
|
|
|
|
Descriptor->u.Memory.Length = Length;
|
|
Descriptor->u.Memory.Alignment = 1;
|
|
Descriptor->u.Memory.MinimumAddress.QuadPart = Base;
|
|
Descriptor->u.Memory.MaximumAddress.QuadPart = Base + Length - 1;
|
|
}
|
|
Descriptor++;
|
|
|
|
/* Set alternative descriptor */
|
|
Descriptor->Option = IO_RESOURCE_ALTERNATIVE;
|
|
if (Flags & PCI_ADDRESS_IO_SPACE)
|
|
{
|
|
Descriptor->Type = CmResourceTypePort;
|
|
Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
|
|
Descriptor->Flags = CM_RESOURCE_PORT_IO |
|
|
CM_RESOURCE_PORT_16_BIT_DECODE |
|
|
CM_RESOURCE_PORT_POSITIVE_DECODE;
|
|
|
|
Descriptor->u.Port.Length = Length;
|
|
Descriptor->u.Port.Alignment = Length;
|
|
Descriptor->u.Port.MinimumAddress.QuadPart = 0;
|
|
Descriptor->u.Port.MaximumAddress.QuadPart = MaximumAddress;
|
|
}
|
|
else
|
|
{
|
|
Descriptor->Type = CmResourceTypeMemory;
|
|
Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
|
|
Descriptor->Flags = CM_RESOURCE_MEMORY_READ_WRITE |
|
|
(Flags & PCI_ADDRESS_MEMORY_PREFETCHABLE) ? CM_RESOURCE_MEMORY_PREFETCHABLE : 0;
|
|
|
|
Descriptor->u.Memory.Length = Length;
|
|
Descriptor->u.Memory.Alignment = Length;
|
|
Descriptor->u.Port.MinimumAddress.QuadPart = 0;
|
|
Descriptor->u.Port.MaximumAddress.QuadPart = MaximumAddress;
|
|
}
|
|
Descriptor++;
|
|
}
|
|
|
|
if (DeviceExtension->PciDevice->PciConfig.BaseClass == PCI_CLASS_BRIDGE_DEV)
|
|
{
|
|
Descriptor->Option = 0; /* Required */
|
|
Descriptor->Type = CmResourceTypeBusNumber;
|
|
Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
|
|
|
|
ResourceList->BusNumber =
|
|
Descriptor->u.BusNumber.MinBusNumber =
|
|
Descriptor->u.BusNumber.MaxBusNumber = DeviceExtension->PciDevice->PciConfig.u.type1.SecondaryBus;
|
|
Descriptor->u.BusNumber.Length = 1;
|
|
Descriptor->u.BusNumber.Reserved = 0;
|
|
}
|
|
}
|
|
else if (PCI_CONFIGURATION_TYPE(&PciConfig) == PCI_CARDBUS_BRIDGE_TYPE)
|
|
{
|
|
/* FIXME: Add Cardbus bridge resources */
|
|
}
|
|
|
|
Irp->IoStatus.Information = (ULONG_PTR)ResourceList;
|
|
|
|
return STATUS_SUCCESS;
|
|
}
|
|
|
|
|
|
static NTSTATUS
|
|
PdoQueryResources(
|
|
IN PDEVICE_OBJECT DeviceObject,
|
|
IN PIRP Irp,
|
|
PIO_STACK_LOCATION IrpSp)
|
|
{
|
|
PPDO_DEVICE_EXTENSION DeviceExtension;
|
|
PCI_COMMON_CONFIG PciConfig;
|
|
PCM_RESOURCE_LIST ResourceList;
|
|
PCM_PARTIAL_RESOURCE_LIST PartialList;
|
|
PCM_PARTIAL_RESOURCE_DESCRIPTOR Descriptor;
|
|
ULONG Size;
|
|
ULONG ResCount = 0;
|
|
ULONG ListSize;
|
|
UCHAR Bar;
|
|
ULONGLONG Base;
|
|
ULONGLONG Length;
|
|
ULONG Flags;
|
|
|
|
DPRINT("PdoQueryResources() called\n");
|
|
|
|
UNREFERENCED_PARAMETER(IrpSp);
|
|
DeviceExtension = (PPDO_DEVICE_EXTENSION)DeviceObject->DeviceExtension;
|
|
|
|
/* Get PCI configuration space */
|
|
Size= HalGetBusData(PCIConfiguration,
|
|
DeviceExtension->PciDevice->BusNumber,
|
|
DeviceExtension->PciDevice->SlotNumber.u.AsULONG,
|
|
&PciConfig,
|
|
PCI_COMMON_HDR_LENGTH);
|
|
DPRINT("Size %lu\n", Size);
|
|
if (Size < PCI_COMMON_HDR_LENGTH)
|
|
{
|
|
Irp->IoStatus.Information = 0;
|
|
return STATUS_UNSUCCESSFUL;
|
|
}
|
|
|
|
DPRINT("Command register: 0x%04hx\n", PciConfig.Command);
|
|
|
|
/* Count required resource descriptors */
|
|
ResCount = 0;
|
|
if (PCI_CONFIGURATION_TYPE(&PciConfig) == PCI_DEVICE_TYPE)
|
|
{
|
|
for (Bar = 0; Bar < PCI_TYPE0_ADDRESSES;)
|
|
{
|
|
if (!PdoGetRangeLength(DeviceExtension,
|
|
Bar,
|
|
&Base,
|
|
&Length,
|
|
&Flags,
|
|
&Bar,
|
|
NULL))
|
|
break;
|
|
|
|
if (Length)
|
|
ResCount++;
|
|
}
|
|
|
|
if ((PciConfig.u.type0.InterruptPin != 0) &&
|
|
(PciConfig.u.type0.InterruptLine != 0) &&
|
|
(PciConfig.u.type0.InterruptLine != 0xFF))
|
|
ResCount++;
|
|
}
|
|
else if (PCI_CONFIGURATION_TYPE(&PciConfig) == PCI_BRIDGE_TYPE)
|
|
{
|
|
for (Bar = 0; Bar < PCI_TYPE1_ADDRESSES;)
|
|
{
|
|
if (!PdoGetRangeLength(DeviceExtension,
|
|
Bar,
|
|
&Base,
|
|
&Length,
|
|
&Flags,
|
|
&Bar,
|
|
NULL))
|
|
break;
|
|
|
|
if (Length != 0)
|
|
ResCount++;
|
|
}
|
|
|
|
if (DeviceExtension->PciDevice->PciConfig.BaseClass == PCI_CLASS_BRIDGE_DEV)
|
|
ResCount++;
|
|
}
|
|
else if (PCI_CONFIGURATION_TYPE(&PciConfig) == PCI_CARDBUS_BRIDGE_TYPE)
|
|
{
|
|
/* FIXME: Count Cardbus bridge resources */
|
|
}
|
|
else
|
|
{
|
|
DPRINT1("Unsupported header type %d\n", PCI_CONFIGURATION_TYPE(&PciConfig));
|
|
}
|
|
|
|
if (ResCount == 0)
|
|
{
|
|
Irp->IoStatus.Information = 0;
|
|
return STATUS_SUCCESS;
|
|
}
|
|
|
|
/* Calculate the resource list size */
|
|
ListSize = FIELD_OFFSET(CM_RESOURCE_LIST, List[0].PartialResourceList.PartialDescriptors) +
|
|
ResCount * sizeof(CM_PARTIAL_RESOURCE_DESCRIPTOR);
|
|
|
|
/* Allocate the resource list */
|
|
ResourceList = ExAllocatePoolWithTag(PagedPool,
|
|
ListSize,
|
|
TAG_PCI);
|
|
if (ResourceList == NULL)
|
|
return STATUS_INSUFFICIENT_RESOURCES;
|
|
|
|
RtlZeroMemory(ResourceList, ListSize);
|
|
ResourceList->Count = 1;
|
|
ResourceList->List[0].InterfaceType = PCIBus;
|
|
ResourceList->List[0].BusNumber = DeviceExtension->PciDevice->BusNumber;
|
|
|
|
PartialList = &ResourceList->List[0].PartialResourceList;
|
|
PartialList->Version = 1;
|
|
PartialList->Revision = 1;
|
|
PartialList->Count = ResCount;
|
|
|
|
Descriptor = &PartialList->PartialDescriptors[0];
|
|
if (PCI_CONFIGURATION_TYPE(&PciConfig) == PCI_DEVICE_TYPE)
|
|
{
|
|
for (Bar = 0; Bar < PCI_TYPE0_ADDRESSES;)
|
|
{
|
|
if (!PdoGetRangeLength(DeviceExtension,
|
|
Bar,
|
|
&Base,
|
|
&Length,
|
|
&Flags,
|
|
&Bar,
|
|
NULL))
|
|
break;
|
|
|
|
if (Length == 0)
|
|
{
|
|
DPRINT("Unused address register\n");
|
|
continue;
|
|
}
|
|
|
|
if (Flags & PCI_ADDRESS_IO_SPACE)
|
|
{
|
|
Descriptor->Type = CmResourceTypePort;
|
|
Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
|
|
Descriptor->Flags = CM_RESOURCE_PORT_IO |
|
|
CM_RESOURCE_PORT_16_BIT_DECODE |
|
|
CM_RESOURCE_PORT_POSITIVE_DECODE;
|
|
Descriptor->u.Port.Start.QuadPart = (ULONGLONG)Base;
|
|
Descriptor->u.Port.Length = Length;
|
|
|
|
/* Enable IO space access */
|
|
DeviceExtension->PciDevice->EnableIoSpace = TRUE;
|
|
}
|
|
else
|
|
{
|
|
Descriptor->Type = CmResourceTypeMemory;
|
|
Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
|
|
Descriptor->Flags = CM_RESOURCE_MEMORY_READ_WRITE |
|
|
(Flags & PCI_ADDRESS_MEMORY_PREFETCHABLE) ? CM_RESOURCE_MEMORY_PREFETCHABLE : 0;
|
|
Descriptor->u.Memory.Start.QuadPart = (ULONGLONG)Base;
|
|
Descriptor->u.Memory.Length = Length;
|
|
|
|
/* Enable memory space access */
|
|
DeviceExtension->PciDevice->EnableMemorySpace = TRUE;
|
|
}
|
|
|
|
Descriptor++;
|
|
}
|
|
|
|
/* Add interrupt resource */
|
|
if ((PciConfig.u.type0.InterruptPin != 0) &&
|
|
(PciConfig.u.type0.InterruptLine != 0) &&
|
|
(PciConfig.u.type0.InterruptLine != 0xFF))
|
|
{
|
|
Descriptor->Type = CmResourceTypeInterrupt;
|
|
Descriptor->ShareDisposition = CmResourceShareShared;
|
|
Descriptor->Flags = CM_RESOURCE_INTERRUPT_LEVEL_SENSITIVE;
|
|
Descriptor->u.Interrupt.Level = PciConfig.u.type0.InterruptLine;
|
|
Descriptor->u.Interrupt.Vector = PciConfig.u.type0.InterruptLine;
|
|
Descriptor->u.Interrupt.Affinity = 0xFFFFFFFF;
|
|
}
|
|
|
|
/* Allow bus master mode */
|
|
DeviceExtension->PciDevice->EnableBusMaster = TRUE;
|
|
}
|
|
else if (PCI_CONFIGURATION_TYPE(&PciConfig) == PCI_BRIDGE_TYPE)
|
|
{
|
|
for (Bar = 0; Bar < PCI_TYPE1_ADDRESSES;)
|
|
{
|
|
if (!PdoGetRangeLength(DeviceExtension,
|
|
Bar,
|
|
&Base,
|
|
&Length,
|
|
&Flags,
|
|
&Bar,
|
|
NULL))
|
|
break;
|
|
|
|
if (Length == 0)
|
|
{
|
|
DPRINT("Unused address register\n");
|
|
continue;
|
|
}
|
|
|
|
if (Flags & PCI_ADDRESS_IO_SPACE)
|
|
{
|
|
Descriptor->Type = CmResourceTypePort;
|
|
Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
|
|
Descriptor->Flags = CM_RESOURCE_PORT_IO |
|
|
CM_RESOURCE_PORT_16_BIT_DECODE |
|
|
CM_RESOURCE_PORT_POSITIVE_DECODE;
|
|
Descriptor->u.Port.Start.QuadPart = (ULONGLONG)Base;
|
|
Descriptor->u.Port.Length = Length;
|
|
|
|
/* Enable IO space access */
|
|
DeviceExtension->PciDevice->EnableIoSpace = TRUE;
|
|
}
|
|
else
|
|
{
|
|
Descriptor->Type = CmResourceTypeMemory;
|
|
Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
|
|
Descriptor->Flags = CM_RESOURCE_MEMORY_READ_WRITE |
|
|
(Flags & PCI_ADDRESS_MEMORY_PREFETCHABLE) ? CM_RESOURCE_MEMORY_PREFETCHABLE : 0;
|
|
Descriptor->u.Memory.Start.QuadPart = (ULONGLONG)Base;
|
|
Descriptor->u.Memory.Length = Length;
|
|
|
|
/* Enable memory space access */
|
|
DeviceExtension->PciDevice->EnableMemorySpace = TRUE;
|
|
}
|
|
|
|
Descriptor++;
|
|
}
|
|
|
|
if (DeviceExtension->PciDevice->PciConfig.BaseClass == PCI_CLASS_BRIDGE_DEV)
|
|
{
|
|
Descriptor->Type = CmResourceTypeBusNumber;
|
|
Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
|
|
|
|
ResourceList->List[0].BusNumber =
|
|
Descriptor->u.BusNumber.Start = DeviceExtension->PciDevice->PciConfig.u.type1.SecondaryBus;
|
|
Descriptor->u.BusNumber.Length = 1;
|
|
Descriptor->u.BusNumber.Reserved = 0;
|
|
}
|
|
}
|
|
else if (PCI_CONFIGURATION_TYPE(&PciConfig) == PCI_CARDBUS_BRIDGE_TYPE)
|
|
{
|
|
/* FIXME: Add Cardbus bridge resources */
|
|
}
|
|
|
|
Irp->IoStatus.Information = (ULONG_PTR)ResourceList;
|
|
|
|
return STATUS_SUCCESS;
|
|
}
|
|
|
|
|
|
static VOID NTAPI
|
|
InterfaceReference(
|
|
IN PVOID Context)
|
|
{
|
|
PPDO_DEVICE_EXTENSION DeviceExtension;
|
|
|
|
DPRINT("InterfaceReference(%p)\n", Context);
|
|
|
|
DeviceExtension = (PPDO_DEVICE_EXTENSION)((PDEVICE_OBJECT)Context)->DeviceExtension;
|
|
InterlockedIncrement(&DeviceExtension->References);
|
|
}
|
|
|
|
|
|
static VOID NTAPI
|
|
InterfaceDereference(
|
|
IN PVOID Context)
|
|
{
|
|
PPDO_DEVICE_EXTENSION DeviceExtension;
|
|
|
|
DPRINT("InterfaceDereference(%p)\n", Context);
|
|
|
|
DeviceExtension = (PPDO_DEVICE_EXTENSION)((PDEVICE_OBJECT)Context)->DeviceExtension;
|
|
InterlockedDecrement(&DeviceExtension->References);
|
|
}
|
|
|
|
static TRANSLATE_BUS_ADDRESS InterfaceBusTranslateBusAddress;
|
|
|
|
static
|
|
BOOLEAN
|
|
NTAPI
|
|
InterfaceBusTranslateBusAddress(
|
|
IN PVOID Context,
|
|
IN PHYSICAL_ADDRESS BusAddress,
|
|
IN ULONG Length,
|
|
IN OUT PULONG AddressSpace,
|
|
OUT PPHYSICAL_ADDRESS TranslatedAddress)
|
|
{
|
|
PPDO_DEVICE_EXTENSION DeviceExtension;
|
|
|
|
DPRINT("InterfaceBusTranslateBusAddress(%p %p 0x%lx %p %p)\n",
|
|
Context, BusAddress, Length, AddressSpace, TranslatedAddress);
|
|
|
|
DeviceExtension = (PPDO_DEVICE_EXTENSION)((PDEVICE_OBJECT)Context)->DeviceExtension;
|
|
|
|
return HalTranslateBusAddress(PCIBus,
|
|
DeviceExtension->PciDevice->BusNumber,
|
|
BusAddress,
|
|
AddressSpace,
|
|
TranslatedAddress);
|
|
}
|
|
|
|
static GET_DMA_ADAPTER InterfaceBusGetDmaAdapter;
|
|
|
|
static
|
|
PDMA_ADAPTER
|
|
NTAPI
|
|
InterfaceBusGetDmaAdapter(
|
|
IN PVOID Context,
|
|
IN PDEVICE_DESCRIPTION DeviceDescription,
|
|
OUT PULONG NumberOfMapRegisters)
|
|
{
|
|
DPRINT("InterfaceBusGetDmaAdapter(%p %p %p)\n",
|
|
Context, DeviceDescription, NumberOfMapRegisters);
|
|
return (PDMA_ADAPTER)HalGetAdapter(DeviceDescription, NumberOfMapRegisters);
|
|
}
|
|
|
|
static GET_SET_DEVICE_DATA InterfaceBusSetBusData;
|
|
|
|
static
|
|
ULONG
|
|
NTAPI
|
|
InterfaceBusSetBusData(
|
|
IN PVOID Context,
|
|
IN ULONG DataType,
|
|
IN PVOID Buffer,
|
|
IN ULONG Offset,
|
|
IN ULONG Length)
|
|
{
|
|
PPDO_DEVICE_EXTENSION DeviceExtension;
|
|
ULONG Size;
|
|
|
|
DPRINT("InterfaceBusSetBusData(%p 0x%lx %p 0x%lx 0x%lx)\n",
|
|
Context, DataType, Buffer, Offset, Length);
|
|
|
|
if (DataType != PCI_WHICHSPACE_CONFIG)
|
|
{
|
|
DPRINT("Unknown DataType %lu\n", DataType);
|
|
return 0;
|
|
}
|
|
|
|
DeviceExtension = (PPDO_DEVICE_EXTENSION)((PDEVICE_OBJECT)Context)->DeviceExtension;
|
|
|
|
/* Get PCI configuration space */
|
|
Size = HalSetBusDataByOffset(PCIConfiguration,
|
|
DeviceExtension->PciDevice->BusNumber,
|
|
DeviceExtension->PciDevice->SlotNumber.u.AsULONG,
|
|
Buffer,
|
|
Offset,
|
|
Length);
|
|
return Size;
|
|
}
|
|
|
|
static GET_SET_DEVICE_DATA InterfaceBusGetBusData;
|
|
|
|
static
|
|
ULONG
|
|
NTAPI
|
|
InterfaceBusGetBusData(
|
|
IN PVOID Context,
|
|
IN ULONG DataType,
|
|
IN PVOID Buffer,
|
|
IN ULONG Offset,
|
|
IN ULONG Length)
|
|
{
|
|
PPDO_DEVICE_EXTENSION DeviceExtension;
|
|
ULONG Size;
|
|
|
|
DPRINT("InterfaceBusGetBusData(%p 0x%lx %p 0x%lx 0x%lx) called\n",
|
|
Context, DataType, Buffer, Offset, Length);
|
|
|
|
if (DataType != PCI_WHICHSPACE_CONFIG)
|
|
{
|
|
DPRINT("Unknown DataType %lu\n", DataType);
|
|
return 0;
|
|
}
|
|
|
|
DeviceExtension = (PPDO_DEVICE_EXTENSION)((PDEVICE_OBJECT)Context)->DeviceExtension;
|
|
|
|
/* Get PCI configuration space */
|
|
Size = HalGetBusDataByOffset(PCIConfiguration,
|
|
DeviceExtension->PciDevice->BusNumber,
|
|
DeviceExtension->PciDevice->SlotNumber.u.AsULONG,
|
|
Buffer,
|
|
Offset,
|
|
Length);
|
|
return Size;
|
|
}
|
|
|
|
|
|
static BOOLEAN NTAPI
|
|
InterfacePciDevicePresent(
|
|
IN USHORT VendorID,
|
|
IN USHORT DeviceID,
|
|
IN UCHAR RevisionID,
|
|
IN USHORT SubVendorID,
|
|
IN USHORT SubSystemID,
|
|
IN ULONG Flags)
|
|
{
|
|
PFDO_DEVICE_EXTENSION FdoDeviceExtension;
|
|
PPCI_DEVICE PciDevice;
|
|
PLIST_ENTRY CurrentBus, CurrentEntry;
|
|
KIRQL OldIrql;
|
|
BOOLEAN Found = FALSE;
|
|
|
|
KeAcquireSpinLock(&DriverExtension->BusListLock, &OldIrql);
|
|
CurrentBus = DriverExtension->BusListHead.Flink;
|
|
while (!Found && CurrentBus != &DriverExtension->BusListHead)
|
|
{
|
|
FdoDeviceExtension = CONTAINING_RECORD(CurrentBus, FDO_DEVICE_EXTENSION, ListEntry);
|
|
|
|
KeAcquireSpinLockAtDpcLevel(&FdoDeviceExtension->DeviceListLock);
|
|
CurrentEntry = FdoDeviceExtension->DeviceListHead.Flink;
|
|
while (!Found && CurrentEntry != &FdoDeviceExtension->DeviceListHead)
|
|
{
|
|
PciDevice = CONTAINING_RECORD(CurrentEntry, PCI_DEVICE, ListEntry);
|
|
if (PciDevice->PciConfig.VendorID == VendorID &&
|
|
PciDevice->PciConfig.DeviceID == DeviceID)
|
|
{
|
|
if (!(Flags & PCI_USE_SUBSYSTEM_IDS) ||
|
|
(PciDevice->PciConfig.u.type0.SubVendorID == SubVendorID &&
|
|
PciDevice->PciConfig.u.type0.SubSystemID == SubSystemID))
|
|
{
|
|
if (!(Flags & PCI_USE_REVISION) ||
|
|
PciDevice->PciConfig.RevisionID == RevisionID)
|
|
{
|
|
DPRINT("Found the PCI device\n");
|
|
Found = TRUE;
|
|
}
|
|
}
|
|
}
|
|
|
|
CurrentEntry = CurrentEntry->Flink;
|
|
}
|
|
|
|
KeReleaseSpinLockFromDpcLevel(&FdoDeviceExtension->DeviceListLock);
|
|
CurrentBus = CurrentBus->Flink;
|
|
}
|
|
KeReleaseSpinLock(&DriverExtension->BusListLock, OldIrql);
|
|
|
|
return Found;
|
|
}
|
|
|
|
|
|
static BOOLEAN
|
|
CheckPciDevice(
|
|
IN PPCI_COMMON_CONFIG PciConfig,
|
|
IN PPCI_DEVICE_PRESENCE_PARAMETERS Parameters)
|
|
{
|
|
if ((Parameters->Flags & PCI_USE_VENDEV_IDS) &&
|
|
(PciConfig->VendorID != Parameters->VendorID ||
|
|
PciConfig->DeviceID != Parameters->DeviceID))
|
|
{
|
|
return FALSE;
|
|
}
|
|
|
|
if ((Parameters->Flags & PCI_USE_CLASS_SUBCLASS) &&
|
|
(PciConfig->BaseClass != Parameters->BaseClass ||
|
|
PciConfig->SubClass != Parameters->SubClass))
|
|
{
|
|
return FALSE;
|
|
}
|
|
|
|
if ((Parameters->Flags & PCI_USE_PROGIF) &&
|
|
PciConfig->ProgIf != Parameters->ProgIf)
|
|
{
|
|
return FALSE;
|
|
}
|
|
|
|
if ((Parameters->Flags & PCI_USE_SUBSYSTEM_IDS) &&
|
|
(PciConfig->u.type0.SubVendorID != Parameters->SubVendorID ||
|
|
PciConfig->u.type0.SubSystemID != Parameters->SubSystemID))
|
|
{
|
|
return FALSE;
|
|
}
|
|
|
|
if ((Parameters->Flags & PCI_USE_REVISION) &&
|
|
PciConfig->RevisionID != Parameters->RevisionID)
|
|
{
|
|
return FALSE;
|
|
}
|
|
|
|
return TRUE;
|
|
}
|
|
|
|
|
|
static BOOLEAN NTAPI
|
|
InterfacePciDevicePresentEx(
|
|
IN PVOID Context,
|
|
IN PPCI_DEVICE_PRESENCE_PARAMETERS Parameters)
|
|
{
|
|
PPDO_DEVICE_EXTENSION DeviceExtension;
|
|
PFDO_DEVICE_EXTENSION MyFdoDeviceExtension;
|
|
PFDO_DEVICE_EXTENSION FdoDeviceExtension;
|
|
PPCI_DEVICE PciDevice;
|
|
PLIST_ENTRY CurrentBus, CurrentEntry;
|
|
KIRQL OldIrql;
|
|
BOOLEAN Found = FALSE;
|
|
|
|
DPRINT("InterfacePciDevicePresentEx(%p %p) called\n",
|
|
Context, Parameters);
|
|
|
|
if (!Parameters || Parameters->Size != sizeof(PCI_DEVICE_PRESENCE_PARAMETERS))
|
|
return FALSE;
|
|
|
|
DeviceExtension = (PPDO_DEVICE_EXTENSION)((PDEVICE_OBJECT)Context)->DeviceExtension;
|
|
MyFdoDeviceExtension = (PFDO_DEVICE_EXTENSION)DeviceExtension->Fdo->DeviceExtension;
|
|
|
|
if (Parameters->Flags & PCI_USE_LOCAL_DEVICE)
|
|
{
|
|
return CheckPciDevice(&DeviceExtension->PciDevice->PciConfig, Parameters);
|
|
}
|
|
|
|
KeAcquireSpinLock(&DriverExtension->BusListLock, &OldIrql);
|
|
CurrentBus = DriverExtension->BusListHead.Flink;
|
|
while (!Found && CurrentBus != &DriverExtension->BusListHead)
|
|
{
|
|
FdoDeviceExtension = CONTAINING_RECORD(CurrentBus, FDO_DEVICE_EXTENSION, ListEntry);
|
|
if (!(Parameters->Flags & PCI_USE_LOCAL_BUS) || FdoDeviceExtension == MyFdoDeviceExtension)
|
|
{
|
|
KeAcquireSpinLockAtDpcLevel(&FdoDeviceExtension->DeviceListLock);
|
|
CurrentEntry = FdoDeviceExtension->DeviceListHead.Flink;
|
|
while (!Found && CurrentEntry != &FdoDeviceExtension->DeviceListHead)
|
|
{
|
|
PciDevice = CONTAINING_RECORD(CurrentEntry, PCI_DEVICE, ListEntry);
|
|
|
|
if (CheckPciDevice(&PciDevice->PciConfig, Parameters))
|
|
{
|
|
DPRINT("Found the PCI device\n");
|
|
Found = TRUE;
|
|
}
|
|
|
|
CurrentEntry = CurrentEntry->Flink;
|
|
}
|
|
|
|
KeReleaseSpinLockFromDpcLevel(&FdoDeviceExtension->DeviceListLock);
|
|
}
|
|
CurrentBus = CurrentBus->Flink;
|
|
}
|
|
KeReleaseSpinLock(&DriverExtension->BusListLock, OldIrql);
|
|
|
|
return Found;
|
|
}
|
|
|
|
|
|
static NTSTATUS
|
|
PdoQueryInterface(
|
|
IN PDEVICE_OBJECT DeviceObject,
|
|
IN PIRP Irp,
|
|
PIO_STACK_LOCATION IrpSp)
|
|
{
|
|
NTSTATUS Status;
|
|
|
|
UNREFERENCED_PARAMETER(Irp);
|
|
|
|
if (RtlCompareMemory(IrpSp->Parameters.QueryInterface.InterfaceType,
|
|
&GUID_BUS_INTERFACE_STANDARD, sizeof(GUID)) == sizeof(GUID))
|
|
{
|
|
/* BUS_INTERFACE_STANDARD */
|
|
if (IrpSp->Parameters.QueryInterface.Version < 1)
|
|
Status = STATUS_NOT_SUPPORTED;
|
|
else if (IrpSp->Parameters.QueryInterface.Size < sizeof(BUS_INTERFACE_STANDARD))
|
|
Status = STATUS_BUFFER_TOO_SMALL;
|
|
else
|
|
{
|
|
PBUS_INTERFACE_STANDARD BusInterface;
|
|
BusInterface = (PBUS_INTERFACE_STANDARD)IrpSp->Parameters.QueryInterface.Interface;
|
|
BusInterface->Size = sizeof(BUS_INTERFACE_STANDARD);
|
|
BusInterface->Version = 1;
|
|
BusInterface->TranslateBusAddress = InterfaceBusTranslateBusAddress;
|
|
BusInterface->GetDmaAdapter = InterfaceBusGetDmaAdapter;
|
|
BusInterface->SetBusData = InterfaceBusSetBusData;
|
|
BusInterface->GetBusData = InterfaceBusGetBusData;
|
|
Status = STATUS_SUCCESS;
|
|
}
|
|
}
|
|
else if (RtlCompareMemory(IrpSp->Parameters.QueryInterface.InterfaceType,
|
|
&GUID_PCI_DEVICE_PRESENT_INTERFACE, sizeof(GUID)) == sizeof(GUID))
|
|
{
|
|
/* PCI_DEVICE_PRESENT_INTERFACE */
|
|
if (IrpSp->Parameters.QueryInterface.Version < 1)
|
|
Status = STATUS_NOT_SUPPORTED;
|
|
else if (IrpSp->Parameters.QueryInterface.Size < sizeof(PCI_DEVICE_PRESENT_INTERFACE))
|
|
Status = STATUS_BUFFER_TOO_SMALL;
|
|
else
|
|
{
|
|
PPCI_DEVICE_PRESENT_INTERFACE PciDevicePresentInterface;
|
|
PciDevicePresentInterface = (PPCI_DEVICE_PRESENT_INTERFACE)IrpSp->Parameters.QueryInterface.Interface;
|
|
PciDevicePresentInterface->Size = sizeof(PCI_DEVICE_PRESENT_INTERFACE);
|
|
PciDevicePresentInterface->Version = 1;
|
|
PciDevicePresentInterface->IsDevicePresent = InterfacePciDevicePresent;
|
|
PciDevicePresentInterface->IsDevicePresentEx = InterfacePciDevicePresentEx;
|
|
Status = STATUS_SUCCESS;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Not a supported interface */
|
|
return STATUS_NOT_SUPPORTED;
|
|
}
|
|
|
|
if (NT_SUCCESS(Status))
|
|
{
|
|
/* Add a reference for the returned interface */
|
|
PINTERFACE Interface;
|
|
Interface = (PINTERFACE)IrpSp->Parameters.QueryInterface.Interface;
|
|
Interface->Context = DeviceObject;
|
|
Interface->InterfaceReference = InterfaceReference;
|
|
Interface->InterfaceDereference = InterfaceDereference;
|
|
Interface->InterfaceReference(Interface->Context);
|
|
}
|
|
|
|
return Status;
|
|
}
|
|
|
|
static NTSTATUS
|
|
PdoStartDevice(
|
|
IN PDEVICE_OBJECT DeviceObject,
|
|
IN PIRP Irp,
|
|
PIO_STACK_LOCATION IrpSp)
|
|
{
|
|
PCM_RESOURCE_LIST RawResList = IrpSp->Parameters.StartDevice.AllocatedResources;
|
|
PCM_FULL_RESOURCE_DESCRIPTOR RawFullDesc;
|
|
PCM_PARTIAL_RESOURCE_DESCRIPTOR RawPartialDesc;
|
|
ULONG i, ii;
|
|
PPDO_DEVICE_EXTENSION DeviceExtension = DeviceObject->DeviceExtension;
|
|
UCHAR Irq;
|
|
USHORT Command;
|
|
|
|
UNREFERENCED_PARAMETER(Irp);
|
|
|
|
if (!RawResList)
|
|
return STATUS_SUCCESS;
|
|
|
|
/* TODO: Assign the other resources we get to the card */
|
|
|
|
RawFullDesc = &RawResList->List[0];
|
|
for (i = 0; i < RawResList->Count; i++, RawFullDesc = CmiGetNextResourceDescriptor(RawFullDesc))
|
|
{
|
|
for (ii = 0; ii < RawFullDesc->PartialResourceList.Count; ii++)
|
|
{
|
|
/* Partial resource descriptors can be of variable size (CmResourceTypeDeviceSpecific),
|
|
but only one is allowed and it must be the last one in the list! */
|
|
RawPartialDesc = &RawFullDesc->PartialResourceList.PartialDescriptors[ii];
|
|
|
|
if (RawPartialDesc->Type == CmResourceTypeInterrupt)
|
|
{
|
|
DPRINT("Assigning IRQ %u to PCI device 0x%x on bus 0x%x\n",
|
|
RawPartialDesc->u.Interrupt.Vector,
|
|
DeviceExtension->PciDevice->SlotNumber.u.AsULONG,
|
|
DeviceExtension->PciDevice->BusNumber);
|
|
|
|
Irq = (UCHAR)RawPartialDesc->u.Interrupt.Vector;
|
|
HalSetBusDataByOffset(PCIConfiguration,
|
|
DeviceExtension->PciDevice->BusNumber,
|
|
DeviceExtension->PciDevice->SlotNumber.u.AsULONG,
|
|
&Irq,
|
|
0x3c /* PCI_INTERRUPT_LINE */,
|
|
sizeof(UCHAR));
|
|
}
|
|
}
|
|
}
|
|
|
|
Command = 0;
|
|
|
|
DBGPRINT("pci!PdoStartDevice: Enabling command flags for PCI device 0x%x on bus 0x%x: ",
|
|
DeviceExtension->PciDevice->SlotNumber.u.AsULONG,
|
|
DeviceExtension->PciDevice->BusNumber);
|
|
if (DeviceExtension->PciDevice->EnableBusMaster)
|
|
{
|
|
Command |= PCI_ENABLE_BUS_MASTER;
|
|
DBGPRINT("[Bus master] ");
|
|
}
|
|
|
|
if (DeviceExtension->PciDevice->EnableMemorySpace)
|
|
{
|
|
Command |= PCI_ENABLE_MEMORY_SPACE;
|
|
DBGPRINT("[Memory space enable] ");
|
|
}
|
|
|
|
if (DeviceExtension->PciDevice->EnableIoSpace)
|
|
{
|
|
Command |= PCI_ENABLE_IO_SPACE;
|
|
DBGPRINT("[I/O space enable] ");
|
|
}
|
|
|
|
if (Command != 0)
|
|
{
|
|
DBGPRINT("\n");
|
|
|
|
/* OR with the previous value */
|
|
Command |= DeviceExtension->PciDevice->PciConfig.Command;
|
|
|
|
HalSetBusDataByOffset(PCIConfiguration,
|
|
DeviceExtension->PciDevice->BusNumber,
|
|
DeviceExtension->PciDevice->SlotNumber.u.AsULONG,
|
|
&Command,
|
|
FIELD_OFFSET(PCI_COMMON_CONFIG, Command),
|
|
sizeof(USHORT));
|
|
}
|
|
else
|
|
{
|
|
DBGPRINT("None\n");
|
|
}
|
|
|
|
return STATUS_SUCCESS;
|
|
}
|
|
|
|
static NTSTATUS
|
|
PdoReadConfig(
|
|
IN PDEVICE_OBJECT DeviceObject,
|
|
IN PIRP Irp,
|
|
PIO_STACK_LOCATION IrpSp)
|
|
{
|
|
ULONG Size;
|
|
|
|
DPRINT("PdoReadConfig() called\n");
|
|
|
|
Size = InterfaceBusGetBusData(DeviceObject,
|
|
IrpSp->Parameters.ReadWriteConfig.WhichSpace,
|
|
IrpSp->Parameters.ReadWriteConfig.Buffer,
|
|
IrpSp->Parameters.ReadWriteConfig.Offset,
|
|
IrpSp->Parameters.ReadWriteConfig.Length);
|
|
|
|
if (Size != IrpSp->Parameters.ReadWriteConfig.Length)
|
|
{
|
|
DPRINT1("Size %lu Length %lu\n", Size, IrpSp->Parameters.ReadWriteConfig.Length);
|
|
Irp->IoStatus.Information = 0;
|
|
return STATUS_UNSUCCESSFUL;
|
|
}
|
|
|
|
Irp->IoStatus.Information = Size;
|
|
|
|
return STATUS_SUCCESS;
|
|
}
|
|
|
|
|
|
static NTSTATUS
|
|
PdoWriteConfig(
|
|
IN PDEVICE_OBJECT DeviceObject,
|
|
IN PIRP Irp,
|
|
PIO_STACK_LOCATION IrpSp)
|
|
{
|
|
ULONG Size;
|
|
|
|
DPRINT1("PdoWriteConfig() called\n");
|
|
|
|
/* Get PCI configuration space */
|
|
Size = InterfaceBusSetBusData(DeviceObject,
|
|
IrpSp->Parameters.ReadWriteConfig.WhichSpace,
|
|
IrpSp->Parameters.ReadWriteConfig.Buffer,
|
|
IrpSp->Parameters.ReadWriteConfig.Offset,
|
|
IrpSp->Parameters.ReadWriteConfig.Length);
|
|
|
|
if (Size != IrpSp->Parameters.ReadWriteConfig.Length)
|
|
{
|
|
DPRINT1("Size %lu Length %lu\n", Size, IrpSp->Parameters.ReadWriteConfig.Length);
|
|
Irp->IoStatus.Information = 0;
|
|
return STATUS_UNSUCCESSFUL;
|
|
}
|
|
|
|
Irp->IoStatus.Information = Size;
|
|
|
|
return STATUS_SUCCESS;
|
|
}
|
|
|
|
static NTSTATUS
|
|
PdoQueryDeviceRelations(
|
|
IN PDEVICE_OBJECT DeviceObject,
|
|
IN PIRP Irp,
|
|
PIO_STACK_LOCATION IrpSp)
|
|
{
|
|
PDEVICE_RELATIONS DeviceRelations;
|
|
|
|
/* We only support TargetDeviceRelation for child PDOs */
|
|
if (IrpSp->Parameters.QueryDeviceRelations.Type != TargetDeviceRelation)
|
|
return Irp->IoStatus.Status;
|
|
|
|
/* We can do this because we only return 1 PDO for TargetDeviceRelation */
|
|
DeviceRelations = ExAllocatePoolWithTag(PagedPool, sizeof(*DeviceRelations), TAG_PCI);
|
|
if (!DeviceRelations)
|
|
return STATUS_INSUFFICIENT_RESOURCES;
|
|
|
|
DeviceRelations->Count = 1;
|
|
DeviceRelations->Objects[0] = DeviceObject;
|
|
|
|
/* The PnP manager will remove this when it is done with the PDO */
|
|
ObReferenceObject(DeviceObject);
|
|
|
|
Irp->IoStatus.Information = (ULONG_PTR)DeviceRelations;
|
|
|
|
return STATUS_SUCCESS;
|
|
}
|
|
|
|
|
|
/*** PUBLIC ******************************************************************/
|
|
|
|
NTSTATUS
|
|
PdoPnpControl(
|
|
PDEVICE_OBJECT DeviceObject,
|
|
PIRP Irp)
|
|
/*
|
|
* FUNCTION: Handle Plug and Play IRPs for the child device
|
|
* ARGUMENTS:
|
|
* DeviceObject = Pointer to physical device object of the child device
|
|
* Irp = Pointer to IRP that should be handled
|
|
* RETURNS:
|
|
* Status
|
|
*/
|
|
{
|
|
PIO_STACK_LOCATION IrpSp;
|
|
NTSTATUS Status;
|
|
|
|
DPRINT("Called\n");
|
|
|
|
Status = Irp->IoStatus.Status;
|
|
|
|
IrpSp = IoGetCurrentIrpStackLocation(Irp);
|
|
|
|
switch (IrpSp->MinorFunction)
|
|
{
|
|
case IRP_MN_DEVICE_USAGE_NOTIFICATION:
|
|
DPRINT("Unimplemented IRP_MN_DEVICE_USAGE_NOTIFICATION received\n");
|
|
break;
|
|
|
|
case IRP_MN_EJECT:
|
|
DPRINT("Unimplemented IRP_MN_EJECT received\n");
|
|
break;
|
|
|
|
case IRP_MN_QUERY_BUS_INFORMATION:
|
|
Status = PdoQueryBusInformation(DeviceObject, Irp, IrpSp);
|
|
break;
|
|
|
|
case IRP_MN_QUERY_CAPABILITIES:
|
|
Status = PdoQueryCapabilities(DeviceObject, Irp, IrpSp);
|
|
break;
|
|
|
|
case IRP_MN_QUERY_DEVICE_RELATIONS:
|
|
Status = PdoQueryDeviceRelations(DeviceObject, Irp, IrpSp);
|
|
break;
|
|
|
|
case IRP_MN_QUERY_DEVICE_TEXT:
|
|
DPRINT("IRP_MN_QUERY_DEVICE_TEXT received\n");
|
|
Status = PdoQueryDeviceText(DeviceObject, Irp, IrpSp);
|
|
break;
|
|
|
|
case IRP_MN_QUERY_ID:
|
|
DPRINT("IRP_MN_QUERY_ID received\n");
|
|
Status = PdoQueryId(DeviceObject, Irp, IrpSp);
|
|
break;
|
|
|
|
case IRP_MN_QUERY_PNP_DEVICE_STATE:
|
|
DPRINT("Unimplemented IRP_MN_QUERY_ID received\n");
|
|
break;
|
|
|
|
case IRP_MN_QUERY_RESOURCE_REQUIREMENTS:
|
|
DPRINT("IRP_MN_QUERY_RESOURCE_REQUIREMENTS received\n");
|
|
Status = PdoQueryResourceRequirements(DeviceObject, Irp, IrpSp);
|
|
break;
|
|
|
|
case IRP_MN_QUERY_RESOURCES:
|
|
DPRINT("IRP_MN_QUERY_RESOURCES received\n");
|
|
Status = PdoQueryResources(DeviceObject, Irp, IrpSp);
|
|
break;
|
|
|
|
case IRP_MN_SET_LOCK:
|
|
DPRINT("Unimplemented IRP_MN_SET_LOCK received\n");
|
|
break;
|
|
|
|
case IRP_MN_START_DEVICE:
|
|
Status = PdoStartDevice(DeviceObject, Irp, IrpSp);
|
|
break;
|
|
|
|
case IRP_MN_QUERY_STOP_DEVICE:
|
|
case IRP_MN_CANCEL_STOP_DEVICE:
|
|
case IRP_MN_STOP_DEVICE:
|
|
case IRP_MN_QUERY_REMOVE_DEVICE:
|
|
case IRP_MN_CANCEL_REMOVE_DEVICE:
|
|
case IRP_MN_REMOVE_DEVICE:
|
|
case IRP_MN_SURPRISE_REMOVAL:
|
|
Status = STATUS_SUCCESS;
|
|
break;
|
|
|
|
case IRP_MN_QUERY_INTERFACE:
|
|
DPRINT("IRP_MN_QUERY_INTERFACE received\n");
|
|
Status = PdoQueryInterface(DeviceObject, Irp, IrpSp);
|
|
break;
|
|
|
|
case IRP_MN_READ_CONFIG:
|
|
DPRINT("IRP_MN_READ_CONFIG received\n");
|
|
Status = PdoReadConfig(DeviceObject, Irp, IrpSp);
|
|
break;
|
|
|
|
case IRP_MN_WRITE_CONFIG:
|
|
DPRINT("IRP_MN_WRITE_CONFIG received\n");
|
|
Status = PdoWriteConfig(DeviceObject, Irp, IrpSp);
|
|
break;
|
|
|
|
case IRP_MN_FILTER_RESOURCE_REQUIREMENTS:
|
|
DPRINT("IRP_MN_FILTER_RESOURCE_REQUIREMENTS received\n");
|
|
/* Nothing to do */
|
|
Irp->IoStatus.Status = Status;
|
|
break;
|
|
|
|
default:
|
|
DPRINT1("Unknown IOCTL 0x%lx\n", IrpSp->MinorFunction);
|
|
break;
|
|
}
|
|
|
|
if (Status != STATUS_PENDING)
|
|
{
|
|
Irp->IoStatus.Status = Status;
|
|
IoCompleteRequest(Irp, IO_NO_INCREMENT);
|
|
}
|
|
|
|
DPRINT("Leaving. Status 0x%X\n", Status);
|
|
|
|
return Status;
|
|
}
|
|
|
|
NTSTATUS
|
|
PdoPowerControl(
|
|
PDEVICE_OBJECT DeviceObject,
|
|
PIRP Irp)
|
|
/*
|
|
* FUNCTION: Handle power management IRPs for the child device
|
|
* ARGUMENTS:
|
|
* DeviceObject = Pointer to physical device object of the child device
|
|
* Irp = Pointer to IRP that should be handled
|
|
* RETURNS:
|
|
* Status
|
|
*/
|
|
{
|
|
PIO_STACK_LOCATION IrpSp;
|
|
NTSTATUS Status = Irp->IoStatus.Status;
|
|
|
|
DPRINT("Called\n");
|
|
|
|
IrpSp = IoGetCurrentIrpStackLocation(Irp);
|
|
|
|
switch (IrpSp->MinorFunction)
|
|
{
|
|
case IRP_MN_QUERY_POWER:
|
|
case IRP_MN_SET_POWER:
|
|
Status = STATUS_SUCCESS;
|
|
break;
|
|
}
|
|
|
|
PoStartNextPowerIrp(Irp);
|
|
Irp->IoStatus.Status = Status;
|
|
IoCompleteRequest(Irp, IO_NO_INCREMENT);
|
|
|
|
DPRINT("Leaving. Status 0x%X\n", Status);
|
|
|
|
return Status;
|
|
}
|
|
|
|
/* EOF */
|