mirror of
https://github.com/reactos/reactos.git
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965 lines
22 KiB
C
965 lines
22 KiB
C
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/*******************************************************************************
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*
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* Module Name: hwregs - Read/write access functions for the various ACPI
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* control and status registers.
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* $Revision: 1.1 $
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*
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******************************************************************************/
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/*
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* Copyright (C) 2000, 2001 R. Byron Moore
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <acpi.h>
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#define _COMPONENT ACPI_HARDWARE
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MODULE_NAME ("hwregs")
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/* This matches the #defines in actypes.h. */
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NATIVE_CHAR *sleep_state_table[] = {"\\_S0_","\\_S1_","\\_S2_","\\_S3_",
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"\\_S4_","\\_S5_","\\_S4_b"};
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/*******************************************************************************
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*
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* FUNCTION: Acpi_hw_get_bit_shift
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*
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* PARAMETERS: Mask - Input mask to determine bit shift from.
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* Must have at least 1 bit set.
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*
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* RETURN: Bit location of the lsb of the mask
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*
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* DESCRIPTION: Returns the bit number for the low order bit that's set.
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*
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******************************************************************************/
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u32
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acpi_hw_get_bit_shift (
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u32 mask) {
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u32 shift;
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for (shift = 0; ((mask >> shift) & 1) == 0; shift++) { ; }
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return (shift);
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}
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/*******************************************************************************
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*
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* FUNCTION: Acpi_hw_clear_acpi_status
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*
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* PARAMETERS: none
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*
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* RETURN: none
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*
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* DESCRIPTION: Clears all fixed and general purpose status bits
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*
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******************************************************************************/
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void
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acpi_hw_clear_acpi_status (void)
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{
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u16 gpe_length;
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u16 index;
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acpi_cm_acquire_mutex (ACPI_MTX_HARDWARE);
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acpi_hw_register_write (ACPI_MTX_DO_NOT_LOCK, PM1_STS, ALL_FIXED_STS_BITS);
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if (ACPI_VALID_ADDRESS (acpi_gbl_FADT->Xpm1b_evt_blk.address)) {
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acpi_os_out16 ((ACPI_IO_ADDRESS) ACPI_GET_ADDRESS (acpi_gbl_FADT->Xpm1b_evt_blk.address),
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(u16) ALL_FIXED_STS_BITS);
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}
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/* now clear the GPE Bits */
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if (acpi_gbl_FADT->gpe0blk_len) {
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gpe_length = (u16) DIV_2 (acpi_gbl_FADT->gpe0blk_len);
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for (index = 0; index < gpe_length; index++) {
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acpi_os_out8 ((ACPI_IO_ADDRESS) (ACPI_GET_ADDRESS (acpi_gbl_FADT->Xgpe0blk.address) + index),
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(u8) 0xff);
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}
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}
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if (acpi_gbl_FADT->gpe1_blk_len) {
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gpe_length = (u16) DIV_2 (acpi_gbl_FADT->gpe1_blk_len);
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for (index = 0; index < gpe_length; index++) {
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acpi_os_out8 ((ACPI_IO_ADDRESS) (ACPI_GET_ADDRESS (acpi_gbl_FADT->Xgpe1_blk.address) + index),
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(u8) 0xff);
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}
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}
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acpi_cm_release_mutex (ACPI_MTX_HARDWARE);
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return;
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}
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/*******************************************************************************
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*
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* FUNCTION: Acpi_hw_obtain_sleep_type_register_data
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*
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* PARAMETERS: Sleep_state - Numeric state requested
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* *Slp_Typ_a - Pointer to byte to receive SLP_TYPa value
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* *Slp_Typ_b - Pointer to byte to receive SLP_TYPb value
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*
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* RETURN: Status - ACPI status
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*
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* DESCRIPTION: Acpi_hw_obtain_sleep_type_register_data() obtains the SLP_TYP and
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* SLP_TYPb values for the sleep state requested.
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*
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******************************************************************************/
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ACPI_STATUS
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acpi_hw_obtain_sleep_type_register_data (
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u8 sleep_state,
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u8 *slp_typ_a,
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u8 *slp_typ_b)
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{
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ACPI_STATUS status = AE_OK;
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ACPI_OPERAND_OBJECT *obj_desc;
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/*
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* Validate parameters
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*/
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if ((sleep_state > ACPI_S_STATES_MAX) ||
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!slp_typ_a || !slp_typ_b) {
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return (AE_BAD_PARAMETER);
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}
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/*
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* Acpi_evaluate the namespace object containing the values for this state
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*/
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status = acpi_ns_evaluate_by_name (sleep_state_table[sleep_state], NULL, &obj_desc);
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if (ACPI_FAILURE (status)) {
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return (status);
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}
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if (!obj_desc) {
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REPORT_ERROR (("Missing Sleep State object\n"));
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return (AE_NOT_EXIST);
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}
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/*
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* We got something, now ensure it is correct. The object must
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* be a package and must have at least 2 numeric values as the
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* two elements
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*/
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/* Even though Acpi_evaluate_object resolves package references,
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* Ns_evaluate dpesn't. So, we do it here.
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*/
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status = acpi_cm_resolve_package_references(obj_desc);
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if (obj_desc->package.count < 2) {
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/* Must have at least two elements */
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REPORT_ERROR (("Sleep State package does not have at least two elements\n"));
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status = AE_ERROR;
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}
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else if (((obj_desc->package.elements[0])->common.type !=
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ACPI_TYPE_INTEGER) ||
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((obj_desc->package.elements[1])->common.type !=
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ACPI_TYPE_INTEGER)) {
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/* Must have two */
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REPORT_ERROR (("Sleep State package elements are not both of type Number\n"));
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status = AE_ERROR;
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}
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else {
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/*
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* Valid _Sx_ package size, type, and value
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*/
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*slp_typ_a = (u8) (obj_desc->package.elements[0])->integer.value;
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*slp_typ_b = (u8) (obj_desc->package.elements[1])->integer.value;
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}
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acpi_cm_remove_reference (obj_desc);
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return (status);
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}
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/*******************************************************************************
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*
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* FUNCTION: Acpi_hw_register_bit_access
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*
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* PARAMETERS: Read_write - Either ACPI_READ or ACPI_WRITE.
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* Use_lock - Lock the hardware
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* Register_id - index of ACPI Register to access
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* Value - (only used on write) value to write to the
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* Register. Shifted all the way right.
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*
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* RETURN: Value written to or read from specified Register. This value
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* is shifted all the way right.
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*
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* DESCRIPTION: Generic ACPI Register read/write function.
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*
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******************************************************************************/
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u32
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acpi_hw_register_bit_access (
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NATIVE_UINT read_write,
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u8 use_lock,
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u32 register_id,
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...) /* Value (only used on write) */
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{
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u32 register_value = 0;
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u32 mask = 0;
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u32 value = 0;
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if (read_write == ACPI_WRITE) {
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va_list marker;
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va_start (marker, register_id);
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value = va_arg (marker, u32);
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va_end (marker);
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}
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if (ACPI_MTX_LOCK == use_lock) {
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acpi_cm_acquire_mutex (ACPI_MTX_HARDWARE);
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}
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/*
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* Decode the Register ID
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* Register id = Register block id | bit id
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*
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* Check bit id to fine locate Register offset.
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* check Mask to determine Register offset, and then read-write.
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*/
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switch (REGISTER_BLOCK_ID(register_id)) {
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case PM1_STS:
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switch (register_id) {
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case TMR_STS:
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mask = TMR_STS_MASK;
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break;
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case BM_STS:
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mask = BM_STS_MASK;
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break;
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case GBL_STS:
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mask = GBL_STS_MASK;
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break;
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case PWRBTN_STS:
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mask = PWRBTN_STS_MASK;
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break;
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case SLPBTN_STS:
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mask = SLPBTN_STS_MASK;
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break;
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case RTC_STS:
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mask = RTC_STS_MASK;
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break;
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case WAK_STS:
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mask = WAK_STS_MASK;
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break;
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default:
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mask = 0;
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break;
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}
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register_value = acpi_hw_register_read (ACPI_MTX_DO_NOT_LOCK, PM1_STS);
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if (read_write == ACPI_WRITE) {
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/*
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* Status Registers are different from the rest. Clear by
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* writing 1, writing 0 has no effect. So, the only relevent
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* information is the single bit we're interested in, all
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* others should be written as 0 so they will be left
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* unchanged
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*/
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value <<= acpi_hw_get_bit_shift (mask);
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value &= mask;
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if (value) {
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acpi_hw_register_write (ACPI_MTX_DO_NOT_LOCK, PM1_STS, (u16) value);
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register_value = 0;
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}
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}
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break;
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case PM1_EN:
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switch (register_id) {
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case TMR_EN:
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mask = TMR_EN_MASK;
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break;
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case GBL_EN:
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mask = GBL_EN_MASK;
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break;
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case PWRBTN_EN:
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mask = PWRBTN_EN_MASK;
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break;
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case SLPBTN_EN:
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mask = SLPBTN_EN_MASK;
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break;
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case RTC_EN:
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mask = RTC_EN_MASK;
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break;
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default:
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mask = 0;
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break;
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}
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register_value = acpi_hw_register_read (ACPI_MTX_DO_NOT_LOCK, PM1_EN);
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if (read_write == ACPI_WRITE) {
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register_value &= ~mask;
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value <<= acpi_hw_get_bit_shift (mask);
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value &= mask;
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register_value |= value;
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acpi_hw_register_write (ACPI_MTX_DO_NOT_LOCK, PM1_EN, (u16) register_value);
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}
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break;
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case PM1_CONTROL:
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switch (register_id) {
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case SCI_EN:
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mask = SCI_EN_MASK;
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break;
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case BM_RLD:
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mask = BM_RLD_MASK;
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break;
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case GBL_RLS:
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mask = GBL_RLS_MASK;
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break;
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case SLP_TYPE_A:
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case SLP_TYPE_B:
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mask = SLP_TYPE_X_MASK;
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break;
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case SLP_EN:
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mask = SLP_EN_MASK;
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break;
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default:
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mask = 0;
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break;
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}
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/*
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* Read the PM1 Control register.
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* Note that at this level, the fact that there are actually TWO
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* registers (A and B) and that B may not exist, are abstracted.
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*/
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register_value = acpi_hw_register_read (ACPI_MTX_DO_NOT_LOCK, PM1_CONTROL);
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if (read_write == ACPI_WRITE) {
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register_value &= ~mask;
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value <<= acpi_hw_get_bit_shift (mask);
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value &= mask;
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register_value |= value;
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/*
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* SLP_TYPE_x Registers are written differently
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* than any other control Registers with
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* respect to A and B Registers. The value
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* for A may be different than the value for B
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*
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* Therefore, pass the Register_id, not just generic PM1_CONTROL,
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* because we need to do different things. Yuck.
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*/
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acpi_hw_register_write (ACPI_MTX_DO_NOT_LOCK,
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register_id, (u16) register_value);
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}
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break;
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case PM2_CONTROL:
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switch (register_id) {
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case ARB_DIS:
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mask = ARB_DIS_MASK;
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break;
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default:
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mask = 0;
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break;
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}
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register_value = acpi_hw_register_read (ACPI_MTX_DO_NOT_LOCK, PM2_CONTROL);
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if (read_write == ACPI_WRITE) {
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register_value &= ~mask;
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value <<= acpi_hw_get_bit_shift (mask);
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value &= mask;
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register_value |= value;
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acpi_hw_register_write (ACPI_MTX_DO_NOT_LOCK,
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PM2_CONTROL, (u8) (register_value));
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}
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break;
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case PM_TIMER:
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mask = TMR_VAL_MASK;
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register_value = acpi_hw_register_read (ACPI_MTX_DO_NOT_LOCK,
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PM_TIMER);
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break;
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case GPE1_EN_BLOCK:
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case GPE1_STS_BLOCK:
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case GPE0_EN_BLOCK:
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case GPE0_STS_BLOCK:
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/* Determine the bit to be accessed
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*
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* (u32) Register_id:
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* 31 24 16 8 0
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* +--------+--------+--------+--------+
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* | gpe_block_id | gpe_bit_number |
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* +--------+--------+--------+--------+
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*
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* gpe_block_id is one of GPE[01]_EN_BLOCK and GPE[01]_STS_BLOCK
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* gpe_bit_number is relative from the gpe_block (0x00~0xFF)
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*/
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mask = REGISTER_BIT_ID(register_id); /* gpe_bit_number */
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register_id = REGISTER_BLOCK_ID(register_id) | (mask >> 3);
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mask = acpi_gbl_decode_to8bit [mask % 8];
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/*
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* The base address of the GPE 0 Register Block
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* Plus 1/2 the length of the GPE 0 Register Block
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* The enable Register is the Register following the Status Register
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* and each Register is defined as 1/2 of the total Register Block
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*/
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/*
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* This sets the bit within Enable_bit that needs to be written to
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* the Register indicated in Mask to a 1, all others are 0
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*/
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/* Now get the current Enable Bits in the selected Reg */
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register_value = acpi_hw_register_read (ACPI_MTX_DO_NOT_LOCK, register_id);
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if (read_write == ACPI_WRITE) {
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register_value &= ~mask;
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value <<= acpi_hw_get_bit_shift (mask);
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value &= mask;
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register_value |= value;
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/* This write will put the Action state into the General Purpose */
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/* Enable Register indexed by the value in Mask */
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acpi_hw_register_write (ACPI_MTX_DO_NOT_LOCK,
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register_id, (u8) register_value);
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register_value = acpi_hw_register_read (ACPI_MTX_DO_NOT_LOCK, register_id);
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}
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break;
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|
|
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case SMI_CMD_BLOCK:
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case PROCESSOR_BLOCK:
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/* not used */
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default:
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mask = 0;
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break;
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}
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if (ACPI_MTX_LOCK == use_lock) {
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acpi_cm_release_mutex (ACPI_MTX_HARDWARE);
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}
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|
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register_value &= mask;
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register_value >>= acpi_hw_get_bit_shift (mask);
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return (register_value);
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}
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|
|
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/******************************************************************************
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|
*
|
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* FUNCTION: Acpi_hw_register_read
|
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*
|
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* PARAMETERS: Use_lock - Mutex hw access.
|
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* Register_id - Register_iD + Offset.
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*
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* RETURN: Value read or written.
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*
|
|
* DESCRIPTION: Acpi register read function. Registers are read at the
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* given offset.
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*
|
|
******************************************************************************/
|
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|
|
u32
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acpi_hw_register_read (
|
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u8 use_lock,
|
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u32 register_id)
|
|
{
|
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u32 value = 0;
|
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u32 bank_offset;
|
|
|
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if (ACPI_MTX_LOCK == use_lock) {
|
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acpi_cm_acquire_mutex (ACPI_MTX_HARDWARE);
|
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}
|
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|
|
|
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switch (REGISTER_BLOCK_ID(register_id)) {
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case PM1_STS: /* 16-bit access */
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|
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value = acpi_hw_low_level_read (16, &acpi_gbl_FADT->Xpm1a_evt_blk, 0);
|
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value |= acpi_hw_low_level_read (16, &acpi_gbl_FADT->Xpm1b_evt_blk, 0);
|
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break;
|
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|
|
|
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case PM1_EN: /* 16-bit access*/
|
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|
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bank_offset = DIV_2 (acpi_gbl_FADT->pm1_evt_len);
|
|
value = acpi_hw_low_level_read (16, &acpi_gbl_FADT->Xpm1a_evt_blk, bank_offset);
|
|
value |= acpi_hw_low_level_read (16, &acpi_gbl_FADT->Xpm1b_evt_blk, bank_offset);
|
|
break;
|
|
|
|
|
|
case PM1_CONTROL: /* 16-bit access */
|
|
|
|
value = acpi_hw_low_level_read (16, &acpi_gbl_FADT->Xpm1a_cnt_blk, 0);
|
|
value |= acpi_hw_low_level_read (16, &acpi_gbl_FADT->Xpm1b_cnt_blk, 0);
|
|
break;
|
|
|
|
|
|
case PM2_CONTROL: /* 8-bit access */
|
|
|
|
value = acpi_hw_low_level_read (8, &acpi_gbl_FADT->Xpm2_cnt_blk, 0);
|
|
break;
|
|
|
|
|
|
case PM_TIMER: /* 32-bit access */
|
|
|
|
value = acpi_hw_low_level_read (32, &acpi_gbl_FADT->Xpm_tmr_blk, 0);
|
|
break;
|
|
|
|
|
|
case GPE0_STS_BLOCK: /* 8-bit access */
|
|
|
|
value = acpi_hw_low_level_read (8, &acpi_gbl_FADT->Xgpe0blk, 0);
|
|
break;
|
|
|
|
|
|
case GPE0_EN_BLOCK: /* 8-bit access */
|
|
|
|
bank_offset = DIV_2 (acpi_gbl_FADT->gpe0blk_len);
|
|
value = acpi_hw_low_level_read (8, &acpi_gbl_FADT->Xgpe0blk, bank_offset);
|
|
break;
|
|
|
|
|
|
case GPE1_STS_BLOCK: /* 8-bit access */
|
|
|
|
value = acpi_hw_low_level_read (8, &acpi_gbl_FADT->Xgpe1_blk, 0);
|
|
break;
|
|
|
|
|
|
case GPE1_EN_BLOCK: /* 8-bit access */
|
|
|
|
bank_offset = DIV_2 (acpi_gbl_FADT->gpe1_blk_len);
|
|
value = acpi_hw_low_level_read (8, &acpi_gbl_FADT->Xgpe1_blk, bank_offset);
|
|
break;
|
|
|
|
|
|
case SMI_CMD_BLOCK: /* 8bit */
|
|
|
|
value = (u32) acpi_os_in8 (acpi_gbl_FADT->smi_cmd);
|
|
break;
|
|
|
|
|
|
default:
|
|
value = 0;
|
|
break;
|
|
}
|
|
|
|
|
|
if (ACPI_MTX_LOCK == use_lock) {
|
|
acpi_cm_release_mutex (ACPI_MTX_HARDWARE);
|
|
}
|
|
|
|
return (value);
|
|
}
|
|
|
|
|
|
/******************************************************************************
|
|
*
|
|
* FUNCTION: Acpi_hw_register_write
|
|
*
|
|
* PARAMETERS: Use_lock - Mutex hw access.
|
|
* Register_id - Register_iD + Offset.
|
|
*
|
|
* RETURN: Value read or written.
|
|
*
|
|
* DESCRIPTION: Acpi register Write function. Registers are written at the
|
|
* given offset.
|
|
*
|
|
******************************************************************************/
|
|
|
|
void
|
|
acpi_hw_register_write (
|
|
u8 use_lock,
|
|
u32 register_id,
|
|
u32 value)
|
|
{
|
|
u32 bank_offset;
|
|
|
|
|
|
if (ACPI_MTX_LOCK == use_lock) {
|
|
acpi_cm_acquire_mutex (ACPI_MTX_HARDWARE);
|
|
}
|
|
|
|
|
|
switch (REGISTER_BLOCK_ID (register_id)) {
|
|
case PM1_STS: /* 16-bit access */
|
|
|
|
acpi_hw_low_level_write (16, value, &acpi_gbl_FADT->Xpm1a_evt_blk, 0);
|
|
acpi_hw_low_level_write (16, value, &acpi_gbl_FADT->Xpm1b_evt_blk, 0);
|
|
break;
|
|
|
|
|
|
case PM1_EN: /* 16-bit access*/
|
|
|
|
bank_offset = DIV_2 (acpi_gbl_FADT->pm1_evt_len);
|
|
acpi_hw_low_level_write (16, value, &acpi_gbl_FADT->Xpm1a_evt_blk, bank_offset);
|
|
acpi_hw_low_level_write (16, value, &acpi_gbl_FADT->Xpm1b_evt_blk, bank_offset);
|
|
break;
|
|
|
|
|
|
case PM1_CONTROL: /* 16-bit access */
|
|
|
|
acpi_hw_low_level_write (16, value, &acpi_gbl_FADT->Xpm1a_cnt_blk, 0);
|
|
acpi_hw_low_level_write (16, value, &acpi_gbl_FADT->Xpm1b_cnt_blk, 0);
|
|
break;
|
|
|
|
|
|
case PM1_a_CONTROL: /* 16-bit access */
|
|
|
|
acpi_hw_low_level_write (16, value, &acpi_gbl_FADT->Xpm1a_cnt_blk, 0);
|
|
break;
|
|
|
|
|
|
case PM1_b_CONTROL: /* 16-bit access */
|
|
|
|
acpi_hw_low_level_write (16, value, &acpi_gbl_FADT->Xpm1b_cnt_blk, 0);
|
|
break;
|
|
|
|
|
|
case PM2_CONTROL: /* 8-bit access */
|
|
|
|
acpi_hw_low_level_write (8, value, &acpi_gbl_FADT->Xpm2_cnt_blk, 0);
|
|
break;
|
|
|
|
|
|
case PM_TIMER: /* 32-bit access */
|
|
|
|
acpi_hw_low_level_write (32, value, &acpi_gbl_FADT->Xpm_tmr_blk, 0);
|
|
break;
|
|
|
|
|
|
case GPE0_STS_BLOCK: /* 8-bit access */
|
|
|
|
acpi_hw_low_level_write (8, value, &acpi_gbl_FADT->Xgpe0blk, 0);
|
|
break;
|
|
|
|
|
|
case GPE0_EN_BLOCK: /* 8-bit access */
|
|
|
|
bank_offset = DIV_2 (acpi_gbl_FADT->gpe0blk_len);
|
|
acpi_hw_low_level_write (8, value, &acpi_gbl_FADT->Xgpe0blk, bank_offset);
|
|
break;
|
|
|
|
|
|
case GPE1_STS_BLOCK: /* 8-bit access */
|
|
|
|
acpi_hw_low_level_write (8, value, &acpi_gbl_FADT->Xgpe1_blk, 0);
|
|
break;
|
|
|
|
|
|
case GPE1_EN_BLOCK: /* 8-bit access */
|
|
|
|
bank_offset = DIV_2 (acpi_gbl_FADT->gpe1_blk_len);
|
|
acpi_hw_low_level_write (8, value, &acpi_gbl_FADT->Xgpe1_blk, bank_offset);
|
|
break;
|
|
|
|
|
|
case SMI_CMD_BLOCK: /* 8bit */
|
|
|
|
/* For 2.0, SMI_CMD is always in IO space */
|
|
/* TBD: what about 1.0? 0.71? */
|
|
|
|
acpi_os_out8 (acpi_gbl_FADT->smi_cmd, (u8) value);
|
|
break;
|
|
|
|
|
|
default:
|
|
value = 0;
|
|
break;
|
|
}
|
|
|
|
|
|
if (ACPI_MTX_LOCK == use_lock) {
|
|
acpi_cm_release_mutex (ACPI_MTX_HARDWARE);
|
|
}
|
|
|
|
return;
|
|
}
|
|
|
|
|
|
/******************************************************************************
|
|
*
|
|
* FUNCTION: Acpi_hw_low_level_read
|
|
*
|
|
* PARAMETERS: Register - GAS register structure
|
|
* Offset - Offset from the base address in the GAS
|
|
* Width - 8, 16, or 32
|
|
*
|
|
* RETURN: Value read
|
|
*
|
|
* DESCRIPTION: Read from either memory, IO, or PCI config space.
|
|
*
|
|
******************************************************************************/
|
|
|
|
u32
|
|
acpi_hw_low_level_read (
|
|
u32 width,
|
|
ACPI_GAS *reg,
|
|
u32 offset)
|
|
{
|
|
u32 value = 0;
|
|
ACPI_PHYSICAL_ADDRESS mem_address;
|
|
ACPI_IO_ADDRESS io_address;
|
|
u32 pci_register;
|
|
u32 pci_dev_func;
|
|
|
|
|
|
/*
|
|
* Must have a valid pointer to a GAS structure, and
|
|
* a non-zero address within
|
|
*/
|
|
if ((!reg) ||
|
|
(!ACPI_VALID_ADDRESS (reg->address))) {
|
|
return 0;
|
|
}
|
|
|
|
|
|
/*
|
|
* Three address spaces supported:
|
|
* Memory, Io, or PCI config.
|
|
*/
|
|
|
|
switch (reg->address_space_id) {
|
|
case ADDRESS_SPACE_SYSTEM_MEMORY:
|
|
|
|
mem_address = (ACPI_PHYSICAL_ADDRESS) (ACPI_GET_ADDRESS (reg->address) + offset);
|
|
|
|
switch (width) {
|
|
case 8:
|
|
value = acpi_os_mem_in8 (mem_address);
|
|
break;
|
|
case 16:
|
|
value = acpi_os_mem_in16 (mem_address);
|
|
break;
|
|
case 32:
|
|
value = acpi_os_mem_in32 (mem_address);
|
|
break;
|
|
}
|
|
break;
|
|
|
|
|
|
case ADDRESS_SPACE_SYSTEM_IO:
|
|
|
|
io_address = (ACPI_IO_ADDRESS) (ACPI_GET_ADDRESS (reg->address) + offset);
|
|
|
|
switch (width) {
|
|
case 8:
|
|
value = acpi_os_in8 (io_address);
|
|
break;
|
|
case 16:
|
|
value = acpi_os_in16 (io_address);
|
|
break;
|
|
case 32:
|
|
value = acpi_os_in32 (io_address);
|
|
break;
|
|
}
|
|
break;
|
|
|
|
|
|
case ADDRESS_SPACE_PCI_CONFIG:
|
|
|
|
pci_dev_func = ACPI_PCI_DEVFUN (ACPI_GET_ADDRESS (reg->address));
|
|
pci_register = ACPI_PCI_REGISTER (ACPI_GET_ADDRESS (reg->address)) + offset;
|
|
|
|
switch (width) {
|
|
case 8:
|
|
acpi_os_read_pci_cfg_byte (0, pci_dev_func, pci_register, (u8 *) &value);
|
|
break;
|
|
case 16:
|
|
acpi_os_read_pci_cfg_word (0, pci_dev_func, pci_register, (u16 *) &value);
|
|
break;
|
|
case 32:
|
|
acpi_os_read_pci_cfg_dword (0, pci_dev_func, pci_register, (u32 *) &value);
|
|
break;
|
|
}
|
|
break;
|
|
}
|
|
|
|
return value;
|
|
}
|
|
|
|
|
|
/******************************************************************************
|
|
*
|
|
* FUNCTION: Acpi_hw_low_level_write
|
|
*
|
|
* PARAMETERS: Width - 8, 16, or 32
|
|
* Value - To be written
|
|
* Register - GAS register structure
|
|
* Offset - Offset from the base address in the GAS
|
|
*
|
|
*
|
|
* RETURN: Value read
|
|
*
|
|
* DESCRIPTION: Read from either memory, IO, or PCI config space.
|
|
*
|
|
******************************************************************************/
|
|
|
|
void
|
|
acpi_hw_low_level_write (
|
|
u32 width,
|
|
u32 value,
|
|
ACPI_GAS *reg,
|
|
u32 offset)
|
|
{
|
|
ACPI_PHYSICAL_ADDRESS mem_address;
|
|
ACPI_IO_ADDRESS io_address;
|
|
u32 pci_register;
|
|
u32 pci_dev_func;
|
|
|
|
|
|
/*
|
|
* Must have a valid pointer to a GAS structure, and
|
|
* a non-zero address within
|
|
*/
|
|
if ((!reg) ||
|
|
(!ACPI_VALID_ADDRESS (reg->address))) {
|
|
return;
|
|
}
|
|
|
|
|
|
/*
|
|
* Three address spaces supported:
|
|
* Memory, Io, or PCI config.
|
|
*/
|
|
|
|
switch (reg->address_space_id) {
|
|
case ADDRESS_SPACE_SYSTEM_MEMORY:
|
|
|
|
mem_address = (ACPI_PHYSICAL_ADDRESS) (ACPI_GET_ADDRESS (reg->address) + offset);
|
|
|
|
switch (width) {
|
|
case 8:
|
|
acpi_os_mem_out8 (mem_address, (u8) value);
|
|
break;
|
|
case 16:
|
|
acpi_os_mem_out16 (mem_address, (u16) value);
|
|
break;
|
|
case 32:
|
|
acpi_os_mem_out32 (mem_address, (u32) value);
|
|
break;
|
|
}
|
|
break;
|
|
|
|
|
|
case ADDRESS_SPACE_SYSTEM_IO:
|
|
|
|
io_address = (ACPI_IO_ADDRESS) (ACPI_GET_ADDRESS (reg->address) + offset);
|
|
|
|
switch (width) {
|
|
case 8:
|
|
acpi_os_out8 (io_address, (u8) value);
|
|
break;
|
|
case 16:
|
|
acpi_os_out16 (io_address, (u16) value);
|
|
break;
|
|
case 32:
|
|
acpi_os_out32 (io_address, (u32) value);
|
|
break;
|
|
}
|
|
break;
|
|
|
|
|
|
case ADDRESS_SPACE_PCI_CONFIG:
|
|
|
|
pci_dev_func = ACPI_PCI_DEVFUN (ACPI_GET_ADDRESS (reg->address));
|
|
pci_register = ACPI_PCI_REGISTER (ACPI_GET_ADDRESS (reg->address)) + offset;
|
|
|
|
switch (width) {
|
|
case 8:
|
|
acpi_os_write_pci_cfg_byte (0, pci_dev_func, pci_register, (u8) value);
|
|
break;
|
|
case 16:
|
|
acpi_os_write_pci_cfg_word (0, pci_dev_func, pci_register, (u16) value);
|
|
break;
|
|
case 32:
|
|
acpi_os_write_pci_cfg_dword (0, pci_dev_func, pci_register, (u32) value);
|
|
break;
|
|
}
|
|
break;
|
|
}
|
|
}
|