mirror of
https://github.com/reactos/reactos.git
synced 2024-10-31 03:48:17 +00:00
cd91271796
- Add boot video color constants
- Refactor palette initialization
- Move some common stuff in right place
- Get rid of some magic constants and hardcoded values
- Get rid of TopDelta variable (calculated at compile time)
- Update SAL annotations
Addendum to 5f2ca473. CORE-16216 CORE-16219
493 lines
16 KiB
C
493 lines
16 KiB
C
#include "precomp.h"
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/* PRIVATE FUNCTIONS *********************************************************/
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static BOOLEAN
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NTAPI
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VgaInterpretCmdStream(
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_In_ PUSHORT CmdStream)
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{
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USHORT Cmd;
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UCHAR Major, Minor;
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USHORT Port;
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USHORT Count;
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UCHAR Index;
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UCHAR Value;
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USHORT ShortValue;
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/* First make sure that we have a Command Stream */
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if (!CmdStream) return TRUE;
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/* Loop as long as we have commands */
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while (*CmdStream != EOD)
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{
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/* Get the next command and its Major and Minor functions */
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Cmd = *CmdStream++;
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Major = Cmd & 0xF0;
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Minor = Cmd & 0x0F;
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/* Check which major function this is */
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if (Major == INOUT)
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{
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/* Check the minor function */
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if (Minor & IO /* CMD_STREAM_READ */)
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{
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/* Check the sub-type */
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if (Minor & BW /* CMD_STREAM_USHORT */)
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{
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/* Get the port and read an USHORT from it */
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Port = *CmdStream++;
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ShortValue = __inpw(Port);
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}
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else // if (Minor & CMD_STREAM_WRITE)
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{
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/* Get the port and read an UCHAR from it */
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Port = *CmdStream++;
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Value = __inpb(Port);
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}
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}
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else if (Minor & MULTI /* CMD_STREAM_WRITE_ARRAY */)
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{
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/* Check the sub-type */
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if (Minor & BW /* CMD_STREAM_USHORT */)
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{
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/* Get the port and the count of elements */
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Port = *CmdStream++;
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Count = *CmdStream++;
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/* Write the USHORT to the port; the buffer is what's in the command stream */
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WRITE_PORT_BUFFER_USHORT((PUSHORT)(VgaRegisterBase + Port), CmdStream, Count);
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/* Move past the buffer in the command stream */
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CmdStream += Count;
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}
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else // if (Minor & CMD_STREAM_WRITE)
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{
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/* Get the port and the count of elements */
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Port = *CmdStream++;
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Count = *CmdStream++;
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/* Loop the command array */
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for (; Count; --Count, ++CmdStream)
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{
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/* Get the UCHAR and write it to the port */
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Value = (UCHAR)*CmdStream;
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__outpb(Port, Value);
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}
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}
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}
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else if (Minor & BW /* CMD_STREAM_USHORT */)
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{
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/* Get the port */
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Port = *CmdStream++;
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/* Get the USHORT and write it to the port */
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ShortValue = *CmdStream++;
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__outpw(Port, ShortValue);
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}
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else // if (Minor & CMD_STREAM_WRITE)
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{
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/* Get the port */
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Port = *CmdStream++;
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/* Get the UCHAR and write it to the port */
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Value = (UCHAR)*CmdStream++;
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__outpb(Port, Value);
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}
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}
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else if (Major == METAOUT)
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{
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/* Check the minor function. Note these are not flags. */
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switch (Minor)
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{
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case INDXOUT:
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{
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/* Get the port, the count of elements and the start index */
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Port = *CmdStream++;
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Count = *CmdStream++;
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Index = (UCHAR)*CmdStream++;
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/* Loop the command array */
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for (; Count; --Count, ++Index, ++CmdStream)
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{
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/* Get the USHORT and write it to the port */
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ShortValue = (USHORT)Index + ((*CmdStream) << 8);
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__outpw(Port, ShortValue);
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}
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break;
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}
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case ATCOUT:
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{
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/* Get the port, the count of elements and the start index */
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Port = *CmdStream++;
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Count = *CmdStream++;
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Index = (UCHAR)*CmdStream++;
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/* Loop the command array */
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for (; Count; --Count, ++Index, ++CmdStream)
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{
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/* Write the index */
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__outpb(Port, Index);
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/* Get the UCHAR and write it to the port */
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Value = (UCHAR)*CmdStream;
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__outpb(Port, Value);
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}
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break;
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}
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case MASKOUT:
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{
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/* Get the port */
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Port = *CmdStream++;
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/* Read the current value and add the stream data */
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Value = __inpb(Port);
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Value &= *CmdStream++;
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Value ^= *CmdStream++;
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/* Write the value */
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__outpb(Port, Value);
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break;
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}
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default:
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/* Unknown command, fail */
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return FALSE;
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}
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}
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else if (Major != NCMD)
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{
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/* Unknown major function, fail */
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return FALSE;
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}
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}
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/* If we got here, return success */
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return TRUE;
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}
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static BOOLEAN
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NTAPI
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VgaIsPresent(VOID)
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{
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UCHAR OrgGCAddr, OrgReadMap, OrgBitMask;
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UCHAR OrgSCAddr, OrgMemMode;
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UCHAR i;
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/* Remember the original state of the Graphics Controller Address register */
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OrgGCAddr = __inpb(VGA_BASE_IO_PORT + GRAPH_ADDRESS_PORT);
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/*
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* Write the Read Map register with a known state so we can verify
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* that it isn't changed after we fool with the Bit Mask. This ensures
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* that we're dealing with indexed registers, since both the Read Map and
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* the Bit Mask are addressed at GRAPH_DATA_PORT.
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*/
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__outpb(VGA_BASE_IO_PORT + GRAPH_ADDRESS_PORT, IND_READ_MAP);
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/*
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* If we can't read back the Graphics Address register setting we just
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* performed, it's not readable and this isn't a VGA.
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*/
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if ((__inpb(VGA_BASE_IO_PORT + GRAPH_ADDRESS_PORT) & GRAPH_ADDR_MASK) != IND_READ_MAP)
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return FALSE;
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/*
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* Set the Read Map register to a known state.
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*/
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OrgReadMap = __inpb(VGA_BASE_IO_PORT + GRAPH_DATA_PORT);
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__outpb(VGA_BASE_IO_PORT + GRAPH_DATA_PORT, READ_MAP_TEST_SETTING);
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/* Read it back... it should be the same */
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if (__inpb(VGA_BASE_IO_PORT + GRAPH_DATA_PORT) != READ_MAP_TEST_SETTING)
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{
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/*
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* The Read Map setting we just performed can't be read back; not a
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* VGA. Restore the default Read Map state and fail.
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*/
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__outpb(VGA_BASE_IO_PORT + GRAPH_DATA_PORT, READ_MAP_DEFAULT);
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return FALSE;
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}
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/* Remember the original setting of the Bit Mask register */
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__outpb(VGA_BASE_IO_PORT + GRAPH_ADDRESS_PORT, IND_BIT_MASK);
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/* Read it back... it should be the same */
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if ((__inpb(VGA_BASE_IO_PORT + GRAPH_ADDRESS_PORT) & GRAPH_ADDR_MASK) != IND_BIT_MASK)
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{
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/*
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* The Graphics Address register setting we just made can't be read
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* back; not a VGA. Restore the default Read Map state and fail.
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*/
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__outpb(VGA_BASE_IO_PORT + GRAPH_ADDRESS_PORT, IND_READ_MAP);
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__outpb(VGA_BASE_IO_PORT + GRAPH_DATA_PORT, READ_MAP_DEFAULT);
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return FALSE;
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}
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/* Read the VGA Data Register */
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OrgBitMask = __inpb(VGA_BASE_IO_PORT + GRAPH_DATA_PORT);
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/*
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* Set up the initial test mask we'll write to and read from the Bit Mask,
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* and loop on the bitmasks.
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*/
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for (i = 0xBB; i; i >>= 1)
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{
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/* Write the test mask to the Bit Mask */
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__outpb(VGA_BASE_IO_PORT + GRAPH_DATA_PORT, i);
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/* Read it back... it should be the same */
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if (__inpb(VGA_BASE_IO_PORT + GRAPH_DATA_PORT) != i)
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{
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/*
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* The Bit Mask is not properly writable and readable; not a VGA.
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* Restore the Bit Mask and Read Map to their default states and fail.
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*/
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__outpb(VGA_BASE_IO_PORT + GRAPH_DATA_PORT, BIT_MASK_DEFAULT);
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__outpb(VGA_BASE_IO_PORT + GRAPH_ADDRESS_PORT, IND_READ_MAP);
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__outpb(VGA_BASE_IO_PORT + GRAPH_DATA_PORT, READ_MAP_DEFAULT);
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return FALSE;
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}
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}
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/*
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* There's something readable at GRAPH_DATA_PORT; now switch back and
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* make sure that the Read Map register hasn't changed, to verify that
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* we're dealing with indexed registers.
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*/
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__outpb(VGA_BASE_IO_PORT + GRAPH_ADDRESS_PORT, IND_READ_MAP);
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/* Read it back */
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if (__inpb(VGA_BASE_IO_PORT + GRAPH_DATA_PORT) != READ_MAP_TEST_SETTING)
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{
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/*
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* The Read Map is not properly writable and readable; not a VGA.
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* Restore the Bit Mask and Read Map to their default states, in case
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* this is an EGA, so subsequent writes to the screen aren't garbled.
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* Then fail.
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*/
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__outpb(VGA_BASE_IO_PORT + GRAPH_DATA_PORT, READ_MAP_DEFAULT);
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__outpb(VGA_BASE_IO_PORT + GRAPH_ADDRESS_PORT, IND_BIT_MASK);
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__outpb(VGA_BASE_IO_PORT + GRAPH_DATA_PORT, BIT_MASK_DEFAULT);
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return FALSE;
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}
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/*
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* We've pretty surely verified the existence of the Bit Mask register.
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* Put the Graphics Controller back to the original state.
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*/
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__outpb(VGA_BASE_IO_PORT + GRAPH_DATA_PORT, OrgReadMap);
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__outpb(VGA_BASE_IO_PORT + GRAPH_ADDRESS_PORT, IND_BIT_MASK);
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__outpb(VGA_BASE_IO_PORT + GRAPH_DATA_PORT, OrgBitMask);
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__outpb(VGA_BASE_IO_PORT + GRAPH_ADDRESS_PORT, OrgGCAddr);
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/*
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* Now, check for the existence of the Chain4 bit.
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*/
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/*
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* Remember the original states of the Sequencer Address and Memory Mode
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* registers.
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*/
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OrgSCAddr = __inpb(VGA_BASE_IO_PORT + SEQ_ADDRESS_PORT);
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__outpb(VGA_BASE_IO_PORT + SEQ_ADDRESS_PORT, IND_MEMORY_MODE);
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/* Read it back... it should be the same */
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if ((__inpb(VGA_BASE_IO_PORT + SEQ_ADDRESS_PORT) & SEQ_ADDR_MASK) != IND_MEMORY_MODE)
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{
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/*
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* Couldn't read back the Sequencer Address register setting
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* we just performed, fail.
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*/
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return FALSE;
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}
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/* Read sequencer Data */
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OrgMemMode = __inpb(VGA_BASE_IO_PORT + SEQ_DATA_PORT);
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/*
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* Toggle the Chain4 bit and read back the result. This must be done during
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* sync reset, since we're changing the chaining state.
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*/
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/* Begin sync reset */
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__outpw(VGA_BASE_IO_PORT + SEQ_ADDRESS_PORT, (IND_SYNC_RESET + (START_SYNC_RESET_VALUE << 8)));
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/* Toggle the Chain4 bit */
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__outpb(VGA_BASE_IO_PORT + SEQ_ADDRESS_PORT, IND_MEMORY_MODE);
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__outpb(VGA_BASE_IO_PORT + SEQ_DATA_PORT, OrgMemMode ^ CHAIN4_MASK);
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/* Read it back... it should be the same */
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if (__inpb(VGA_BASE_IO_PORT + SEQ_DATA_PORT) != (OrgMemMode ^ CHAIN4_MASK))
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{
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/*
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* Chain4 bit is not there, not a VGA.
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* Set text mode default for Memory Mode register.
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*/
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__outpb(VGA_BASE_IO_PORT + SEQ_DATA_PORT, MEMORY_MODE_TEXT_DEFAULT);
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/* End sync reset */
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__outpw(VGA_BASE_IO_PORT + SEQ_ADDRESS_PORT, (IND_SYNC_RESET + (END_SYNC_RESET_VALUE << 8)));
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/* Fail */
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return FALSE;
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}
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/*
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* It's a VGA.
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*/
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/* Restore the original Memory Mode setting */
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__outpb(VGA_BASE_IO_PORT + SEQ_DATA_PORT, OrgMemMode);
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/* End sync reset */
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__outpw(VGA_BASE_IO_PORT + SEQ_ADDRESS_PORT, (IND_SYNC_RESET + (END_SYNC_RESET_VALUE << 8)));
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/* Restore the original Sequencer Address setting */
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__outpb(VGA_BASE_IO_PORT + SEQ_ADDRESS_PORT, OrgSCAddr);
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/* VGA is present! */
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return TRUE;
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}
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/* PUBLIC FUNCTIONS **********************************************************/
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/*
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* @implemented
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*/
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BOOLEAN
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NTAPI
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VidInitialize(
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_In_ BOOLEAN SetMode)
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{
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ULONG_PTR Context = 0;
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PHYSICAL_ADDRESS TranslatedAddress;
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PHYSICAL_ADDRESS NullAddress = {{0, 0}}, VgaAddress;
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ULONG AddressSpace;
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BOOLEAN Result;
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ULONG_PTR Base;
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/* Make sure that we have a bus translation function */
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if (!HalFindBusAddressTranslation) return FALSE;
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/* Loop trying to find possible VGA base addresses */
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while (TRUE)
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{
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/* Get the VGA Register address */
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AddressSpace = 1;
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Result = HalFindBusAddressTranslation(NullAddress,
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&AddressSpace,
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&TranslatedAddress,
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&Context,
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TRUE);
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if (!Result) return FALSE;
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/* See if this is I/O Space, which we need to map */
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if (!AddressSpace)
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{
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/* Map it */
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Base = (ULONG_PTR)MmMapIoSpace(TranslatedAddress, 0x400, MmNonCached);
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}
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else
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{
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/* The base is the translated address, no need to map I/O space */
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Base = TranslatedAddress.LowPart;
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}
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/* Try to see if this is VGA */
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VgaRegisterBase = Base;
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if (VgaIsPresent())
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{
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/* Translate the VGA Memory Address */
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VgaAddress.LowPart = MEM_VGA;
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VgaAddress.HighPart = 0;
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AddressSpace = 0;
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Result = HalFindBusAddressTranslation(VgaAddress,
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&AddressSpace,
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&TranslatedAddress,
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&Context,
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FALSE);
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if (Result) break;
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}
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else
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{
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/* It's not, so unmap the I/O space if we mapped it */
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if (!AddressSpace) MmUnmapIoSpace((PVOID)VgaRegisterBase, 0x400);
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}
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/* Continue trying to see if there's any other address */
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}
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/* Success! See if this is I/O Space, which we need to map */
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if (!AddressSpace)
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{
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/* Map it */
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Base = (ULONG_PTR)MmMapIoSpace(TranslatedAddress,
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MEM_VGA_SIZE,
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MmNonCached);
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}
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else
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{
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/* The base is the translated address, no need to map I/O space */
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Base = TranslatedAddress.LowPart;
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}
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/* Set the VGA Memory Base */
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VgaBase = Base;
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/* Now check if we have to set the mode */
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if (SetMode)
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{
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/* Clear the current position */
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VidpCurrentX = 0;
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VidpCurrentY = 0;
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/* Reset the display and initialize it */
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if (HalResetDisplay())
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{
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/* The HAL handled the display, re-initialize only the AC registers */
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VgaInterpretCmdStream(AT_Initialization);
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}
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else
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{
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/* The HAL didn't handle the display, fully re-initialize the VGA */
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VgaInterpretCmdStream(VGA_640x480);
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}
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}
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/* VGA is ready */
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return TRUE;
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}
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/*
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* @implemented
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*/
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VOID
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NTAPI
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VidResetDisplay(
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_In_ BOOLEAN HalReset)
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{
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/* Clear the current position */
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VidpCurrentX = 0;
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VidpCurrentY = 0;
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/* Clear the screen with HAL if we were asked to */
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if (HalReset)
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{
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if (!HalResetDisplay())
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{
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/* The HAL didn't handle the display, fully re-initialize the VGA */
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VgaInterpretCmdStream(VGA_640x480);
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}
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}
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/* Always re-initialize the AC registers */
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VgaInterpretCmdStream(AT_Initialization);
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/* Re-initialize the palette and fill the screen black */
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InitializePalette();
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VidSolidColorFill(0, 0, SCREEN_WIDTH - 1, SCREEN_HEIGHT - 1, BV_COLOR_BLACK);
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}
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