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fa8f26e7c6
Adding stw for dissembler and converting (PPC and IA32) Fixing a counter bug in ConvertBitToByte, ConvertBitToByte32, GetMaskByte, GetMaskByte32 we did miss one bit calculation when we count the mask the bit 0 svn path=/trunk/; revision=25527
26 lines
1.1 KiB
C
26 lines
1.1 KiB
C
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#include "../../misc.h"
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/* example how setup a opcode, this opcode is 16bit long (taken from M68K)
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* 0 and 1 mean normal bit, 2 mean mask bit the bit that are determent diffent
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* thing in the opcode, example which reg so on, it can be etither 0 or 1 in
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* the opcode. but a opcode have also normal bit that is always been set to
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* same. thuse bit are always 0 or 1
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*/
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/* FIXME RA should be 0 in stwu */
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CPU_BYTE cpuPPCInit_Blr[32] = {0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,1,1,1,0};
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CPU_BYTE cpuPPCInit_Li[32] = {2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,0,0,0,0,0,0,0,1,1,1,0,2,2};
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CPU_BYTE cpuPPCInit_stw[32] = {2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,1,0,0,1,0,0,2,2};
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CPU_BYTE cpuPPCInit_stwu[32] = {2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,1,0,0,1,0,1,2,2};
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/* mask */
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/*
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* no mask we implement function getting the reg right
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*/
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/* bit index
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3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
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1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
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*/
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