mirror of
https://github.com/reactos/reactos.git
synced 2024-11-09 16:20:37 +00:00
708 lines
15 KiB
C
708 lines
15 KiB
C
/*
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* PROJECT: ReactOS Hardware Abstraction Layer (HAL)
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* LICENSE: BSD - See COPYING.ARM in the top level directory
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* FILE: halx86/generic/bios.c
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* PURPOSE: BIOS Access Routines
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* PROGRAMMERS: ReactOS Portable Systems Group
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* Alex Ionescu (alex.ionescu@reactos.org)
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*/
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/* INCLUDES *******************************************************************/
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#include <hal.h>
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#define NDEBUG
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#include <debug.h>
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#include <setjmp.h>
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void HalpTrap0D();
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/* GLOBALS ********************************************************************/
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//
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// PTE Data
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//
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ULONG HalpSavedPfn;
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HARDWARE_PTE HalpSavedPte;
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//
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// IDT Data
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//
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PVOID HalpGpfHandler;
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PVOID HalpBopHandler;
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//
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// TSS Data
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//
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ULONG HalpSavedEsp0;
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USHORT HalpSavedTss;
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//
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// IOPM Data
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//
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USHORT HalpSavedIopmBase;
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PUSHORT HalpSavedIoMap;
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USHORT HalpSavedIoMapData[32][2];
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ULONG HalpSavedIoMapEntries;
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/* Where the protected mode stack is */
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ULONG_PTR HalpSavedEsp;
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/* Where the real mode code ends */
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extern PVOID HalpRealModeEnd;
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/* Context saved for return from v86 mode */
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jmp_buf HalpSavedContext;
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/* V86 OPCODE HANDLERS ********************************************************/
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BOOLEAN
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FASTCALL
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HalpOpcodeInvalid(IN PHAL_BIOS_FRAME BiosFrame)
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{
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/* Print error message */
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DPRINT1("HAL: An invalid V86 opcode was encountered at address %x:%x\n",
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BiosFrame->SegCs, BiosFrame->Eip);
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/* Break */
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DbgBreakPoint();
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return FALSE;
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}
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BOOLEAN
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FASTCALL
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HalpPushInt(IN PHAL_BIOS_FRAME BiosFrame,
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IN ULONG Interrupt)
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{
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PUSHORT Stack;
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ULONG Eip;
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/* Calculate stack address (SP) */
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Stack = (PUSHORT)(BiosFrame->SsBase + (BiosFrame->Esp & 0xFFFF));
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/* Push EFlags */
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Stack--;
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*Stack = BiosFrame->EFlags & 0xFFFF;
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/* Push CS */
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Stack--;
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*Stack = BiosFrame->SegCs & 0xFFFF;
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/* Push IP */
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Stack--;
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*Stack = BiosFrame->Eip & 0xFFFF;
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/* Compute new CS:IP from the IVT address for this interrupt entry */
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Eip = *(PULONG)(Interrupt * 4);
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BiosFrame->Eip = Eip & 0xFFFF;
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BiosFrame->SegCs = Eip >> 16;
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/* Update stack address */
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BiosFrame->Esp = (ULONG_PTR)Stack & 0xFFFF;
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/* Update CS to linear */
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BiosFrame->CsBase = BiosFrame->SegCs << 4;
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BiosFrame->CsLimit = 0xFFFF;
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BiosFrame->CsFlags = 0;
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/* We're done */
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return TRUE;
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}
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BOOLEAN
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FASTCALL
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HalpOpcodeINTnn(IN PHAL_BIOS_FRAME BiosFrame)
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{
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UCHAR Interrupt;
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PKTRAP_FRAME TrapFrame;
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/* Convert SS to linear */
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BiosFrame->SsBase = BiosFrame->SegSs << 4;
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BiosFrame->SsLimit = 0xFFFF;
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BiosFrame->SsFlags = 0;
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/* Increase EIP and validate */
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BiosFrame->Eip++;
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if (BiosFrame->Eip > BiosFrame->CsLimit) return FALSE;
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/* Read interrupt number */
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Interrupt = *(PUCHAR)(BiosFrame->CsBase + BiosFrame->Eip);
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/* Increase EIP and push the interrupt */
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BiosFrame->Eip++;
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if (HalpPushInt(BiosFrame, Interrupt))
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{
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/* Update the trap frame */
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TrapFrame = BiosFrame->TrapFrame;
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TrapFrame->HardwareSegSs = BiosFrame->SegSs;
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TrapFrame->HardwareEsp = BiosFrame->Esp;
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TrapFrame->SegCs = BiosFrame->SegCs;
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TrapFrame->EFlags = BiosFrame->EFlags;
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/* Success */
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return TRUE;
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}
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/* Failure */
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return FALSE;
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}
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BOOLEAN
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FASTCALL
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HalpDispatchV86Opcode(IN PKTRAP_FRAME TrapFrame)
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{
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UCHAR Instruction;
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HAL_BIOS_FRAME BiosFrame;
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/* Fill out the BIOS frame */
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BiosFrame.TrapFrame = TrapFrame;
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BiosFrame.SegSs = TrapFrame->HardwareSegSs;
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BiosFrame.Esp = TrapFrame->HardwareEsp;
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BiosFrame.EFlags = TrapFrame->EFlags;
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BiosFrame.SegCs = TrapFrame->SegCs;
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BiosFrame.Eip = TrapFrame->Eip;
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BiosFrame.Prefix = 0;
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/* Convert CS to linear */
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BiosFrame.CsBase = BiosFrame.SegCs << 4;
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BiosFrame.CsLimit = 0xFFFF;
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BiosFrame.CsFlags = 0;
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/* Validate IP */
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if (BiosFrame.Eip > BiosFrame.CsLimit) return FALSE;
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/* Read IP */
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Instruction = *(PUCHAR)(BiosFrame.CsBase + BiosFrame.Eip);
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if (Instruction != 0xCD)
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{
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/* We only support INT */
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HalpOpcodeInvalid(&BiosFrame);
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return FALSE;
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}
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/* Handle the interrupt */
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if (HalpOpcodeINTnn(&BiosFrame))
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{
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/* Update EIP */
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TrapFrame->Eip = BiosFrame.Eip;
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/* We're done */
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return TRUE;
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}
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/* Failure */
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return FALSE;
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}
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/* V86 TRAP HANDLERS **********************************************************/
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#ifndef _MINIHAL_
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DECLSPEC_NORETURN
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VOID
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FASTCALL
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HalpTrap0DHandler(IN PKTRAP_FRAME TrapFrame)
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{
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/* Enter the trap */
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KiEnterTrap(TrapFrame);
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/* Check if this is a V86 trap */
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if (TrapFrame->EFlags & EFLAGS_V86_MASK)
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{
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/* Dispatch the opcode and exit the trap */
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HalpDispatchV86Opcode(TrapFrame);
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KiEoiHelper(TrapFrame);
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}
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/* Strange, it isn't! This can happen during NMI */
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DPRINT1("HAL: Trap0D while not in V86 mode\n");
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KiDumpTrapFrame(TrapFrame);
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ERROR_FATAL();
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while (TRUE); /* 'noreturn' function */
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}
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VOID
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DECLSPEC_NORETURN
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HalpTrap06()
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{
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/* Restore ES/DS to known good values first */
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Ke386SetEs(KGDT_R3_DATA | RPL_MASK);
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Ke386SetDs(KGDT_R3_DATA | RPL_MASK);
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Ke386SetFs(KGDT_R0_PCR);
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/* Restore the stack */
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KeGetPcr()->TSS->Esp0 = HalpSavedEsp0;
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/* Return back to where we left */
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longjmp(HalpSavedContext, 1);
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UNREACHABLE;
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}
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/* V8086 ENTER ****************************************************************/
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VOID
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NTAPI
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HalpBiosCall()
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{
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/* Must be volatile so it doesn't get optimized away! */
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volatile KTRAP_FRAME V86TrapFrame;
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ULONG_PTR StackOffset, CodeOffset;
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/* Save the context, check for return */
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if (_setjmp(HalpSavedContext))
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{
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/* Returned from v86 */
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return;
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}
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/* Kill alignment faults */
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__writecr0(__readcr0() & ~CR0_AM);
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/* Set new stack address */
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KeGetPcr()->TSS->Esp0 = (ULONG)&V86TrapFrame - 0x20 - sizeof(FX_SAVE_AREA);
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/* Compute segmented IP and SP offsets */
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StackOffset = (ULONG_PTR)&HalpRealModeEnd - 4 - (ULONG_PTR)HalpRealModeStart;
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CodeOffset = (ULONG_PTR)HalpRealModeStart & 0xFFF;
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/* Now build the V86 trap frame */
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V86TrapFrame.V86Es = 0;
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V86TrapFrame.V86Ds = 0;
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V86TrapFrame.V86Gs = 0;
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V86TrapFrame.V86Fs = 0;
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V86TrapFrame.HardwareSegSs = 0x2000;
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V86TrapFrame.HardwareEsp = StackOffset + CodeOffset;
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V86TrapFrame.EFlags = __readeflags() | EFLAGS_V86_MASK | EFLAGS_IOPL;
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V86TrapFrame.SegCs = 0x2000;
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V86TrapFrame.Eip = CodeOffset;
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/* Exit to V86 mode */
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HalpExitToV86((PKTRAP_FRAME)&V86TrapFrame);
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}
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#endif
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/* FUNCTIONS ******************************************************************/
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VOID
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NTAPI
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HalpBorrowTss(VOID)
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{
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USHORT Tss;
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PKGDTENTRY TssGdt;
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ULONG_PTR TssLimit;
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PKTSS TssBase;
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//
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// Get the current TSS and its GDT entry
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//
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Tss = Ke386GetTr();
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TssGdt = &((PKIPCR)KeGetPcr())->GDT[Tss / sizeof(KGDTENTRY)];
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//
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// Get the KTSS limit and check if it has IOPM space
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//
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TssLimit = TssGdt->LimitLow | TssGdt->HighWord.Bits.LimitHi << 16;
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//
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// If the KTSS doesn't have enough space this is probably an NMI or DF
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//
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if (TssLimit > IOPM_SIZE)
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{
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//
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// We are good to go
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//
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HalpSavedTss = 0;
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return;
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}
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//
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// Get the "real" TSS
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//
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TssGdt = &((PKIPCR)KeGetPcr())->GDT[KGDT_TSS / sizeof(KGDTENTRY)];
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TssBase = (PKTSS)(ULONG_PTR)(TssGdt->BaseLow |
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TssGdt->HighWord.Bytes.BaseMid << 16 |
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TssGdt->HighWord.Bytes.BaseHi << 24);
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//
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// Switch to it
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//
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KeGetPcr()->TSS = TssBase;
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//
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// Set it up
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//
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TssGdt->HighWord.Bits.Type = I386_TSS;
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TssGdt->HighWord.Bits.Pres = 1;
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TssGdt->HighWord.Bits.Dpl = 0;
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//
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// Load new TSS and return old one
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//
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Ke386SetTr(KGDT_TSS);
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HalpSavedTss = Tss;
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}
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VOID
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NTAPI
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HalpReturnTss(VOID)
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{
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PKGDTENTRY TssGdt;
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PKTSS TssBase;
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//
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// Get the original TSS
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//
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TssGdt = &((PKIPCR)KeGetPcr())->GDT[HalpSavedTss / sizeof(KGDTENTRY)];
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TssBase = (PKTSS)(ULONG_PTR)(TssGdt->BaseLow |
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TssGdt->HighWord.Bytes.BaseMid << 16 |
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TssGdt->HighWord.Bytes.BaseHi << 24);
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//
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// Switch to it
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//
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KeGetPcr()->TSS = TssBase;
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//
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// Set it up
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//
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TssGdt->HighWord.Bits.Type = I386_TSS;
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TssGdt->HighWord.Bits.Pres = 1;
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TssGdt->HighWord.Bits.Dpl = 0;
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//
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// Load old TSS
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//
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Ke386SetTr(HalpSavedTss);
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}
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VOID
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NTAPI
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HalpStoreAndClearIopm(VOID)
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{
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USHORT i, j;
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PUSHORT Entry = HalpSavedIoMap;
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//
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// Loop the I/O Map
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//
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for (i = j = 0; i < (IOPM_SIZE) / 2; i++)
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{
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//
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// Check for non-FFFF entry
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//
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if (*Entry != 0xFFFF)
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{
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//
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// Save it
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//
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ASSERT(j < 32);
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HalpSavedIoMapData[j][0] = i;
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HalpSavedIoMapData[j][1] = *Entry;
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j++;
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}
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//
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// Clear it
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//
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*Entry++ = 0;
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}
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//
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// Terminate it
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//
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while (i++ < (IOPM_FULL_SIZE / 2)) *Entry++ = 0xFFFF;
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//
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// Return the entries we saved
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//
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HalpSavedIoMapEntries = j;
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}
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VOID
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NTAPI
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HalpRestoreIopm(VOID)
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{
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ULONG i = HalpSavedIoMapEntries;
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//
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// Set default state
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//
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RtlFillMemory(HalpSavedIoMap, IOPM_FULL_SIZE, 0xFF);
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//
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// Restore the backed up copy, and initialize it
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//
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while (i--) HalpSavedIoMap[HalpSavedIoMapData[i][0]] = HalpSavedIoMapData[i][1];
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}
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#ifndef _MINIHAL_
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VOID
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NTAPI
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HalpMapRealModeMemory(VOID)
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{
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PHARDWARE_PTE Pte, V86Pte;
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ULONG i;
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//
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// Get the page table directory for the lowest meg of memory
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//
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Pte = HalAddressToPde(0);
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HalpSavedPfn = Pte->PageFrameNumber;
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HalpSavedPte = *Pte;
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//
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// Map it to the HAL reserved region and make it valid
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//
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Pte->Valid = 1;
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Pte->Write = 1;
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Pte->Owner = 1;
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Pte->PageFrameNumber = (HalAddressToPde(0xFFC00000))->PageFrameNumber;
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//
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// Flush the TLB
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//
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HalpFlushTLB();
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//
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// Now loop the first meg of memory
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//
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for (i = 0; i < 0x100000; i += PAGE_SIZE)
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{
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//
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// Identity map it
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//
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Pte = HalAddressToPte(i);
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Pte->PageFrameNumber = i >> PAGE_SHIFT;
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Pte->Valid = 1;
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Pte->Write = 1;
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Pte->Owner = 1;
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}
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//
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// Now get the entry for our real mode V86 code and the target
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//
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Pte = HalAddressToPte(0x20000);
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V86Pte = HalAddressToPte(&HalpRealModeStart);
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do
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{
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//
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// Map the physical address into our real-mode region
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//
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Pte->PageFrameNumber = V86Pte->PageFrameNumber;
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//
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// Keep going until we've reached the end of our region
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//
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Pte++;
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V86Pte++;
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} while (V86Pte <= HalAddressToPte(&HalpRealModeEnd));
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//
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// Flush the TLB
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//
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HalpFlushTLB();
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}
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VOID
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NTAPI
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HalpSwitchToRealModeTrapHandlers(VOID)
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{
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//
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// Save the current Invalid Opcode and General Protection Fault Handlers
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//
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HalpGpfHandler = KeQueryInterruptHandler(13);
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HalpBopHandler = KeQueryInterruptHandler(6);
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//
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// Now set our own GPF handler to handle exceptions while in real mode
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//
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KeRegisterInterruptHandler(13, HalpTrap0D);
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//
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// And our own invalid opcode handler to detect the BOP to get us out
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//
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KeRegisterInterruptHandler(6, HalpTrap06);
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}
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#endif
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VOID
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NTAPI
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HalpSetupRealModeIoPermissionsAndTask(VOID)
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{
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//
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// Switch to valid TSS
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//
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HalpBorrowTss();
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//
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// Save a copy of the I/O Map and delete it
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//
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HalpSavedIoMap = (PUSHORT)&(KeGetPcr()->TSS->IoMaps[0]);
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HalpStoreAndClearIopm();
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//
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// Save the IOPM and switch to the real-mode one
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//
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HalpSavedIopmBase = KeGetPcr()->TSS->IoMapBase;
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KeGetPcr()->TSS->IoMapBase = KiComputeIopmOffset(1);
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//
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// Save our stack pointer
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//
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HalpSavedEsp0 = KeGetPcr()->TSS->Esp0;
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}
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VOID
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NTAPI
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HalpRestoreTrapHandlers(VOID)
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{
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//
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// Keep dummy GPF handler in case we get an NMI during V8086
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//
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if (!HalpNMIInProgress)
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{
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//
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// Not an NMI -- put back the original handler
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//
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KeRegisterInterruptHandler(13, HalpGpfHandler);
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}
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//
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// Restore invalid opcode handler
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//
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KeRegisterInterruptHandler(6, HalpBopHandler);
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}
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VOID
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NTAPI
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HalpRestoreIoPermissionsAndTask(VOID)
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{
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//
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// Restore the stack pointer
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//
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KeGetPcr()->TSS->Esp0 = HalpSavedEsp0;
|
|
|
|
//
|
|
// Restore the I/O Map
|
|
//
|
|
HalpRestoreIopm();
|
|
|
|
//
|
|
// Restore the IOPM
|
|
//
|
|
KeGetPcr()->TSS->IoMapBase = HalpSavedIopmBase;
|
|
|
|
//
|
|
// Restore the TSS
|
|
//
|
|
if (HalpSavedTss) HalpReturnTss();
|
|
}
|
|
|
|
VOID
|
|
NTAPI
|
|
HalpUnmapRealModeMemory(VOID)
|
|
{
|
|
ULONG i;
|
|
PHARDWARE_PTE Pte;
|
|
|
|
//
|
|
// Loop the first meg of memory
|
|
//
|
|
for (i = 0; i < 0x100000; i += PAGE_SIZE)
|
|
{
|
|
//
|
|
// Invalidate each PTE
|
|
//
|
|
Pte = HalAddressToPte(i);
|
|
Pte->Valid = 0;
|
|
Pte->Write = 0;
|
|
Pte->Owner = 0;
|
|
Pte->PageFrameNumber = 0;
|
|
}
|
|
|
|
//
|
|
// Restore the PDE for the lowest megabyte of memory
|
|
//
|
|
Pte = HalAddressToPde(0);
|
|
*Pte = HalpSavedPte;
|
|
Pte->PageFrameNumber = HalpSavedPfn;
|
|
|
|
//
|
|
// Flush the TLB
|
|
//
|
|
HalpFlushTLB();
|
|
}
|
|
|
|
#ifndef _MINIHAL_
|
|
BOOLEAN
|
|
NTAPI
|
|
HalpBiosDisplayReset(VOID)
|
|
{
|
|
ULONG Flags;
|
|
PHARDWARE_PTE IdtPte;
|
|
BOOLEAN RestoreWriteProtection = FALSE;
|
|
|
|
//
|
|
// Disable interrupts
|
|
//
|
|
Flags = __readeflags();
|
|
_disable();
|
|
|
|
//
|
|
// Map memory available to the V8086 real-mode code
|
|
//
|
|
HalpMapRealModeMemory();
|
|
|
|
//
|
|
// On P5, the first 7 entries of the IDT are write protected to work around
|
|
// the cmpxchg8b lock errata. Unprotect them here so we can set our custom
|
|
// invalid op-code handler.
|
|
//
|
|
IdtPte = HalAddressToPte(((PKIPCR)KeGetPcr())->IDT);
|
|
RestoreWriteProtection = IdtPte->Write != 0;
|
|
IdtPte->Write = 1;
|
|
|
|
//
|
|
// Use special invalid opcode and GPF trap handlers
|
|
//
|
|
HalpSwitchToRealModeTrapHandlers();
|
|
|
|
//
|
|
// Configure the IOPM and TSS
|
|
//
|
|
HalpSetupRealModeIoPermissionsAndTask();
|
|
|
|
//
|
|
// Now jump to real mode
|
|
//
|
|
HalpBiosCall();
|
|
|
|
//
|
|
// Restore kernel trap handlers
|
|
//
|
|
HalpRestoreTrapHandlers();
|
|
|
|
//
|
|
// Restore write permission
|
|
//
|
|
IdtPte->Write = RestoreWriteProtection;
|
|
|
|
//
|
|
// Restore TSS and IOPM
|
|
//
|
|
HalpRestoreIoPermissionsAndTask();
|
|
|
|
//
|
|
// Restore low memory mapping
|
|
//
|
|
HalpUnmapRealModeMemory();
|
|
|
|
//
|
|
// Restore interrupts if they were previously enabled
|
|
//
|
|
__writeeflags(Flags);
|
|
return TRUE;
|
|
}
|
|
#endif
|
|
|
|
/* EOF */
|