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7601fb549c
- Rename UP -> PIC. The "up" folder in fact contains the code for managing the Intel 8259 PIC chip - Move amd64/processor.c -> apic/processor.c. The code is not tied to amd64 - Remove platform from "halinit*" files. They already reside in the corresponding folder
164 lines
7.3 KiB
C
164 lines
7.3 KiB
C
/*
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* PROJECT: ReactOS Hardware Abstraction Layer
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* LICENSE: BSD - See COPYING.ARM in the top level directory
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* PURPOSE: IRQL mapping
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* PROGRAMMERS: ReactOS Portable Systems Group
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*/
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/* INCLUDES *******************************************************************/
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#include <hal.h>
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/* GLOBALS ********************************************************************/
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/* This table contains the static x86 PIC mapping between IRQLs and IRQs */
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ULONG KiI8259MaskTable[32] =
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{
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/*
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* It Device IRQLs only start at 4 or higher, so these are just software
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* IRQLs that don't really change anything on the hardware
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*/
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0b00000000000000000000000000000000, /* IRQL 0 */
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0b00000000000000000000000000000000, /* IRQL 1 */
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0b00000000000000000000000000000000, /* IRQL 2 */
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0b00000000000000000000000000000000, /* IRQL 3 */
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/*
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* These next IRQLs are actually useless from the PIC perspective, because
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* with only 2 PICs, the mask you can send them is only 8 bits each, for 16
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* bits total, so these IRQLs are masking off a phantom PIC.
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*/
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0b11111111100000000000000000000000, /* IRQL 4 */
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0b11111111110000000000000000000000, /* IRQL 5 */
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0b11111111111000000000000000000000, /* IRQL 6 */
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0b11111111111100000000000000000000, /* IRQL 7 */
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0b11111111111110000000000000000000, /* IRQL 8 */
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0b11111111111111000000000000000000, /* IRQL 9 */
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0b11111111111111100000000000000000, /* IRQL 10 */
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0b11111111111111110000000000000000, /* IRQL 11 */
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/*
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* Okay, now we're finally starting to mask off IRQs on the slave PIC, from
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* IRQ15 to IRQ8. This means the higher-level IRQs get less priority in the
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* IRQL sense.
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*/
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0b11111111111111111000000000000000, /* IRQL 12 */
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0b11111111111111111100000000000000, /* IRQL 13 */
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0b11111111111111111110000000000000, /* IRQL 14 */
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0b11111111111111111111000000000000, /* IRQL 15 */
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0b11111111111111111111100000000000, /* IRQL 16 */
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0b11111111111111111111110000000000, /* IRQL 17 */
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0b11111111111111111111111000000000, /* IRQL 18 */
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0b11111111111111111111111000000000, /* IRQL 19 */
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/*
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* Now we mask off the IRQs on the master. Notice the 0 "droplet"? You might
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* have also seen that IRQL 18 and 19 are essentially equal as far as the
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* PIC is concerned. That bit is actually IRQ8, which happens to be the RTC.
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* The RTC will keep firing as long as we don't reach PROFILE_LEVEL which
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* actually kills it. The RTC clock (unlike the system clock) is used by the
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* profiling APIs in the HAL, so that explains the logic.
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*/
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0b11111111111111111111111010000000, /* IRQL 20 */
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0b11111111111111111111111011000000, /* IRQL 21 */
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0b11111111111111111111111011100000, /* IRQL 22 */
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0b11111111111111111111111011110000, /* IRQL 23 */
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0b11111111111111111111111011111000, /* IRQL 24 */
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0b11111111111111111111111011111000, /* IRQL 25 */
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0b11111111111111111111111011111010, /* IRQL 26 */
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0b11111111111111111111111111111010, /* IRQL 27 */
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/*
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* IRQL 24 and 25 are actually identical, so IRQL 28 is actually the last
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* IRQL to modify a bit on the master PIC. It happens to modify the very
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* last of the IRQs, IRQ0, which corresponds to the system clock interval
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* timer that keeps track of time (the Windows heartbeat). We only want to
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* turn this off at a high-enough IRQL, which is why IRQLs 24 and 25 are the
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* same to give this guy a chance to come up higher. Note that IRQL 28 is
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* called CLOCK2_LEVEL, which explains the usage we just explained.
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*/
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0b11111111111111111111111111111011, /* IRQL 28 */
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/*
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* We have finished off with the PIC so there's nothing left to mask at the
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* level of these IRQLs, making them only logical IRQLs on x86 machines.
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* Note that we have another 0 "droplet" you might've caught since IRQL 26.
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* In this case, it's the 2nd bit that never gets turned off, which is IRQ2,
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* the cascade IRQ that we use to bridge the slave PIC with the master PIC.
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* We never want to turn it off, so no matter the IRQL, it will be set to 0.
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*/
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0b11111111111111111111111111111011, /* IRQL 29 */
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0b11111111111111111111111111111011, /* IRQL 30 */
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0b11111111111111111111111111111011 /* IRQL 31 */
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};
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/* This table indicates which IRQs, if pending, can preempt a given IRQL level */
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ULONG FindHigherIrqlMask[32] =
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{
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/*
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* Software IRQLs, at these levels all hardware interrupts can preempt.
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* Each higher IRQL simply enables which software IRQL can preempt the
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* current level.
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*/
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0b11111111111111111111111111111110, /* IRQL 0 */
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0b11111111111111111111111111111100, /* IRQL 1 */
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0b11111111111111111111111111111000, /* IRQL 2 */
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/*
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* IRQL3 means only hardware IRQLs can now preempt. These last 4 zeros will
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* then continue throughout the rest of the list, trickling down.
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*/
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0b11111111111111111111111111110000, /* IRQL 3 */
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/*
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* Just like in the previous list, these masks don't really mean anything
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* since we've only got two PICs with 16 possible IRQs total
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*/
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0b00000111111111111111111111110000, /* IRQL 4 */
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0b00000011111111111111111111110000, /* IRQL 5 */
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0b00000001111111111111111111110000, /* IRQL 6 */
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0b00000000111111111111111111110000, /* IRQL 7 */
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0b00000000011111111111111111110000, /* IRQL 8 */
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0b00000000001111111111111111110000, /* IRQL 9 */
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0b00000000000111111111111111110000, /* IRQL 10 */
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/*
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* Now we start progressivly limiting which slave PIC interrupts have the
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* right to preempt us at each level.
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*/
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0b00000000000011111111111111110000, /* IRQL 11 */
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0b00000000000001111111111111110000, /* IRQL 12 */
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0b00000000000000111111111111110000, /* IRQL 13 */
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0b00000000000000011111111111110000, /* IRQL 14 */
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0b00000000000000001111111111110000, /* IRQL 15 */
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0b00000000000000000111111111110000, /* IRQL 16 */
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0b00000000000000000011111111110000, /* IRQL 17 */
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0b00000000000000000001111111110000, /* IRQL 18 */
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0b00000000000000000001111111110000, /* IRQL 19 */
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/*
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* Also recall from the earlier table that IRQL 18/19 are treated the same
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* in order to spread the masks better thoughout the 32 IRQLs and to reflect
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* the fact that some bits will always stay on until much higher IRQLs since
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* they are system-critical. One such example is the 1 bit that you start to
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* see trickling down here. This is IRQ8, the RTC timer used for profiling,
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* so it will always preempt until we reach PROFILE_LEVEL.
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*/
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0b00000000000000000001011111110000, /* IRQL 20 */
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0b00000000000000000001001111110000, /* IRQL 21 */
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0b00000000000000000001000111110000, /* IRQL 22 */
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0b00000000000000000001000011110000, /* IRQL 23 */
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0b00000000000000000001000001110000, /* IRQL 24 */
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0b00000000000000000001000000110000, /* IRQL 25 */
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0b00000000000000000001000000010000, /* IRQL 26 */
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/* At this point, only the clock (IRQ0) can still preempt... */
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0b00000000000000000000000000010000, /* IRQL 27 */
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/* And any higher than that there's no relation with hardware PICs anymore */
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0b00000000000000000000000000000000, /* IRQL 28 */
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0b00000000000000000000000000000000, /* IRQL 29 */
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0b00000000000000000000000000000000, /* IRQL 30 */
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0b00000000000000000000000000000000 /* IRQL 31 */
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};
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