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https://github.com/reactos/reactos.git
synced 2024-08-02 09:30:55 +00:00
441 lines
13 KiB
C
441 lines
13 KiB
C
/*
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*
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*/
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#ifndef __INTERNAL_HAL_HAL_H
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#define __INTERNAL_HAL_HAL_H
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#define HAL_APC_REQUEST 0
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#define HAL_DPC_REQUEST 1
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/* display.c */
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VOID FASTCALL HalInitializeDisplay (PLOADER_PARAMETER_BLOCK LoaderBlock);
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VOID FASTCALL HalClearDisplay (UCHAR CharAttribute);
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/* adapter.c */
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PADAPTER_OBJECT STDCALL HalpAllocateAdapterEx(ULONG NumberOfMapRegisters,BOOLEAN IsMaster, BOOLEAN Dma32BitAddresses);
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/* bus.c */
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VOID HalpInitBusHandlers (VOID);
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/* irql.c */
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VOID HalpInitPICs(VOID);
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/* udelay.c */
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VOID HalpCalibrateStallExecution(VOID);
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/* pci.c */
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VOID HalpInitPciBus (VOID);
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/* enum.c */
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VOID HalpStartEnumerator (VOID);
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/* dma.c */
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VOID HalpInitDma (VOID);
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/* mem.c */
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PVOID HalpMapPhysMemory(ULONG PhysAddr, ULONG Size);
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/* Non-generic initialization */
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VOID HalpInitPhase0 (VOID);
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/* DMA Page Register Structure
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080 DMA RESERVED
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081 DMA Page Register (channel 2)
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082 DMA Page Register (channel 3)
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083 DMA Page Register (channel 1)
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084 DMA RESERVED
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085 DMA RESERVED
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086 DMA RESERVED
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087 DMA Page Register (channel 0)
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088 DMA RESERVED
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089 PS/2-DMA Page Register (channel 6)
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08A PS/2-DMA Page Register (channel 7)
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08B PS/2-DMA Page Register (channel 5)
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08C PS/2-DMA RESERVED
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08D PS/2-DMA RESERVED
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08E PS/2-DMA RESERVED
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08F PS/2-DMA Page Register (channel 4)
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*/
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typedef struct _DMA_PAGE{
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UCHAR Reserved1;
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UCHAR Channel2;
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UCHAR Channel3;
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UCHAR Channel1;
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UCHAR Reserved2[3];
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UCHAR Channel0;
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UCHAR Reserved3;
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UCHAR Channel6;
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UCHAR Channel7;
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UCHAR Channel5;
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UCHAR Reserved4[3];
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UCHAR Channel4;
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} DMA_PAGE, *PDMA_PAGE;
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/* DMA Channel Mask Register Structure
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MSB LSB
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x x x x x x x x
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------------------- - -----
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| | | 00 - Select channel 0 mask bit
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| | \---- 01 - Select channel 1 mask bit
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| | 10 - Select channel 2 mask bit
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| | 11 - Select channel 3 mask bit
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| |
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| \---------- 0 - Clear mask bit
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| 1 - Set mask bit
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\----------------------- xx - Reserved
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*/
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typedef struct _DMA_CHANNEL_MASK {
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UCHAR Channel : 2;
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UCHAR SetMask : 1;
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UCHAR Reserved : 5;
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} DMA_CHANNEL_MASK, *PDMA_CHANNEL_MASK;
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/* DMA Mask Register Structure
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MSB LSB
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x x x x x x x x
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\---/ - - ----- -----
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| | | | | 00 - Channel 0 select
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| | | | \---- 01 - Channel 1 select
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| | | | 10 - Channel 2 select
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| | | | 11 - Channel 3 select
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| | | | 00 - Verify transfer
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| | | \------------ 01 - Write transfer
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| | | 10 - Read transfer
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| | |
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| | \-------------------- 0 - Autoinitialized
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| | 1 - Non-autoinitialized
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| |
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| \------------------------ 0 - Address increment select
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| 00 - Demand mode
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\------------------------------ 01 - Single mode
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10 - Block mode
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11 - Cascade mode
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*/
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typedef struct _DMA_MODE {
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UCHAR Channel : 2;
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UCHAR TransferType : 2;
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UCHAR AutoInitialize : 1;
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UCHAR AddressDecrement : 1;
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UCHAR RequestMode : 2;
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} DMA_MODE, *PDMA_MODE;
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/* DMA Extended Mode Register Structure
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MSB LSB
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x x x x x x x x
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- - ----- ----- -----
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| | | | | 00 - Channel 0 select
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| | | | \---- 01 - Channel 1 select
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| | | | 10 - Channel 2 select
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| | | | 11 - Channel 3 select
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| | | |
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| | | | 00 - 8-bit I/O, by bytes
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| | | \------------ 01 - 16-bit I/O, by words, address shifted
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| | | 10 - 32-bit I/O, by bytes
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| | | 11 - 16-bit I/O, by bytes
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| | |
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| | \---------------------- 00 - Compatible
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| | 01 - Type A
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| | 10 - Type B
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| | 11 - Burst
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| \---------------------------- 0 - Terminal Count is Output
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\---------------------------------0 - Disable Stop Register
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1 - Enable Stop Register
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*/
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typedef struct _DMA_EXTENDED_MODE {
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UCHAR ChannelNumber : 2;
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UCHAR TransferSize : 2;
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UCHAR TimingMode : 2;
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UCHAR TerminalCountIsOutput : 1;
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UCHAR EnableStopRegister : 1;
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}DMA_EXTENDED_MODE, *PDMA_EXTENDED_MODE;
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/* DMA Extended Mode Register Transfer Sizes */
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#define B_8BITS 0
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#define W_16BITS 1
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#define B_32BITS 2
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#define B_16BITS 3
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/* DMA Extended Mode Register Timing */
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#define COMPATIBLE_TIMING 0
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#define TYPE_A_TIMING 1
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#define TYPE_B_TIMING 2
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#define BURST_TIMING 3
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/* Channel Stop Registers for each Channel */
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typedef struct _DMA_CHANNEL_STOP {
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UCHAR ChannelLow;
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UCHAR ChannelMid;
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UCHAR ChannelHigh;
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UCHAR Reserved;
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} DMA_CHANNEL_STOP, *PDMA_CHANNEL_STOP;
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/* Transfer Types */
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#define VERIFY_TRANSFER 0x00
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#define READ_TRANSFER 0x01
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#define WRITE_TRANSFER 0x02
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/* Request Modes */
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#define DEMAND_REQUEST_MODE 0x00
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#define SINGLE_REQUEST_MODE 0x01
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#define BLOCK_REQUEST_MODE 0x02
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#define CASCADE_REQUEST_MODE 0x03
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#define DMA_SETMASK 4
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#define DMA_CLEARMASK 0
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#define DMA_READ 4
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#define DMA_WRITE 8
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#define DMA_SINGLE_TRANSFER 0x40
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#define DMA_AUTO_INIT 0x10
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typedef struct _DMA1_ADDRESS_COUNT {
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UCHAR DmaBaseAddress;
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UCHAR DmaBaseCount;
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} DMA1_ADDRESS_COUNT, *PDMA1_ADDRESS_COUNT;
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typedef struct _DMA2_ADDRESS_COUNT {
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UCHAR DmaBaseAddress;
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UCHAR Reserved1;
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UCHAR DmaBaseCount;
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UCHAR Reserved2;
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} DMA2_ADDRESS_COUNT, *PDMA2_ADDRESS_COUNT;
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typedef struct _DMA1_CONTROL {
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DMA1_ADDRESS_COUNT DmaAddressCount[4];
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UCHAR DmaStatus;
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UCHAR DmaRequest;
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UCHAR SingleMask;
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UCHAR Mode;
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UCHAR ClearBytePointer;
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UCHAR MasterClear;
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UCHAR ClearMask;
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UCHAR AllMask;
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} DMA1_CONTROL, *PDMA1_CONTROL;
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typedef struct _DMA2_CONTROL {
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DMA2_ADDRESS_COUNT DmaAddressCount[4];
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UCHAR DmaStatus;
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UCHAR Reserved1;
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UCHAR DmaRequest;
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UCHAR Reserved2;
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UCHAR SingleMask;
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UCHAR Reserved3;
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UCHAR Mode;
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UCHAR Reserved4;
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UCHAR ClearBytePointer;
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UCHAR Reserved5;
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UCHAR MasterClear;
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UCHAR Reserved6;
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UCHAR ClearMask;
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UCHAR Reserved7;
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UCHAR AllMask;
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UCHAR Reserved8;
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} DMA2_CONTROL, *PDMA2_CONTROL;
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/* This Structure Defines the I/O Map of the 82537 Controller
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I've only defined the registers which are likely to be useful to us */
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typedef struct _EISA_CONTROL {
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/* DMA Controller 1 */
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DMA1_CONTROL DmaController1; /* 00h-0Fh */
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UCHAR Reserved1[16]; /* 0Fh-1Fh */
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/* Interrupt Controller 1 (PIC) */
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UCHAR Pic1Operation; /* 20h */
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UCHAR Pic1Interrupt; /* 21h */
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UCHAR Reserved2[30]; /* 22h-3Fh */
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/* Timer */
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UCHAR TimerCounter; /* 40h */
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UCHAR TimerMemoryRefresh; /* 41h */
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UCHAR Speaker; /* 42h */
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UCHAR TimerOperation; /* 43h */
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UCHAR TimerMisc; /* 44h */
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UCHAR Reserved3[2]; /* 45-46h */
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UCHAR TimerCounterControl; /* 47h */
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UCHAR TimerFailSafeCounter; /* 48h */
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UCHAR Reserved4; /* 49h */
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UCHAR TimerCounter2; /* 4Ah */
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UCHAR TimerOperation2; /* 4Bh */
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UCHAR Reserved5[20]; /* 4Ch-5Fh */
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/* NMI / Keyboard / RTC */
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UCHAR Keyboard; /* 60h */
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UCHAR NmiStatus; /* 61h */
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UCHAR Reserved6[14]; /* 62h-6Fh */
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UCHAR NmiEnable; /* 70h */
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UCHAR Reserved7[15]; /* 71h-7Fh */
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/* DMA Page Registers Controller 1 */
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DMA_PAGE DmaController1Pages; /* 80h-8Fh */
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UCHAR Reserved8[16]; /* 90h-9Fh */
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/* Interrupt Controller 2 (PIC) */
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UCHAR Pic2Operation; /* 0A0h */
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UCHAR Pic2Interrupt; /* 0A1h */
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UCHAR Reserved9[30]; /* 0A2h-0BFh */
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/* DMA Controller 2 */
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DMA1_CONTROL DmaController2; /* 0C0h-0DFh */
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/* System Reserved Ports */
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UCHAR SystemReserved[800]; /* 0E0h-3FFh */
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/* Extended DMA Registers, Controller 1 */
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UCHAR DmaHighByteCount1[8]; /* 400h-407h */
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UCHAR Reserved10[2]; /* 408h-409h */
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UCHAR DmaChainMode1; /* 40Ah */
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UCHAR DmaExtendedMode1; /* 40Bh */
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UCHAR DmaBufferControl; /* 40Ch */
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UCHAR Reserved11[84]; /* 40Dh-460h */
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UCHAR ExtendedNmiControl; /* 461h */
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UCHAR NmiCommand; /* 462h */
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UCHAR Reserved12; /* 463h */
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UCHAR BusMaster; /* 464h */
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UCHAR Reserved13[27]; /* 465h-47Fh */
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/* DMA Page Registers Controller 2 */
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DMA_PAGE DmaController2Pages; /* 480h-48Fh */
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UCHAR Reserved14[48]; /* 490h-4BFh */
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/* Extended DMA Registers, Controller 2 */
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UCHAR DmaHighByteCount2[16]; /* 4C0h-4CFh */
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/* Edge/Level Control Registers */
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UCHAR Pic1EdgeLevel; /* 4D0h */
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UCHAR Pic2EdgeLevel; /* 4D1h */
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UCHAR Reserved15[2]; /* 4D2h-4D3h */
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/* Extended DMA Registers, Controller 2 */
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UCHAR DmaChainMode2; /* 4D4h */
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UCHAR Reserved16; /* 4D5h */
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UCHAR DmaExtendedMode2; /* 4D6h */
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UCHAR Reserved17[9]; /* 4D7h-4DFh */
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/* DMA Stop Registers */
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DMA_CHANNEL_STOP DmaChannelStop[8]; /* 4E0h-4FFh */
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} EISA_CONTROL, *PEISA_CONTROL;
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extern ULONG HalpEisaDma;
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extern PADAPTER_OBJECT MasterAdapter;
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EXPORTED ULONG HalpEisaDma;
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EXPORTED PADAPTER_OBJECT MasterAdapter;
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/*
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* ADAPTER_OBJECT - Track a busmaster DMA adapter and its associated resources
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*
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* NOTES:
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* - I've updated this to the Windows Object Defintion.
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*/
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struct _ADAPTER_OBJECT {
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DMA_ADAPTER DmaHeader;
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struct _ADAPTER_OBJECT *MasterAdapter;
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ULONG MapRegistersPerChannel;
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PVOID AdapterBaseVa;
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PVOID MapRegisterBase;
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ULONG NumberOfMapRegisters;
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ULONG CommittedMapRegisters;
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PWAIT_CONTEXT_BLOCK CurrentWcb;
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KDEVICE_QUEUE ChannelWaitQueue;
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PKDEVICE_QUEUE RegisterWaitQueue;
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LIST_ENTRY AdapterQueue;
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ULONG SpinLock;
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PRTL_BITMAP MapRegisters;
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PUCHAR PagePort;
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UCHAR ChannelNumber;
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UCHAR AdapterNumber;
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USHORT DmaPortAddress;
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UCHAR AdapterMode;
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BOOLEAN NeedsMapRegisters;
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BOOLEAN MasterDevice;
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UCHAR Width16Bits;
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UCHAR ScatterGather;
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UCHAR IgnoreCount;
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UCHAR Dma32BitAddresses;
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UCHAR Dma64BitAddresses;
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BOOLEAN LegacyAdapter;
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LIST_ENTRY AdapterList;
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};
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/*
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struct _ADAPTER_OBJECT {
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INTERFACE_TYPE InterfaceType;
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BOOLEAN Master;
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int Channel;
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PVOID PagePort;
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PVOID CountPort;
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PVOID OffsetPort;
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KSPIN_LOCK SpinLock;
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PVOID Buffer;
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BOOLEAN Inuse;
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ULONG AvailableMapRegisters;
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PVOID MapRegisterBase;
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ULONG AllocatedMapRegisters;
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PWAIT_CONTEXT_BLOCK WaitContextBlock;
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KDEVICE_QUEUE DeviceQueue;
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BOOLEAN ScatterGather;
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BOOLEAN DemandMode;
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BOOLEAN AutoInitialize;
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};
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*/
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/* sysinfo.c */
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NTSTATUS STDCALL
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HalpQuerySystemInformation(IN HAL_QUERY_INFORMATION_CLASS InformationClass,
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IN ULONG BufferSize,
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IN OUT PVOID Buffer,
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OUT PULONG ReturnedLength);
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/* Non-standard functions */
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VOID STDCALL
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HalReleaseDisplayOwnership();
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BOOLEAN STDCALL
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HalQueryDisplayOwnership();
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#if defined(__GNUC__)
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#define Ki386SaveFlags(x) __asm__ __volatile__("pushfl ; popl %0":"=g" (x): /* no input */)
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#define Ki386RestoreFlags(x) __asm__ __volatile__("pushl %0 ; popfl": /* no output */ :"g" (x):"memory")
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#define Ki386DisableInterrupts() __asm__ __volatile__("cli\n\t")
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#define Ki386EnableInterrupts() __asm__ __volatile__("sti\n\t")
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#define Ki386HaltProcessor() __asm__ __volatile__("hlt\n\t")
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#define Ki386RdTSC(x) __asm__ __volatile__("rdtsc\n\t" : "=A" (x.u.LowPart), "=d" (x.u.HighPart));
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static inline BYTE Ki386ReadFsByte(ULONG offset)
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{
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BYTE b;
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__asm__ __volatile__("movb %%fs:(%1),%0":"=g" (b):"0" (offset));
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return b;
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}
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static inline VOID Ki386WriteFsByte(ULONG offset, BYTE value)
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{
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__asm__ __volatile__("movb %0,%%fs:(%1)"::"r" (value), "r" (offset));
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}
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#elif defined(_MSC_VER)
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#define Ki386SaveFlags(x) __asm pushfd __asm pop x;
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#define Ki386RestoreFlags(x) __asm push x __asm popfd;
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#define Ki386DisableInterrupts() __asm cli
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#define Ki386EnableInterrupts() __asm sti
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#define Ki386HaltProcessor() __asm hlt
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#else
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#error Unknown compiler for inline assembler
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#endif
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#endif /* __INTERNAL_HAL_HAL_H */
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