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![Amine Khaldi](/assets/img/avatar_default.png)
* Create a branch for some evul shell experiments. svn path=/branches/shell-experiments/; revision=61927
890 lines
21 KiB
C
890 lines
21 KiB
C
/*
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* PROJECT: ReactOS HAL
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* LICENSE: GNU GPL - See COPYING in the top level directory
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* FILE: hal/halx86/generic/apic.c
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* PURPOSE: HAL APIC Management and Control Code
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* PROGRAMMERS: Timo Kreuzer (timo.kreuzer@reactos.org)
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* REFERENCES: http://www.joseflores.com/docs/ExploringIrql.html
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* http://www.codeproject.com/KB/system/soviet_kernel_hack.aspx
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* http://bbs.unixmap.net/thread-2022-1-1.html
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*/
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/* INCLUDES *******************************************************************/
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#include <hal.h>
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#define NDEBUG
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#include <debug.h>
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#include "apic.h"
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void HackEoi(void);
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#ifndef _M_AMD64
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#define APIC_LAZY_IRQL
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#endif
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/* GLOBALS ********************************************************************/
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ULONG ApicVersion;
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UCHAR HalpVectorToIndex[256];
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#ifndef _M_AMD64
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const UCHAR
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HalpIRQLtoTPR[32] =
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{
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0x00, /* 0 PASSIVE_LEVEL */
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0x3d, /* 1 APC_LEVEL */
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0x41, /* 2 DISPATCH_LEVEL */
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0x41, /* 3 \ */
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0x51, /* 4 \ */
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0x61, /* 5 | */
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0x71, /* 6 | */
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0x81, /* 7 | */
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0x91, /* 8 | */
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0xa1, /* 9 | */
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0xb1, /* 10 | */
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0xb1, /* 11 | */
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0xb1, /* 12 | */
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0xb1, /* 13 | */
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0xb1, /* 14 | */
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0xb1, /* 15 DEVICE IRQL */
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0xb1, /* 16 | */
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0xb1, /* 17 | */
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0xb1, /* 18 | */
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0xb1, /* 19 | */
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0xb1, /* 20 | */
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0xb1, /* 21 | */
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0xb1, /* 22 | */
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0xb1, /* 23 | */
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0xb1, /* 24 | */
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0xb1, /* 25 / */
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0xb1, /* 26 / */
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0xc1, /* 27 PROFILE_LEVEL */
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0xd1, /* 28 CLOCK2_LEVEL */
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0xe1, /* 29 IPI_LEVEL */
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0xef, /* 30 POWER_LEVEL */
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0xff, /* 31 HIGH_LEVEL */
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};
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const KIRQL
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HalVectorToIRQL[16] =
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{
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0, /* 00 PASSIVE_LEVEL */
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0xff, /* 10 */
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0xff, /* 20 */
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1, /* 3D APC_LEVEL */
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2, /* 41 DISPATCH_LEVEL */
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4, /* 50 \ */
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5, /* 60 \ */
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6, /* 70 | */
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7, /* 80 DEVICE IRQL */
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8, /* 90 | */
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9, /* A0 / */
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10, /* B0 / */
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27, /* C1 PROFILE_LEVEL */
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28, /* D1 CLOCK2_LEVEL */
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29, /* E1 IPI_LEVEL / EF POWER_LEVEL */
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31, /* FF HIGH_LEVEL */
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};
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#endif
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/* PRIVATE FUNCTIONS **********************************************************/
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ULONG
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FORCEINLINE
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IOApicRead(UCHAR Register)
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{
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/* Select the register, then do the read */
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*(volatile UCHAR *)(IOAPIC_BASE + IOAPIC_IOREGSEL) = Register;
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return *(volatile ULONG *)(IOAPIC_BASE + IOAPIC_IOWIN);
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}
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VOID
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FORCEINLINE
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IOApicWrite(UCHAR Register, ULONG Value)
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{
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/* Select the register, then do the write */
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*(volatile UCHAR *)(IOAPIC_BASE + IOAPIC_IOREGSEL) = Register;
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*(volatile ULONG *)(IOAPIC_BASE + IOAPIC_IOWIN) = Value;
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}
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VOID
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FORCEINLINE
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ApicWriteIORedirectionEntry(
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UCHAR Index,
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IOAPIC_REDIRECTION_REGISTER ReDirReg)
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{
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IOApicWrite(IOAPIC_REDTBL + 2 * Index, ReDirReg.Long0);
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IOApicWrite(IOAPIC_REDTBL + 2 * Index + 1, ReDirReg.Long1);
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}
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IOAPIC_REDIRECTION_REGISTER
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FORCEINLINE
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ApicReadIORedirectionEntry(
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UCHAR Index)
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{
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IOAPIC_REDIRECTION_REGISTER ReDirReg;
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ReDirReg.Long0 = IOApicRead(IOAPIC_REDTBL + 2 * Index);
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ReDirReg.Long1 = IOApicRead(IOAPIC_REDTBL + 2 * Index + 1);
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return ReDirReg;
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}
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VOID
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FORCEINLINE
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ApicRequestInterrupt(IN UCHAR Vector, UCHAR TriggerMode)
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{
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APIC_COMMAND_REGISTER CommandRegister;
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/* Setup the command register */
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CommandRegister.Long0 = 0;
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CommandRegister.Vector = Vector;
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CommandRegister.MessageType = APIC_MT_Fixed;
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CommandRegister.TriggerMode = TriggerMode;
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CommandRegister.DestinationShortHand = APIC_DSH_Self;
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/* Write the low dword to send the interrupt */
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ApicWrite(APIC_ICR0, CommandRegister.Long0);
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}
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VOID
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FORCEINLINE
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ApicSendEOI(void)
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{
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//ApicWrite(APIC_EOI, 0);
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HackEoi();
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}
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KIRQL
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FORCEINLINE
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ApicGetProcessorIrql(VOID)
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{
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/* Read the TPR and convert it to an IRQL */
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return TprToIrql(ApicRead(APIC_PPR));
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}
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KIRQL
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FORCEINLINE
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ApicGetCurrentIrql(VOID)
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{
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#ifdef _M_AMD64
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return (KIRQL)__readcr8();
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#elif defined(APIC_LAZY_IRQL)
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// HACK: some magic to Sync VBox's APIC registers
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ApicRead(APIC_VER);
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/* Return the field in the PCR */
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return (KIRQL)__readfsbyte(FIELD_OFFSET(KPCR, Irql));
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#else
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// HACK: some magic to Sync VBox's APIC registers
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ApicRead(APIC_VER);
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/* Read the TPR and convert it to an IRQL */
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return TprToIrql(ApicRead(APIC_TPR));
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#endif
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}
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VOID
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FORCEINLINE
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ApicSetIrql(KIRQL Irql)
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{
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#ifdef _M_AMD64
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__writecr8(Irql);
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#elif defined(APIC_LAZY_IRQL)
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__writefsbyte(FIELD_OFFSET(KPCR, Irql), Irql);
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#else
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/* Convert IRQL and write the TPR */
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ApicWrite(APIC_TPR, IrqlToTpr(Irql));
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#endif
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}
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#define ApicRaiseIrql ApicSetIrql
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#ifdef APIC_LAZY_IRQL
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VOID
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FORCEINLINE
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ApicLowerIrql(KIRQL Irql)
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{
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__writefsbyte(FIELD_OFFSET(KPCR, Irql), Irql);
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/* Is the new Irql lower than set in the TPR? */
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if (Irql < KeGetPcr()->IRR)
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{
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/* Save the new hard IRQL in the IRR field */
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KeGetPcr()->IRR = Irql;
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/* Need to lower it back */
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ApicWrite(APIC_TPR, IrqlToTpr(Irql));
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}
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}
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#else
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#define ApicLowerIrql ApicSetIrql
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#endif
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UCHAR
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FASTCALL
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HalpIrqToVector(UCHAR Irq)
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{
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IOAPIC_REDIRECTION_REGISTER ReDirReg;
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/* Read low dword of the redirection entry */
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ReDirReg.Long0 = IOApicRead(IOAPIC_REDTBL + 2 * Irq);
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/* Return the vector */
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return (UCHAR)ReDirReg.Vector;
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}
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KIRQL
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FASTCALL
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HalpVectorToIrql(UCHAR Vector)
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{
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return TprToIrql(Vector);
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}
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UCHAR
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FASTCALL
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HalpVectorToIrq(UCHAR Vector)
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{
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return HalpVectorToIndex[Vector];
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}
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VOID
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NTAPI
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HalpSendEOI(VOID)
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{
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ApicSendEOI();
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}
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VOID
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NTAPI
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HalpInitializeLegacyPIC(VOID)
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{
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I8259_ICW1 Icw1;
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I8259_ICW2 Icw2;
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I8259_ICW3 Icw3;
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I8259_ICW4 Icw4;
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/* Initialize ICW1 for master, interval 8, edge-triggered mode with ICW4 */
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Icw1.NeedIcw4 = TRUE;
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Icw1.OperatingMode = Cascade;
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Icw1.Interval = Interval8;
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Icw1.InterruptMode = EdgeTriggered;
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Icw1.Init = TRUE;
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Icw1.InterruptVectorAddress = 0;
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__outbyte(PIC1_CONTROL_PORT, Icw1.Bits);
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/* ICW2 - interrupt vector offset */
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Icw2.Bits = PRIMARY_VECTOR_BASE;
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__outbyte(PIC1_DATA_PORT, Icw2.Bits);
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/* Connect slave to IRQ 2 */
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Icw3.Bits = 0;
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Icw3.SlaveIrq2 = TRUE;
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__outbyte(PIC1_DATA_PORT, Icw3.Bits);
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/* Enable 8086 mode, non-automatic EOI, non-buffered mode, non special fully nested mode */
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Icw4.SystemMode = New8086Mode;
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Icw4.EoiMode = NormalEoi;
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Icw4.BufferedMode = NonBuffered;
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Icw4.SpecialFullyNestedMode = FALSE;
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Icw4.Reserved = 0;
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__outbyte(PIC1_DATA_PORT, Icw4.Bits);
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/* Mask all interrupts */
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__outbyte(PIC1_DATA_PORT, 0xFF);
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/* Initialize ICW1 for slave, interval 8, edge-triggered mode with ICW4 */
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Icw1.NeedIcw4 = TRUE;
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Icw1.InterruptMode = EdgeTriggered;
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Icw1.OperatingMode = Cascade;
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Icw1.Interval = Interval8;
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Icw1.Init = TRUE;
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Icw1.InterruptVectorAddress = 0; /* This is only used in MCS80/85 mode */
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__outbyte(PIC2_CONTROL_PORT, Icw1.Bits);
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/* Set interrupt vector base */
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Icw2.Bits = PRIMARY_VECTOR_BASE + 8;
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__outbyte(PIC2_DATA_PORT, Icw2.Bits);
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/* Slave ID */
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Icw3.Bits = 0;
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Icw3.SlaveId = 2;
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__outbyte(PIC2_DATA_PORT, Icw3.Bits);
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/* Enable 8086 mode, non-automatic EOI, non-buffered mode, non special fully nested mode */
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Icw4.SystemMode = New8086Mode;
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Icw4.EoiMode = NormalEoi;
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Icw4.BufferedMode = NonBuffered;
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Icw4.SpecialFullyNestedMode = FALSE;
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Icw4.Reserved = 0;
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__outbyte(PIC2_DATA_PORT, Icw4.Bits);
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/* Mask all interrupts */
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__outbyte(PIC2_DATA_PORT, 0xFF);
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}
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VOID
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NTAPI
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ApicInitializeLocalApic(ULONG Cpu)
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{
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APIC_BASE_ADRESS_REGISTER BaseRegister;
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APIC_SPURIOUS_INERRUPT_REGISTER SpIntRegister;
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LVT_REGISTER LvtEntry;
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/* Enable the APIC if it wasn't yet */
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BaseRegister.Long = __readmsr(MSR_APIC_BASE);
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BaseRegister.Enable = 1;
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BaseRegister.BootStrapCPUCore = (Cpu == 0);
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__writemsr(MSR_APIC_BASE, BaseRegister.Long);
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/* Set spurious vector and SoftwareEnable to 1 */
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SpIntRegister.Long = ApicRead(APIC_SIVR);
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SpIntRegister.Vector = APIC_SPURIOUS_VECTOR;
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SpIntRegister.SoftwareEnable = 1;
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SpIntRegister.FocusCPUCoreChecking = 0;
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ApicWrite(APIC_SIVR, SpIntRegister.Long);
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/* Read the version and save it globally */
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if (Cpu == 0) ApicVersion = ApicRead(APIC_VER);
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/* Set the mode to flat (max 8 CPUs supported!) */
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ApicWrite(APIC_DFR, APIC_DF_Flat);
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/* Set logical apic ID */
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ApicWrite(APIC_LDR, ApicLogicalId(Cpu) << 24);
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/* Set the spurious ISR */
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KeRegisterInterruptHandler(APIC_SPURIOUS_VECTOR, ApicSpuriousService);
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/* Create a template LVT */
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LvtEntry.Long = 0;
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LvtEntry.Vector = 0xFF;
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LvtEntry.MessageType = APIC_MT_Fixed;
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LvtEntry.DeliveryStatus = 0;
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LvtEntry.RemoteIRR = 0;
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LvtEntry.TriggerMode = APIC_TGM_Edge;
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LvtEntry.Mask = 1;
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LvtEntry.TimerMode = 0;
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/* Initialize and mask LVTs */
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ApicWrite(APIC_TMRLVTR, LvtEntry.Long);
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ApicWrite(APIC_THRMLVTR, LvtEntry.Long);
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ApicWrite(APIC_PCLVTR, LvtEntry.Long);
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ApicWrite(APIC_EXT0LVTR, LvtEntry.Long);
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ApicWrite(APIC_EXT1LVTR, LvtEntry.Long);
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ApicWrite(APIC_EXT2LVTR, LvtEntry.Long);
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ApicWrite(APIC_EXT3LVTR, LvtEntry.Long);
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/* LINT0 */
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LvtEntry.Vector = APIC_SPURIOUS_VECTOR;
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LvtEntry.MessageType = APIC_MT_ExtInt;
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ApicWrite(APIC_LINT0, LvtEntry.Long);
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/* Enable LINT1 (NMI) */
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LvtEntry.Mask = 0;
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LvtEntry.Vector = APIC_NMI_VECTOR;
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LvtEntry.MessageType = APIC_MT_NMI;
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LvtEntry.TriggerMode = APIC_TGM_Level;
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ApicWrite(APIC_LINT1, LvtEntry.Long);
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/* Enable error LVTR */
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LvtEntry.Vector = APIC_ERROR_VECTOR;
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LvtEntry.MessageType = APIC_MT_Fixed;
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ApicWrite(APIC_ERRLVTR, LvtEntry.Long);
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/* Set the IRQL from the PCR */
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ApicSetIrql(KeGetPcr()->Irql);
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#ifdef APIC_LAZY_IRQL
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/* Save the new hard IRQL in the IRR field */
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KeGetPcr()->IRR = KeGetPcr()->Irql;
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#endif
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}
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UCHAR
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NTAPI
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HalpAllocateSystemInterrupt(
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IN UCHAR Irq,
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IN KIRQL Irql)
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{
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IOAPIC_REDIRECTION_REGISTER ReDirReg;
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IN UCHAR Vector;
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/* Start with lowest vector */
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Vector = IrqlToTpr(Irql) & 0xF0;
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/* Find an empty vector */
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while (HalpVectorToIndex[Vector] != 0xFF)
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{
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Vector++;
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/* Check if we went over the edge */
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if (TprToIrql(Vector) > Irql)
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{
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/* Nothing free, return failure */
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return 0;
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}
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}
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/* Save irq in the table */
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HalpVectorToIndex[Vector] = Irq;
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/* Setup a redirection entry */
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ReDirReg.Vector = Vector;
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ReDirReg.DeliveryMode = APIC_MT_LowestPriority;
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ReDirReg.DestinationMode = APIC_DM_Logical;
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ReDirReg.DeliveryStatus = 0;
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ReDirReg.Polarity = 0;
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ReDirReg.RemoteIRR = 0;
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ReDirReg.TriggerMode = APIC_TGM_Edge;
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ReDirReg.Mask = 1;
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ReDirReg.Reserved = 0;
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ReDirReg.Destination = 0;
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/* Initialize entry */
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IOApicWrite(IOAPIC_REDTBL + 2 * Irq, ReDirReg.Long0);
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IOApicWrite(IOAPIC_REDTBL + 2 * Irq + 1, ReDirReg.Long1);
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return Vector;
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}
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VOID
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NTAPI
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ApicInitializeIOApic(VOID)
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{
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PHARDWARE_PTE Pte;
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IOAPIC_REDIRECTION_REGISTER ReDirReg;
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UCHAR Index;
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ULONG Vector;
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/* Map the I/O Apic page */
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Pte = HalAddressToPte(IOAPIC_BASE);
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Pte->PageFrameNumber = IOAPIC_PHYS_BASE / PAGE_SIZE;
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Pte->Valid = 1;
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Pte->Write = 1;
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Pte->Owner = 1;
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Pte->CacheDisable = 1;
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Pte->Global = 1;
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_ReadWriteBarrier();
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/* Setup a redirection entry */
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ReDirReg.Vector = 0xFF;
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ReDirReg.DeliveryMode = APIC_MT_Fixed;
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ReDirReg.DestinationMode = APIC_DM_Physical;
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ReDirReg.DeliveryStatus = 0;
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ReDirReg.Polarity = 0;
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ReDirReg.RemoteIRR = 0;
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ReDirReg.TriggerMode = APIC_TGM_Edge;
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ReDirReg.Mask = 1;
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ReDirReg.Reserved = 0;
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ReDirReg.Destination = 0;
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/* Loop all table entries */
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for (Index = 0; Index < 24; Index++)
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{
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/* Initialize entry */
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IOApicWrite(IOAPIC_REDTBL + 2 * Index, ReDirReg.Long0);
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IOApicWrite(IOAPIC_REDTBL + 2 * Index + 1, ReDirReg.Long1);
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}
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/* Init the vactor to index table */
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for (Vector = 0; Vector <= 255; Vector++)
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{
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HalpVectorToIndex[Vector] = 0xFF;
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}
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// HACK: Allocate all IRQs, should rather do that on demand
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for (Index = 0; Index <= 15; Index++)
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{
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/* Map the IRQs to IRQLs like with the PIC */
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HalpAllocateSystemInterrupt(Index, 27 - Index);
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}
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/* Enable the timer interrupt */
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ReDirReg.Vector = APIC_CLOCK_VECTOR;
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ReDirReg.DeliveryMode = APIC_MT_Fixed;
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ReDirReg.DestinationMode = APIC_DM_Physical;
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ReDirReg.TriggerMode = APIC_TGM_Edge;
|
|
ReDirReg.Mask = 0;
|
|
ReDirReg.Destination = ApicRead(APIC_ID);
|
|
IOApicWrite(IOAPIC_REDTBL + 2 * APIC_CLOCK_INDEX, ReDirReg.Long0);
|
|
|
|
ApicSendEOI();
|
|
}
|
|
|
|
VOID
|
|
NTAPI
|
|
HalpInitializePICs(IN BOOLEAN EnableInterrupts)
|
|
{
|
|
ULONG_PTR EFlags;
|
|
|
|
/* Save EFlags and disable interrupts */
|
|
EFlags = __readeflags();
|
|
_disable();
|
|
|
|
/* Initialize and mask the PIC */
|
|
HalpInitializeLegacyPIC();
|
|
|
|
/* Initialize the I/O APIC */
|
|
ApicInitializeIOApic();
|
|
|
|
/* Manually reserve some vectors */
|
|
HalpVectorToIndex[APIC_CLOCK_VECTOR] = 8;
|
|
HalpVectorToIndex[APC_VECTOR] = 99;
|
|
HalpVectorToIndex[DISPATCH_VECTOR] = 99;
|
|
|
|
/* Set interrupt handlers in the IDT */
|
|
KeRegisterInterruptHandler(APIC_CLOCK_VECTOR, HalpClockInterrupt);
|
|
#ifndef _M_AMD64
|
|
KeRegisterInterruptHandler(APC_VECTOR, HalpApcInterrupt);
|
|
KeRegisterInterruptHandler(DISPATCH_VECTOR, HalpDispatchInterrupt);
|
|
#endif
|
|
|
|
/* Register the vectors for APC and dispatch interrupts */
|
|
HalpRegisterVector(IDT_INTERNAL, 0, APC_VECTOR, APC_LEVEL);
|
|
HalpRegisterVector(IDT_INTERNAL, 0, DISPATCH_VECTOR, DISPATCH_LEVEL);
|
|
|
|
/* Restore interrupt state */
|
|
if (EnableInterrupts) EFlags |= EFLAGS_INTERRUPT_MASK;
|
|
__writeeflags(EFlags);
|
|
}
|
|
|
|
|
|
/* SOFTWARE INTERRUPT TRAPS ***************************************************/
|
|
|
|
#ifndef _M_AMD64
|
|
VOID
|
|
DECLSPEC_NORETURN
|
|
FASTCALL
|
|
HalpApcInterruptHandler(IN PKTRAP_FRAME TrapFrame)
|
|
{
|
|
KPROCESSOR_MODE ProcessorMode;
|
|
KIRQL OldIrql;
|
|
ASSERT(ApicGetProcessorIrql() == APC_LEVEL);
|
|
|
|
/* Enter trap */
|
|
KiEnterInterruptTrap(TrapFrame);
|
|
|
|
#ifdef APIC_LAZY_IRQL
|
|
if (!HalBeginSystemInterrupt(APC_LEVEL, APC_VECTOR, &OldIrql))
|
|
{
|
|
/* "Spurious" interrupt, exit the interrupt */
|
|
KiEoiHelper(TrapFrame);
|
|
}
|
|
#else
|
|
/* Save the old IRQL */
|
|
OldIrql = ApicGetCurrentIrql();
|
|
ASSERT(OldIrql < APC_LEVEL);
|
|
#endif
|
|
|
|
/* Raise to APC_LEVEL */
|
|
ApicRaiseIrql(APC_LEVEL);
|
|
|
|
/* End the interrupt */
|
|
ApicSendEOI();
|
|
|
|
/* Kernel or user APC? */
|
|
if (KiUserTrap(TrapFrame)) ProcessorMode = UserMode;
|
|
else if (TrapFrame->EFlags & EFLAGS_V86_MASK) ProcessorMode = UserMode;
|
|
else ProcessorMode = KernelMode;
|
|
|
|
/* Enable interrupts and call the kernel's APC interrupt handler */
|
|
_enable();
|
|
KiDeliverApc(ProcessorMode, NULL, TrapFrame);
|
|
|
|
/* Disable interrupts */
|
|
_disable();
|
|
|
|
/* Restore the old IRQL */
|
|
ApicLowerIrql(OldIrql);
|
|
|
|
/* Exit the interrupt */
|
|
KiEoiHelper(TrapFrame);
|
|
}
|
|
|
|
VOID
|
|
DECLSPEC_NORETURN
|
|
FASTCALL
|
|
HalpDispatchInterruptHandler(IN PKTRAP_FRAME TrapFrame)
|
|
{
|
|
KIRQL OldIrql;
|
|
ASSERT(ApicGetProcessorIrql() == DISPATCH_LEVEL);
|
|
|
|
/* Enter trap */
|
|
KiEnterInterruptTrap(TrapFrame);
|
|
|
|
#ifdef APIC_LAZY_IRQL
|
|
if (!HalBeginSystemInterrupt(DISPATCH_LEVEL, DISPATCH_VECTOR, &OldIrql))
|
|
{
|
|
/* "Spurious" interrupt, exit the interrupt */
|
|
KiEoiHelper(TrapFrame);
|
|
}
|
|
#else
|
|
/* Get the current IRQL */
|
|
OldIrql = ApicGetCurrentIrql();
|
|
ASSERT(OldIrql < DISPATCH_LEVEL);
|
|
#endif
|
|
|
|
/* Raise to DISPATCH_LEVEL */
|
|
ApicRaiseIrql(DISPATCH_LEVEL);
|
|
|
|
/* End the interrupt */
|
|
ApicSendEOI();
|
|
|
|
/* Enable interrupts and call the kernel's DPC interrupt handler */
|
|
_enable();
|
|
KiDispatchInterrupt();
|
|
_disable();
|
|
|
|
/* Restore the old IRQL */
|
|
ApicLowerIrql(OldIrql);
|
|
|
|
/* Exit the interrupt */
|
|
KiEoiHelper(TrapFrame);
|
|
}
|
|
#endif
|
|
|
|
|
|
/* SOFTWARE INTERRUPTS ********************************************************/
|
|
|
|
|
|
VOID
|
|
FASTCALL
|
|
HalRequestSoftwareInterrupt(IN KIRQL Irql)
|
|
{
|
|
/* Convert irql to vector and request an interrupt */
|
|
ApicRequestInterrupt(IrqlToSoftVector(Irql), APIC_TGM_Edge);
|
|
}
|
|
|
|
VOID
|
|
FASTCALL
|
|
HalClearSoftwareInterrupt(
|
|
IN KIRQL Irql)
|
|
{
|
|
/* Nothing to do */
|
|
}
|
|
|
|
|
|
/* SYSTEM INTERRUPTS **********************************************************/
|
|
|
|
BOOLEAN
|
|
NTAPI
|
|
HalEnableSystemInterrupt(
|
|
IN ULONG Vector,
|
|
IN KIRQL Irql,
|
|
IN KINTERRUPT_MODE InterruptMode)
|
|
{
|
|
IOAPIC_REDIRECTION_REGISTER ReDirReg;
|
|
PKPRCB Prcb = KeGetCurrentPrcb();
|
|
UCHAR Index;
|
|
ASSERT(Irql <= HIGH_LEVEL);
|
|
ASSERT((IrqlToTpr(Irql) & 0xF0) == (Vector & 0xF0));
|
|
|
|
/* Get the irq for this vector */
|
|
Index = HalpVectorToIndex[Vector];
|
|
|
|
/* Check if its valid */
|
|
if (Index == 0xff)
|
|
{
|
|
/* Interrupt is not in use */
|
|
return FALSE;
|
|
}
|
|
|
|
/* Read the redirection entry */
|
|
ReDirReg = ApicReadIORedirectionEntry(Index);
|
|
|
|
/* Check if the interrupt was unused */
|
|
if (ReDirReg.Vector != Vector)
|
|
{
|
|
ReDirReg.Vector = Vector;
|
|
ReDirReg.DeliveryMode = APIC_MT_LowestPriority;
|
|
ReDirReg.DestinationMode = APIC_DM_Logical;
|
|
ReDirReg.Destination = 0;
|
|
}
|
|
|
|
/* Check if the destination is logical */
|
|
if (ReDirReg.DestinationMode == APIC_DM_Logical)
|
|
{
|
|
/* Set the bit for this cpu */
|
|
ReDirReg.Destination |= ApicLogicalId(Prcb->Number);
|
|
}
|
|
|
|
/* Set the trigger mode */
|
|
ReDirReg.TriggerMode = 1 - InterruptMode;
|
|
|
|
/* Now unmask it */
|
|
ReDirReg.Mask = FALSE;
|
|
|
|
/* Write back the entry */
|
|
ApicWriteIORedirectionEntry(Index, ReDirReg);
|
|
|
|
return TRUE;
|
|
}
|
|
|
|
VOID
|
|
NTAPI
|
|
HalDisableSystemInterrupt(
|
|
IN ULONG Vector,
|
|
IN KIRQL Irql)
|
|
{
|
|
IOAPIC_REDIRECTION_REGISTER ReDirReg;
|
|
UCHAR Index;
|
|
ASSERT(Irql <= HIGH_LEVEL);
|
|
ASSERT(Vector < RTL_NUMBER_OF(HalpVectorToIndex));
|
|
|
|
Index = HalpVectorToIndex[Vector];
|
|
|
|
/* Read lower dword of redirection entry */
|
|
ReDirReg.Long0 = IOApicRead(IOAPIC_REDTBL + 2 * Index);
|
|
|
|
/* Mask it */
|
|
ReDirReg.Mask = 1;
|
|
|
|
/* Write back lower dword */
|
|
IOApicWrite(IOAPIC_REDTBL + 2 * Irql, ReDirReg.Long0);
|
|
}
|
|
|
|
#ifndef _M_AMD64
|
|
BOOLEAN
|
|
NTAPI
|
|
HalBeginSystemInterrupt(
|
|
IN KIRQL Irql,
|
|
IN ULONG Vector,
|
|
OUT PKIRQL OldIrql)
|
|
{
|
|
KIRQL CurrentIrql;
|
|
|
|
/* Get the current IRQL */
|
|
CurrentIrql = ApicGetCurrentIrql();
|
|
|
|
#ifdef APIC_LAZY_IRQL
|
|
/* Check if this interrupt is allowed */
|
|
if (CurrentIrql >= Irql)
|
|
{
|
|
IOAPIC_REDIRECTION_REGISTER RedirReg;
|
|
UCHAR Index;
|
|
|
|
/* It is not, set the real Irql in the TPR! */
|
|
ApicWrite(APIC_TPR, IrqlToTpr(CurrentIrql));
|
|
|
|
/* Save the new hard IRQL in the IRR field */
|
|
KeGetPcr()->IRR = CurrentIrql;
|
|
|
|
/* End this interrupt */
|
|
ApicSendEOI();
|
|
|
|
/* Get the irq for this vector */
|
|
Index = HalpVectorToIndex[Vector];
|
|
|
|
/* Check if its valid */
|
|
if (Index != 0xff)
|
|
{
|
|
/* Read the I/O redirection entry */
|
|
RedirReg = ApicReadIORedirectionEntry(Index);
|
|
|
|
/* Re-request the interrupt to be handled later */
|
|
ApicRequestInterrupt(Vector, (UCHAR)RedirReg.TriggerMode);
|
|
}
|
|
else
|
|
{
|
|
/* Re-request the interrupt to be handled later */
|
|
ApicRequestInterrupt(Vector, APIC_TGM_Edge);
|
|
}
|
|
|
|
/* Pretend it was a spurious interrupt */
|
|
return FALSE;
|
|
}
|
|
#endif
|
|
/* Save the current IRQL */
|
|
*OldIrql = CurrentIrql;
|
|
|
|
/* Set the new IRQL */
|
|
ApicRaiseIrql(Irql);
|
|
|
|
/* Turn on interrupts */
|
|
_enable();
|
|
|
|
/* Success */
|
|
return TRUE;
|
|
}
|
|
|
|
VOID
|
|
NTAPI
|
|
HalEndSystemInterrupt(
|
|
IN KIRQL OldIrql,
|
|
IN PKTRAP_FRAME TrapFrame)
|
|
{
|
|
/* Send an EOI */
|
|
ApicSendEOI();
|
|
|
|
/* Restore the old IRQL */
|
|
ApicLowerIrql(OldIrql);
|
|
}
|
|
|
|
|
|
/* IRQL MANAGEMENT ************************************************************/
|
|
|
|
KIRQL
|
|
NTAPI
|
|
KeGetCurrentIrql(VOID)
|
|
{
|
|
/* Read the current TPR and convert it to an IRQL */
|
|
return ApicGetCurrentIrql();
|
|
}
|
|
|
|
VOID
|
|
FASTCALL
|
|
KfLowerIrql(
|
|
IN KIRQL OldIrql)
|
|
{
|
|
#if DBG
|
|
/* Validate correct lower */
|
|
if (OldIrql > ApicGetCurrentIrql())
|
|
{
|
|
/* Crash system */
|
|
KeBugCheck(IRQL_NOT_LESS_OR_EQUAL);
|
|
}
|
|
#endif
|
|
/* Set the new IRQL */
|
|
ApicLowerIrql(OldIrql);
|
|
}
|
|
|
|
KIRQL
|
|
FASTCALL
|
|
KfRaiseIrql(
|
|
IN KIRQL NewIrql)
|
|
{
|
|
KIRQL OldIrql;
|
|
|
|
/* Read the current IRQL */
|
|
OldIrql = ApicGetCurrentIrql();
|
|
#if DBG
|
|
/* Validate correct raise */
|
|
if (OldIrql > NewIrql)
|
|
{
|
|
/* Crash system */
|
|
KeBugCheck(IRQL_NOT_GREATER_OR_EQUAL);
|
|
}
|
|
#endif
|
|
/* Convert the new IRQL to a TPR value and write the register */
|
|
ApicRaiseIrql(NewIrql);
|
|
|
|
/* Return old IRQL */
|
|
return OldIrql;
|
|
}
|
|
|
|
KIRQL
|
|
NTAPI
|
|
KeRaiseIrqlToDpcLevel(VOID)
|
|
{
|
|
return KfRaiseIrql(DISPATCH_LEVEL);
|
|
}
|
|
|
|
KIRQL
|
|
NTAPI
|
|
KeRaiseIrqlToSynchLevel(VOID)
|
|
{
|
|
return KfRaiseIrql(SYNCH_LEVEL);
|
|
}
|
|
|
|
#endif /* !_M_AMD64 */
|
|
|