mirror of
https://github.com/reactos/reactos.git
synced 2024-07-04 03:34:16 +00:00
691 lines
27 KiB
C++
691 lines
27 KiB
C++
/*
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* COPYRIGHT: See COPYING in the top level directory
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* PROJECT: ReactOS Kernel Streaming
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* FILE: drivers/wdm/audio/hdaudbus/fdo.cpp
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* PURPOSE: HDA Driver Entry
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* PROGRAMMER: Johannes Anderwald
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*/
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#include "hdaudbus.h"
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BOOLEAN
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NTAPI
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HDA_InterruptService(
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IN PKINTERRUPT Interrupt,
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IN PVOID ServiceContext)
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{
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PHDA_FDO_DEVICE_EXTENSION DeviceExtension;
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ULONG InterruptStatus, Response, ResponseFlags, Cad;
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UCHAR RirbStatus, CorbStatus;
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USHORT WritePos;
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PHDA_CODEC_ENTRY Codec;
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/* get device extension */
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DeviceExtension = (PHDA_FDO_DEVICE_EXTENSION)ServiceContext;
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ASSERT(DeviceExtension->IsFDO == TRUE);
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// Check if this interrupt is ours
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InterruptStatus = READ_REGISTER_ULONG((PULONG)(DeviceExtension->RegBase + HDAC_INTR_STATUS));
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DPRINT1("HDA_InterruptService %lx\n", InterruptStatus);
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if ((InterruptStatus & INTR_STATUS_GLOBAL) == 0)
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return FALSE;
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// Controller or stream related?
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if (InterruptStatus & INTR_STATUS_CONTROLLER) {
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RirbStatus = READ_REGISTER_UCHAR(DeviceExtension->RegBase + HDAC_RIRB_STATUS);
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CorbStatus = READ_REGISTER_UCHAR(DeviceExtension->RegBase + HDAC_CORB_STATUS);
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// Check for incoming responses
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if (RirbStatus) {
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WRITE_REGISTER_UCHAR(DeviceExtension->RegBase + HDAC_RIRB_STATUS, RirbStatus);
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if (DeviceExtension->RirbLength == 0)
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{
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/* HACK: spurious interrupt */
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return FALSE;
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}
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if ((RirbStatus & RIRB_STATUS_RESPONSE) != 0) {
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WritePos = (READ_REGISTER_USHORT((PUSHORT)(DeviceExtension->RegBase + HDAC_RIRB_WRITE_POS)) + 1) % DeviceExtension->RirbLength;
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for (; DeviceExtension->RirbReadPos != WritePos; DeviceExtension->RirbReadPos = (DeviceExtension->RirbReadPos + 1) % DeviceExtension->RirbLength)
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{
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Response = DeviceExtension->RirbBase[DeviceExtension->RirbReadPos].response;
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ResponseFlags = DeviceExtension->RirbBase[DeviceExtension->RirbReadPos].flags;
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Cad = ResponseFlags & RESPONSE_FLAGS_CODEC_MASK;
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DPRINT1("Response %lx ResponseFlags %lx Cad %lx\n", Response, ResponseFlags, Cad);
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/* get codec */
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Codec = DeviceExtension->Codecs[Cad];
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if (Codec == NULL)
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{
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DPRINT1("hda: response for unknown codec %x Response %x ResponseFlags %x\n", Cad, Response, ResponseFlags);
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continue;
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}
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/* check response count */
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if (Codec->ResponseCount >= MAX_CODEC_RESPONSES)
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{
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DPRINT1("too many responses for codec %x Response %x ResponseFlags %x\n", Cad, Response, ResponseFlags);
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continue;
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}
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// FIXME handle unsolicited responses
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ASSERT((ResponseFlags & RESPONSE_FLAGS_UNSOLICITED) == 0);
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/* store response */
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Codec->Responses[Codec->ResponseCount] = Response;
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Codec->ResponseCount++;
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}
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}
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if ((RirbStatus & RIRB_STATUS_OVERRUN) != 0)
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DPRINT1("hda: RIRB Overflow\n");
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}
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// Check for sending errors
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if (CorbStatus) {
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WRITE_REGISTER_UCHAR(DeviceExtension->RegBase + HDAC_CORB_STATUS, CorbStatus);
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if ((CorbStatus & CORB_STATUS_MEMORY_ERROR) != 0)
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DPRINT1("hda: CORB Memory Error!\n");
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}
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}
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#if 0
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if ((intrStatus & INTR_STATUS_STREAM_MASK) != 0) {
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for (uint32 index = 0; index < HDA_MAX_STREAMS; index++) {
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if ((intrStatus & (1 << index)) != 0) {
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if (controller->streams[index]) {
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if (stream_handle_interrupt(controller,
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controller->streams[index], index)) {
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handled = B_INVOKE_SCHEDULER;
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}
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}
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else {
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dprintf("hda: Stream interrupt for unconfigured stream "
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"%ld!\n", index);
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}
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}
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}
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}
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#endif
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return TRUE;
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}
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VOID
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HDA_SendVerbs(
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IN PDEVICE_OBJECT DeviceObject,
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IN PHDA_CODEC_ENTRY Codec,
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IN PULONG Verbs,
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OUT PULONG Responses,
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IN ULONG Count)
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{
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PHDA_FDO_DEVICE_EXTENSION DeviceExtension;
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ULONG Sent = 0, ReadPosition, WritePosition, Queued;
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/* get device extension */
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DeviceExtension = (PHDA_FDO_DEVICE_EXTENSION)DeviceObject->DeviceExtension;
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ASSERT(DeviceExtension->IsFDO);
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/* reset response count */
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Codec->ResponseCount = 0;
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while (Sent < Count) {
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ReadPosition = READ_REGISTER_USHORT((PUSHORT)(DeviceExtension->RegBase + HDAC_CORB_READ_POS));
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Queued = 0;
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while (Sent < Count) {
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WritePosition = (DeviceExtension->CorbWritePos + 1) % DeviceExtension->CorbLength;
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if (WritePosition == ReadPosition) {
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// There is no space left in the ring buffer; execute the
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// queued commands and wait until
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break;
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}
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DeviceExtension->CorbBase[WritePosition] = Verbs[Sent++];
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DeviceExtension->CorbWritePos = WritePosition;
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// FIXME HACK
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// do proper synchronization
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WRITE_REGISTER_USHORT((PUSHORT)(DeviceExtension->RegBase + HDAC_CORB_WRITE_POS), DeviceExtension->CorbWritePos);
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KeStallExecutionProcessor(30);
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Queued++;
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}
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WRITE_REGISTER_USHORT((PUSHORT)(DeviceExtension->RegBase + HDAC_CORB_WRITE_POS), DeviceExtension->CorbWritePos);
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}
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if (Responses != NULL) {
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memcpy(Responses, Codec->Responses, Codec->ResponseCount * sizeof(ULONG));
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}
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}
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NTSTATUS
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HDA_InitCodec(
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IN PDEVICE_OBJECT DeviceObject,
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IN ULONG codecAddress)
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{
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PHDA_CODEC_ENTRY Entry;
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ULONG verbs[3];
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PHDA_FDO_DEVICE_EXTENSION DeviceExtension;
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CODEC_RESPONSE Response;
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ULONG NodeId, GroupType;
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NTSTATUS Status;
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PHDA_CODEC_AUDIO_GROUP AudioGroup;
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PHDA_PDO_DEVICE_EXTENSION ChildDeviceExtension;
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/* lets allocate the entry */
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Entry = (PHDA_CODEC_ENTRY)AllocateItem(NonPagedPool, sizeof(HDA_CODEC_ENTRY));
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if (!Entry)
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{
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DPRINT1("hda: failed to allocate memory");
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return STATUS_UNSUCCESSFUL;
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}
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/* init codec */
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Entry->Addr = codecAddress;
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/* get device extension */
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DeviceExtension = (PHDA_FDO_DEVICE_EXTENSION)DeviceObject->DeviceExtension;
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/* store codec */
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DeviceExtension->Codecs[codecAddress] = Entry;
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verbs[0] = MAKE_VERB(codecAddress, 0, VID_GET_PARAMETER, PID_VENDOR_ID);
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verbs[1] = MAKE_VERB(codecAddress, 0, VID_GET_PARAMETER, PID_REVISION_ID);
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verbs[2] = MAKE_VERB(codecAddress, 0, VID_GET_PARAMETER, PID_SUB_NODE_COUNT);
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/* get basic info */
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HDA_SendVerbs(DeviceObject, Entry, verbs, (PULONG)&Response, 3);
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/* store codec details */
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Entry->Major = Response.major;
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Entry->Minor = Response.minor;
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Entry->ProductId = Response.device;
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Entry->Revision = Response.revision;
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Entry->Stepping = Response.stepping;
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Entry->VendorId = Response.vendor;
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DPRINT1("hda Codec %ld Vendor: %04lx Product: %04lx, Revision: %lu.%lu.%lu.%lu NodeStart %u NodeCount %u \n", codecAddress, Response.vendor,
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Response.device, Response.major, Response.minor, Response.revision, Response.stepping, Response.start, Response.count);
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for (NodeId = Response.start; NodeId < Response.start + Response.count; NodeId++) {
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/* get function type */
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verbs[0] = MAKE_VERB(codecAddress, NodeId, VID_GET_PARAMETER, PID_FUNCTION_GROUP_TYPE);
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HDA_SendVerbs(DeviceObject, Entry, verbs, &GroupType, 1);
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DPRINT1("NodeId %u GroupType %x\n", NodeId, GroupType);
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if ((GroupType & FUNCTION_GROUP_NODETYPE_MASK) == FUNCTION_GROUP_NODETYPE_AUDIO) {
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AudioGroup = (PHDA_CODEC_AUDIO_GROUP)AllocateItem(NonPagedPool, sizeof(HDA_CODEC_AUDIO_GROUP));
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if (!AudioGroup)
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{
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DPRINT1("hda: insufficient memory\n");
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return STATUS_INSUFFICIENT_RESOURCES;
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}
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/* init audio group */
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AudioGroup->NodeId = NodeId;
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AudioGroup->FunctionGroup = FUNCTION_GROUP_NODETYPE_AUDIO;
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// Found an Audio Function Group!
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DPRINT1("NodeId %x found an audio function group!\n");
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Status = IoCreateDevice(DeviceObject->DriverObject, sizeof(HDA_PDO_DEVICE_EXTENSION), NULL, FILE_DEVICE_SOUND, FILE_AUTOGENERATED_DEVICE_NAME, FALSE, &AudioGroup->ChildPDO);
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if (!NT_SUCCESS(Status))
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{
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FreeItem(AudioGroup);
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DPRINT1("hda failed to create device object %x\n", Status);
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return Status;
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}
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/* init child pdo*/
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ChildDeviceExtension = (PHDA_PDO_DEVICE_EXTENSION)AudioGroup->ChildPDO->DeviceExtension;
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ChildDeviceExtension->IsFDO = FALSE;
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ChildDeviceExtension->Codec = Entry;
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ChildDeviceExtension->AudioGroup = AudioGroup;
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ChildDeviceExtension->FDO = DeviceObject;
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/* setup flags */
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AudioGroup->ChildPDO->Flags |= DO_POWER_PAGABLE;
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AudioGroup->ChildPDO->Flags &= ~DO_DEVICE_INITIALIZING;
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/* add audio group*/
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Entry->AudioGroups[Entry->AudioGroupCount] = AudioGroup;
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Entry->AudioGroupCount++;
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}
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}
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return STATUS_SUCCESS;
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}
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NTSTATUS
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NTAPI
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HDA_InitCorbRirbPos(
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IN PDEVICE_OBJECT DeviceObject)
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{
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PHDA_FDO_DEVICE_EXTENSION DeviceExtension;
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UCHAR corbSize, value, rirbSize;
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PHYSICAL_ADDRESS HighestPhysicalAddress, CorbPhysicalAddress;
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ULONG Index;
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USHORT corbReadPointer, rirbWritePointer, interruptValue, corbControl, rirbControl;
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/* get device extension */
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DeviceExtension = (PHDA_FDO_DEVICE_EXTENSION)DeviceObject->DeviceExtension;
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// Determine and set size of CORB
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corbSize = READ_REGISTER_UCHAR(DeviceExtension->RegBase + HDAC_CORB_SIZE);
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if ((corbSize & CORB_SIZE_CAP_256_ENTRIES) != 0) {
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DeviceExtension->CorbLength = 256;
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value = READ_REGISTER_UCHAR(DeviceExtension->RegBase + HDAC_CORB_SIZE) & HDAC_CORB_SIZE_MASK;
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WRITE_REGISTER_UCHAR(DeviceExtension->RegBase + HDAC_CORB_SIZE, value | CORB_SIZE_256_ENTRIES);
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}
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else if (corbSize & CORB_SIZE_CAP_16_ENTRIES) {
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DeviceExtension->CorbLength = 16;
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value = READ_REGISTER_UCHAR(DeviceExtension->RegBase + HDAC_CORB_SIZE) & HDAC_CORB_SIZE_MASK;
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WRITE_REGISTER_UCHAR(DeviceExtension->RegBase + HDAC_CORB_SIZE, value | CORB_SIZE_16_ENTRIES);
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}
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else if (corbSize & CORB_SIZE_CAP_2_ENTRIES) {
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DeviceExtension->CorbLength = 2;
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value = READ_REGISTER_UCHAR(DeviceExtension->RegBase + HDAC_CORB_SIZE) & HDAC_CORB_SIZE_MASK;
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WRITE_REGISTER_UCHAR(DeviceExtension->RegBase + HDAC_CORB_SIZE, value | CORB_SIZE_2_ENTRIES);
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}
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// Determine and set size of RIRB
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rirbSize = READ_REGISTER_UCHAR(DeviceExtension->RegBase + HDAC_RIRB_SIZE);
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if (rirbSize & RIRB_SIZE_CAP_256_ENTRIES) {
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DeviceExtension->RirbLength = 256;
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value = READ_REGISTER_UCHAR(DeviceExtension->RegBase + HDAC_RIRB_SIZE) & HDAC_RIRB_SIZE_MASK;
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WRITE_REGISTER_UCHAR(DeviceExtension->RegBase + HDAC_RIRB_SIZE, value | RIRB_SIZE_256_ENTRIES);
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}
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else if (rirbSize & RIRB_SIZE_CAP_16_ENTRIES) {
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DeviceExtension->RirbLength = 16;
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value = READ_REGISTER_UCHAR(DeviceExtension->RegBase + HDAC_RIRB_SIZE) & HDAC_RIRB_SIZE_MASK;
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WRITE_REGISTER_UCHAR(DeviceExtension->RegBase + HDAC_RIRB_SIZE, value | RIRB_SIZE_16_ENTRIES);
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}
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else if (rirbSize & RIRB_SIZE_CAP_2_ENTRIES) {
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DeviceExtension->RirbLength = 2;
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value = READ_REGISTER_UCHAR(DeviceExtension->RegBase + HDAC_RIRB_SIZE) & HDAC_RIRB_SIZE_MASK;
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WRITE_REGISTER_UCHAR(DeviceExtension->RegBase + HDAC_RIRB_SIZE, value | RIRB_SIZE_2_ENTRIES);
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}
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/* init corb */
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HighestPhysicalAddress.QuadPart = 0x00000000FFFFFFFF;
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DeviceExtension->CorbBase = (PULONG)MmAllocateContiguousMemory(PAGE_SIZE * 3, HighestPhysicalAddress);
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ASSERT(DeviceExtension->CorbBase != NULL);
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// FIXME align rirb 128bytes
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ASSERT(DeviceExtension->CorbLength == 256);
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ASSERT(DeviceExtension->RirbLength == 256);
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CorbPhysicalAddress = MmGetPhysicalAddress(DeviceExtension->CorbBase);
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ASSERT(CorbPhysicalAddress.QuadPart != 0LL);
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// Program CORB/RIRB for these locations
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WRITE_REGISTER_ULONG((PULONG)(DeviceExtension->RegBase + HDAC_CORB_BASE_LOWER), CorbPhysicalAddress.LowPart);
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WRITE_REGISTER_ULONG((PULONG)(DeviceExtension->RegBase + HDAC_CORB_BASE_UPPER), CorbPhysicalAddress.HighPart);
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DeviceExtension->RirbBase = (PRIRB_RESPONSE)((ULONG_PTR)DeviceExtension->CorbBase + PAGE_SIZE);
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CorbPhysicalAddress.QuadPart += PAGE_SIZE;
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WRITE_REGISTER_ULONG((PULONG)(DeviceExtension->RegBase + HDAC_RIRB_BASE_LOWER), CorbPhysicalAddress.LowPart);
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WRITE_REGISTER_ULONG((PULONG)(DeviceExtension->RegBase + HDAC_RIRB_BASE_UPPER), CorbPhysicalAddress.HighPart);
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// Program DMA position update
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DeviceExtension->StreamPositions = (PVOID)((ULONG_PTR)DeviceExtension->RirbBase + PAGE_SIZE);
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CorbPhysicalAddress.QuadPart += PAGE_SIZE;
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WRITE_REGISTER_ULONG((PULONG)(DeviceExtension->RegBase + HDAC_DMA_POSITION_BASE_LOWER), CorbPhysicalAddress.LowPart);
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WRITE_REGISTER_ULONG((PULONG)(DeviceExtension->RegBase + HDAC_DMA_POSITION_BASE_UPPER), CorbPhysicalAddress.HighPart);
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value = READ_REGISTER_USHORT((PUSHORT)(DeviceExtension->RegBase + HDAC_CORB_WRITE_POS)) & HDAC_CORB_WRITE_POS_MASK;
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WRITE_REGISTER_USHORT((PUSHORT)(DeviceExtension->RegBase + HDAC_CORB_WRITE_POS), value);
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// Reset CORB read pointer. Preserve bits marked as RsvdP.
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// After setting the reset bit, we must wait for the hardware
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// to acknowledge it, then manually unset it and wait for that
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// to be acknowledged as well.
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corbReadPointer = READ_REGISTER_USHORT((PUSHORT)(DeviceExtension->RegBase + HDAC_CORB_READ_POS));
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corbReadPointer |= CORB_READ_POS_RESET;
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WRITE_REGISTER_USHORT((PUSHORT)(DeviceExtension->RegBase + HDAC_CORB_READ_POS), corbReadPointer);
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for (Index = 0; Index < 100; Index++) {
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KeStallExecutionProcessor(10);
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corbReadPointer = READ_REGISTER_USHORT((PUSHORT)(DeviceExtension->RegBase + HDAC_CORB_READ_POS));
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if ((corbReadPointer & CORB_READ_POS_RESET) != 0)
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break;
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}
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if ((corbReadPointer & CORB_READ_POS_RESET) == 0) {
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DPRINT1("hda: CORB read pointer reset not acknowledged\n");
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// According to HDA spec v1.0a ch3.3.21, software must read the
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// bit as 1 to verify that the reset completed. However, at least
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// some nVidia HDA controllers do not update the bit after reset.
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// Thus don't fail here on nVidia controllers.
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//if (controller->pci_info.vendor_id != PCI_VENDOR_NVIDIA)
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// return B_BUSY;
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}
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corbReadPointer &= ~CORB_READ_POS_RESET;
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WRITE_REGISTER_USHORT((PUSHORT)(DeviceExtension->RegBase + HDAC_CORB_READ_POS), corbReadPointer);
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for (Index = 0; Index < 10; Index++) {
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KeStallExecutionProcessor(10);
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corbReadPointer = READ_REGISTER_USHORT((PUSHORT)(DeviceExtension->RegBase + HDAC_CORB_READ_POS));
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if ((corbReadPointer & CORB_READ_POS_RESET) == 0)
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break;
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}
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if ((corbReadPointer & CORB_READ_POS_RESET) != 0) {
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DPRINT1("hda: CORB read pointer reset failed\n");
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return STATUS_UNSUCCESSFUL;
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}
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// Reset RIRB write pointer
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rirbWritePointer = READ_REGISTER_USHORT((PUSHORT)(DeviceExtension->RegBase + HDAC_RIRB_WRITE_POS)) & RIRB_WRITE_POS_RESET;
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WRITE_REGISTER_USHORT((PUSHORT)(DeviceExtension->RegBase + HDAC_RIRB_WRITE_POS), rirbWritePointer | RIRB_WRITE_POS_RESET);
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// Generate interrupt for every response
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interruptValue = READ_REGISTER_USHORT((PUSHORT)(DeviceExtension->RegBase + HDAC_RESPONSE_INTR_COUNT)) & HDAC_RESPONSE_INTR_COUNT_MASK;
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WRITE_REGISTER_USHORT((PUSHORT)(DeviceExtension->RegBase + HDAC_RESPONSE_INTR_COUNT), interruptValue | 1);
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// Setup cached read/write indices
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DeviceExtension->RirbReadPos = 1;
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DeviceExtension->CorbWritePos = 0;
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// Gentlemen, start your engines...
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corbControl = READ_REGISTER_USHORT((PUSHORT)(DeviceExtension->RegBase + HDAC_CORB_CONTROL)) &HDAC_CORB_CONTROL_MASK;
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WRITE_REGISTER_USHORT((PUSHORT)(DeviceExtension->RegBase + HDAC_CORB_CONTROL), corbControl | CORB_CONTROL_RUN | CORB_CONTROL_MEMORY_ERROR_INTR);
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rirbControl = READ_REGISTER_USHORT((PUSHORT)(DeviceExtension->RegBase + HDAC_RIRB_CONTROL)) & HDAC_RIRB_CONTROL_MASK;
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WRITE_REGISTER_USHORT((PUSHORT)(DeviceExtension->RegBase + HDAC_RIRB_CONTROL), rirbControl | RIRB_CONTROL_DMA_ENABLE | RIRB_CONTROL_OVERRUN_INTR | RIRB_CONTROL_RESPONSE_INTR);
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return STATUS_SUCCESS;
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}
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NTSTATUS
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NTAPI
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HDA_ResetController(
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IN PDEVICE_OBJECT DeviceObject)
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{
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USHORT ValCapabilities;
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ULONG Index;
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PHDA_FDO_DEVICE_EXTENSION DeviceExtension;
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ULONG InputStreams, OutputStreams, BiDirStreams, Control;
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UCHAR corbControl, rirbControl;
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/* get device extension */
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DeviceExtension = (PHDA_FDO_DEVICE_EXTENSION)DeviceObject->DeviceExtension;
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/* read caps */
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ValCapabilities = READ_REGISTER_USHORT((PUSHORT)(DeviceExtension->RegBase + HDAC_GLOBAL_CAP));
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InputStreams = GLOBAL_CAP_INPUT_STREAMS(ValCapabilities);
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OutputStreams = GLOBAL_CAP_OUTPUT_STREAMS(ValCapabilities);
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BiDirStreams = GLOBAL_CAP_BIDIR_STREAMS(ValCapabilities);
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DPRINT1("NumInputStreams %u\n", InputStreams);
|
|
DPRINT1("NumOutputStreams %u\n", OutputStreams);
|
|
DPRINT1("NumBiDirStreams %u\n", BiDirStreams);
|
|
|
|
/* stop all streams */
|
|
for (Index = 0; Index < InputStreams; Index++)
|
|
{
|
|
WRITE_REGISTER_UCHAR(DeviceExtension->RegBase + HDAC_STREAM_CONTROL0 + HDAC_STREAM_BASE + HDAC_INPUT_STREAM_OFFSET(Index), 0);
|
|
WRITE_REGISTER_UCHAR(DeviceExtension->RegBase + HDAC_STREAM_STATUS + HDAC_STREAM_BASE + HDAC_INPUT_STREAM_OFFSET(Index), 0);
|
|
}
|
|
|
|
for (Index = 0; Index < OutputStreams; Index++) {
|
|
WRITE_REGISTER_UCHAR(DeviceExtension->RegBase + HDAC_STREAM_CONTROL0 + HDAC_STREAM_BASE + HDAC_OUTPUT_STREAM_OFFSET(InputStreams, Index), 0);
|
|
WRITE_REGISTER_UCHAR(DeviceExtension->RegBase + HDAC_STREAM_STATUS + HDAC_STREAM_BASE + HDAC_OUTPUT_STREAM_OFFSET(InputStreams, Index), 0);
|
|
}
|
|
|
|
for (Index = 0; Index < BiDirStreams; Index++) {
|
|
WRITE_REGISTER_UCHAR(DeviceExtension->RegBase + HDAC_STREAM_CONTROL0 + HDAC_STREAM_BASE + HDAC_BIDIR_STREAM_OFFSET(InputStreams, OutputStreams, Index), 0);
|
|
WRITE_REGISTER_UCHAR(DeviceExtension->RegBase + HDAC_STREAM_STATUS + HDAC_STREAM_BASE + HDAC_BIDIR_STREAM_OFFSET(InputStreams, OutputStreams, Index), 0);
|
|
}
|
|
|
|
// stop DMA
|
|
Control = READ_REGISTER_UCHAR(DeviceExtension->RegBase + HDAC_CORB_CONTROL) & HDAC_CORB_CONTROL_MASK;
|
|
WRITE_REGISTER_UCHAR(DeviceExtension->RegBase + HDAC_CORB_CONTROL, Control);
|
|
|
|
Control = READ_REGISTER_UCHAR(DeviceExtension->RegBase + HDAC_RIRB_CONTROL) & HDAC_RIRB_CONTROL_MASK;
|
|
WRITE_REGISTER_UCHAR(DeviceExtension->RegBase + HDAC_RIRB_CONTROL, Control);
|
|
|
|
for (int timeout = 0; timeout < 10; timeout++) {
|
|
KeStallExecutionProcessor(10);
|
|
|
|
corbControl = READ_REGISTER_UCHAR(DeviceExtension->RegBase + HDAC_CORB_CONTROL);
|
|
rirbControl = READ_REGISTER_UCHAR(DeviceExtension->RegBase + HDAC_RIRB_CONTROL);
|
|
if (corbControl == 0 && rirbControl == 0)
|
|
break;
|
|
}
|
|
if (corbControl != 0 || rirbControl != 0) {
|
|
DPRINT1("hda: unable to stop dma\n");
|
|
return STATUS_UNSUCCESSFUL;
|
|
}
|
|
|
|
// reset DMA position buffer
|
|
WRITE_REGISTER_ULONG((PULONG)(DeviceExtension->RegBase + HDAC_DMA_POSITION_BASE_LOWER), 0);
|
|
WRITE_REGISTER_ULONG((PULONG)(DeviceExtension->RegBase + HDAC_DMA_POSITION_BASE_UPPER), 0);
|
|
|
|
// Set reset bit - it must be asserted for at least 100us
|
|
Control = READ_REGISTER_ULONG((PULONG)(DeviceExtension->RegBase + HDAC_GLOBAL_CONTROL));
|
|
WRITE_REGISTER_ULONG((PULONG)(DeviceExtension->RegBase + HDAC_GLOBAL_CONTROL), Control & ~GLOBAL_CONTROL_RESET);
|
|
|
|
for (int timeout = 0; timeout < 10; timeout++) {
|
|
KeStallExecutionProcessor(10);
|
|
|
|
Control = READ_REGISTER_ULONG((PULONG)(DeviceExtension->RegBase + HDAC_GLOBAL_CONTROL));
|
|
if ((Control & GLOBAL_CONTROL_RESET) == 0)
|
|
break;
|
|
}
|
|
if ((Control & GLOBAL_CONTROL_RESET) != 0)
|
|
{
|
|
DPRINT1("hda: unable to reset controller\n");
|
|
return STATUS_UNSUCCESSFUL;
|
|
}
|
|
|
|
// Unset reset bit
|
|
Control = READ_REGISTER_ULONG((PULONG)(DeviceExtension->RegBase + HDAC_GLOBAL_CONTROL));
|
|
WRITE_REGISTER_ULONG((PULONG)(DeviceExtension->RegBase + HDAC_GLOBAL_CONTROL), Control | GLOBAL_CONTROL_RESET);
|
|
|
|
for (int timeout = 0; timeout < 10; timeout++) {
|
|
KeStallExecutionProcessor(10);
|
|
|
|
Control = READ_REGISTER_ULONG((PULONG)(DeviceExtension->RegBase + HDAC_GLOBAL_CONTROL));
|
|
if ((Control & GLOBAL_CONTROL_RESET) != 0)
|
|
break;
|
|
}
|
|
if ((Control & GLOBAL_CONTROL_RESET) == 0) {
|
|
DPRINT1("hda: unable to exit reset\n");
|
|
return STATUS_UNSUCCESSFUL;
|
|
}
|
|
|
|
// Wait for codecs to finish their own reset (apparently needs more
|
|
// time than documented in the specs)
|
|
KeStallExecutionProcessor(100);
|
|
|
|
// Enable unsolicited responses
|
|
Control = READ_REGISTER_ULONG((PULONG)(DeviceExtension->RegBase + HDAC_GLOBAL_CONTROL));
|
|
WRITE_REGISTER_ULONG((PULONG)(DeviceExtension->RegBase + HDAC_GLOBAL_CONTROL), Control | GLOBAL_CONTROL_UNSOLICITED);
|
|
|
|
return STATUS_SUCCESS;
|
|
}
|
|
|
|
NTSTATUS
|
|
NTAPI
|
|
HDA_FDOStartDevice(
|
|
IN PDEVICE_OBJECT DeviceObject,
|
|
IN PIRP Irp)
|
|
{
|
|
PIO_STACK_LOCATION IoStack;
|
|
NTSTATUS Status = STATUS_SUCCESS;
|
|
PHDA_FDO_DEVICE_EXTENSION DeviceExtension;
|
|
PCM_RESOURCE_LIST Resources;
|
|
ULONG Index;
|
|
USHORT Value;
|
|
|
|
/* get device extension */
|
|
DeviceExtension = (PHDA_FDO_DEVICE_EXTENSION)DeviceObject->DeviceExtension;
|
|
ASSERT(DeviceExtension->IsFDO == TRUE);
|
|
|
|
/* forward irp to lower device */
|
|
Status = HDA_SyncForwardIrp(DeviceExtension->LowerDevice, Irp);
|
|
if (!NT_SUCCESS(Status))
|
|
{
|
|
// failed to start
|
|
DPRINT1("HDA_StartDevice Lower device failed to start %x\n", Status);
|
|
return Status;
|
|
}
|
|
|
|
/* get current irp stack location */
|
|
IoStack = IoGetCurrentIrpStackLocation(Irp);
|
|
|
|
Resources = IoStack->Parameters.StartDevice.AllocatedResourcesTranslated;
|
|
for (Index = 0; Index < Resources->List[0].PartialResourceList.Count; Index++)
|
|
{
|
|
PCM_PARTIAL_RESOURCE_DESCRIPTOR Descriptor = &Resources->List[0].PartialResourceList.PartialDescriptors[Index];
|
|
|
|
if (Descriptor->Type == CmResourceTypeMemory)
|
|
{
|
|
DeviceExtension->RegBase = (PUCHAR)MmMapIoSpace(Descriptor->u.Memory.Start, Descriptor->u.Memory.Length, MmNonCached);
|
|
if (DeviceExtension->RegBase == NULL)
|
|
{
|
|
DPRINT1("[HDAB] Failed to map registers\n");
|
|
Status = STATUS_UNSUCCESSFUL;
|
|
break;
|
|
}
|
|
}
|
|
else if (Descriptor->Type == CmResourceTypeInterrupt)
|
|
{
|
|
Status = IoConnectInterrupt(&DeviceExtension->Interrupt,
|
|
HDA_InterruptService,
|
|
(PVOID)DeviceExtension,
|
|
NULL,
|
|
Descriptor->u.Interrupt.Vector,
|
|
Descriptor->u.Interrupt.Level,
|
|
Descriptor->u.Interrupt.Level,
|
|
(KINTERRUPT_MODE)(Descriptor->Flags & CM_RESOURCE_INTERRUPT_LATCHED),
|
|
(Descriptor->ShareDisposition != CmResourceShareDeviceExclusive),
|
|
Descriptor->u.Interrupt.Affinity,
|
|
FALSE);
|
|
if (!NT_SUCCESS(Status))
|
|
{
|
|
DPRINT1("[HDAB] Failed to connect interrupt\n");
|
|
break;
|
|
}
|
|
|
|
}
|
|
}
|
|
|
|
if (NT_SUCCESS(Status))
|
|
{
|
|
// Get controller into valid state
|
|
Status = HDA_ResetController(DeviceObject);
|
|
if (!NT_SUCCESS(Status)) return Status;
|
|
|
|
// Setup CORB/RIRB/DMA POS
|
|
Status = HDA_InitCorbRirbPos(DeviceObject);
|
|
if (!NT_SUCCESS(Status)) return Status;
|
|
|
|
|
|
// Don't enable codec state change interrupts. We don't handle
|
|
// them, as we want to use the STATE_STATUS register to identify
|
|
// available codecs. We'd have to clear that register in the interrupt
|
|
// handler to 'ack' the codec change.
|
|
Value = READ_REGISTER_USHORT((PUSHORT)(DeviceExtension->RegBase + HDAC_WAKE_ENABLE)) & ~HDAC_WAKE_ENABLE_MASK;
|
|
WRITE_REGISTER_USHORT((PUSHORT)(DeviceExtension->RegBase + HDAC_WAKE_ENABLE), Value);
|
|
|
|
// Enable controller interrupts
|
|
WRITE_REGISTER_ULONG((PULONG)(DeviceExtension->RegBase + HDAC_INTR_CONTROL), INTR_CONTROL_GLOBAL_ENABLE | INTR_CONTROL_CONTROLLER_ENABLE);
|
|
|
|
KeStallExecutionProcessor(100);
|
|
|
|
Value = READ_REGISTER_USHORT((PUSHORT)(DeviceExtension->RegBase + HDAC_STATE_STATUS));
|
|
if (!Value) {
|
|
DPRINT1("hda: bad codec status\n");
|
|
return STATUS_UNSUCCESSFUL;
|
|
}
|
|
WRITE_REGISTER_USHORT((PUSHORT)(DeviceExtension->RegBase + HDAC_STATE_STATUS), Value);
|
|
|
|
// Create codecs
|
|
DPRINT1("Codecs %lx\n", Value);
|
|
for (Index = 0; Index < HDA_MAX_CODECS; Index++) {
|
|
if ((Value & (1 << Index)) != 0) {
|
|
HDA_InitCodec(DeviceObject, Index);
|
|
}
|
|
}
|
|
}
|
|
|
|
return Status;
|
|
}
|
|
|
|
NTSTATUS
|
|
NTAPI
|
|
HDA_FDOQueryBusRelations(
|
|
IN PDEVICE_OBJECT DeviceObject,
|
|
IN PIRP Irp)
|
|
{
|
|
ULONG DeviceCount, CodecIndex, AFGIndex;
|
|
PHDA_FDO_DEVICE_EXTENSION DeviceExtension;
|
|
PHDA_CODEC_ENTRY Codec;
|
|
PDEVICE_RELATIONS DeviceRelations;
|
|
|
|
/* get device extension */
|
|
DeviceExtension = (PHDA_FDO_DEVICE_EXTENSION)DeviceObject->DeviceExtension;
|
|
ASSERT(DeviceExtension->IsFDO == TRUE);
|
|
|
|
DeviceCount = 0;
|
|
for (CodecIndex = 0; CodecIndex < HDA_MAX_CODECS; CodecIndex++)
|
|
{
|
|
if (DeviceExtension->Codecs[CodecIndex] == NULL)
|
|
continue;
|
|
|
|
Codec = DeviceExtension->Codecs[CodecIndex];
|
|
DeviceCount += Codec->AudioGroupCount;
|
|
}
|
|
|
|
if (DeviceCount == 0)
|
|
return STATUS_UNSUCCESSFUL;
|
|
|
|
DeviceRelations = (PDEVICE_RELATIONS)AllocateItem(NonPagedPool, sizeof(DEVICE_RELATIONS) + (DeviceCount > 1 ? sizeof(PDEVICE_OBJECT) * (DeviceCount - 1) : 0));
|
|
if (!DeviceRelations)
|
|
return STATUS_INSUFFICIENT_RESOURCES;
|
|
|
|
DeviceRelations->Count = 0;
|
|
for (CodecIndex = 0; CodecIndex < HDA_MAX_CODECS; CodecIndex++)
|
|
{
|
|
if (DeviceExtension->Codecs[CodecIndex] == NULL)
|
|
continue;
|
|
|
|
Codec = DeviceExtension->Codecs[CodecIndex];
|
|
for (AFGIndex = 0; AFGIndex < Codec->AudioGroupCount; AFGIndex++)
|
|
{
|
|
DeviceRelations->Objects[DeviceRelations->Count] = Codec->AudioGroups[AFGIndex]->ChildPDO;
|
|
ObReferenceObject(Codec->AudioGroups[AFGIndex]->ChildPDO);
|
|
DeviceRelations->Count++;
|
|
}
|
|
}
|
|
|
|
/* FIXME handle existing device relations */
|
|
ASSERT(Irp->IoStatus.Information == 0);
|
|
|
|
/* store device relations */
|
|
Irp->IoStatus.Information = (ULONG_PTR)DeviceRelations;
|
|
|
|
/* done */
|
|
return STATUS_SUCCESS;
|
|
}
|
|
|
|
|