mirror of
https://github.com/reactos/reactos.git
synced 2024-10-31 11:56:26 +00:00
4f0b8d3db0
svn path=/branches/ntvdm/; revision=59241
643 lines
16 KiB
C
643 lines
16 KiB
C
/*
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* COPYRIGHT: See COPYING in the top level directory
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* PROJECT: ReactOS kernel
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* FILE: hal/halx86/mp/mpconfig.c
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* PURPOSE:
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* PROGRAMMER:
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*/
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/* INCLUDES *****************************************************************/
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#include <hal.h>
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#define NDEBUG
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#include <debug.h>
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/* GLOBALS ******************************************************************/
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MP_FLOATING_POINTER* Mpf = NULL;
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/* FUNCTIONS ****************************************************************/
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static UCHAR
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MPChecksum(PUCHAR Base,
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ULONG Size)
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/*
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* Checksum an MP configuration block
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*/
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{
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UCHAR Sum = 0;
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while (Size--)
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Sum += *Base++;
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return Sum;
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}
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static VOID
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HaliMPIntSrcInfo(PMP_CONFIGURATION_INTSRC m)
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{
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DPRINT("Int: type %d, pol %d, trig %d, bus %d,"
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" IRQ %02x, APIC ID %x, APIC INT %02x\n",
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m->IrqType, m->IrqFlag & 3,
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(m->IrqFlag >> 2) & 3, m->SrcBusId,
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m->SrcBusIrq, m->DstApicId, m->DstApicInt);
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if (IRQCount > MAX_IRQ_SOURCE)
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{
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DPRINT1("Max # of irq sources exceeded!!\n");
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ASSERT(FALSE);
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}
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IRQMap[IRQCount] = *m;
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IRQCount++;
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}
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PCHAR
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HaliMPFamily(ULONG Family,
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ULONG Model)
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{
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static CHAR str[64];
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static PCHAR CPUs[] =
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{
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"80486DX", "80486DX",
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"80486SX", "80486DX/2 or 80487",
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"80486SL", "Intel5X2(tm)",
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"Unknown", "Unknown",
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"80486DX/4"
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};
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if (Family == 0x6)
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return ("Pentium(tm) Pro");
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if (Family == 0x5)
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return ("Pentium(tm)");
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if (Family == 0x0F && Model == 0x0F)
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return("Special controller");
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if (Family == 0x0F && Model == 0x00)
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return("Pentium 4(tm)");
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if (Family == 0x04 && Model < 9)
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return CPUs[Model];
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sprintf(str, "Unknown CPU with family ID %ld and model ID %ld", Family, Model);
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return str;
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}
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static VOID
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HaliMPProcessorInfo(PMP_CONFIGURATION_PROCESSOR m)
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{
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UCHAR ver;
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if (!(m->CpuFlags & CPU_FLAG_ENABLED))
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return;
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DPRINT("Processor #%d %s APIC version %d\n",
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m->ApicId,
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HaliMPFamily((m->FeatureFlags & CPU_FAMILY_MASK) >> 8,
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(m->FeatureFlags & CPU_MODEL_MASK) >> 4),
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m->ApicVersion);
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if (m->FeatureFlags & (1 << 0))
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DPRINT(" Floating point unit present.\n");
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if (m->FeatureFlags & (1 << 7))
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DPRINT(" Machine Exception supported.\n");
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if (m->FeatureFlags & (1 << 8))
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DPRINT(" 64 bit compare & exchange supported.\n");
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if (m->FeatureFlags & (1 << 9))
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DPRINT(" Internal APIC present.\n");
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if (m->FeatureFlags & (1 << 11))
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DPRINT(" SEP present.\n");
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if (m->FeatureFlags & (1 << 12))
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DPRINT(" MTRR present.\n");
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if (m->FeatureFlags & (1 << 13))
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DPRINT(" PGE present.\n");
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if (m->FeatureFlags & (1 << 14))
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DPRINT(" MCA present.\n");
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if (m->FeatureFlags & (1 << 15))
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DPRINT(" CMOV present.\n");
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if (m->FeatureFlags & (1 << 16))
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DPRINT(" PAT present.\n");
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if (m->FeatureFlags & (1 << 17))
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DPRINT(" PSE present.\n");
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if (m->FeatureFlags & (1 << 18))
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DPRINT(" PSN present.\n");
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if (m->FeatureFlags & (1 << 19))
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DPRINT(" Cache Line Flush Instruction present.\n");
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/* 20 Reserved */
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if (m->FeatureFlags & (1 << 21))
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DPRINT(" Debug Trace and EMON Store present.\n");
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if (m->FeatureFlags & (1 << 22))
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DPRINT(" ACPI Thermal Throttle Registers present.\n");
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if (m->FeatureFlags & (1 << 23))
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DPRINT(" MMX present.\n");
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if (m->FeatureFlags & (1 << 24))
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DPRINT(" FXSR present.\n");
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if (m->FeatureFlags & (1 << 25))
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DPRINT(" XMM present.\n");
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if (m->FeatureFlags & (1 << 26))
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DPRINT(" Willamette New Instructions present.\n");
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if (m->FeatureFlags & (1 << 27))
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DPRINT(" Self Snoop present.\n");
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/* 28 Reserved */
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if (m->FeatureFlags & (1 << 29))
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DPRINT(" Thermal Monitor present.\n");
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/* 30, 31 Reserved */
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CPUMap[CPUCount].APICId = m->ApicId;
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CPUMap[CPUCount].Flags = CPU_USABLE;
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if (m->CpuFlags & CPU_FLAG_BSP)
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{
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DPRINT(" Bootup CPU\n");
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CPUMap[CPUCount].Flags |= CPU_BSP;
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BootCPU = m->ApicId;
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}
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if (m->ApicId > MAX_CPU)
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{
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DPRINT("Processor #%d INVALID. (Max ID: %d).\n", m->ApicId, MAX_CPU);
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return;
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}
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ver = m->ApicVersion;
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/*
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* Validate version
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*/
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if (ver == 0x0)
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{
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DPRINT("BIOS bug, APIC version is 0 for CPU#%d! fixing up to 0x10. (tell your hw vendor)\n", m->ApicId);
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ver = 0x10;
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}
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// ApicVersion[m->ApicId] = Ver;
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// BiosCpuApicId[CPUCount] = m->ApicId;
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CPUMap[CPUCount].APICVersion = ver;
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CPUCount++;
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}
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static VOID
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HaliMPBusInfo(PMP_CONFIGURATION_BUS m)
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{
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static UCHAR CurrentPCIBusId = 0;
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DPRINT("Bus #%d is %.*s\n", m->BusId, 6, m->BusType);
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if (strncmp(m->BusType, BUSTYPE_ISA, sizeof(BUSTYPE_ISA)-1) == 0)
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{
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BUSMap[m->BusId] = MP_BUS_ISA;
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}
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else if (strncmp(m->BusType, BUSTYPE_EISA, sizeof(BUSTYPE_EISA)-1) == 0)
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{
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BUSMap[m->BusId] = MP_BUS_EISA;
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}
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else if (strncmp(m->BusType, BUSTYPE_PCI, sizeof(BUSTYPE_PCI)-1) == 0)
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{
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BUSMap[m->BusId] = MP_BUS_PCI;
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PCIBUSMap[m->BusId] = CurrentPCIBusId;
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CurrentPCIBusId++;
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}
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else if (strncmp(m->BusType, BUSTYPE_MCA, sizeof(BUSTYPE_MCA)-1) == 0)
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{
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BUSMap[m->BusId] = MP_BUS_MCA;
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}
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else
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{
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DPRINT("Unknown bustype %.*s - ignoring\n", 6, m->BusType);
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}
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}
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static VOID
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HaliMPIOApicInfo(PMP_CONFIGURATION_IOAPIC m)
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{
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if (!(m->ApicFlags & CPU_FLAG_ENABLED))
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return;
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DPRINT("I/O APIC #%d Version %d at 0x%lX.\n",
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m->ApicId, m->ApicVersion, m->ApicAddress);
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if (IOAPICCount > MAX_IOAPIC)
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{
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DPRINT("Max # of I/O APICs (%d) exceeded (found %d).\n",
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MAX_IOAPIC, IOAPICCount);
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DPRINT1("Recompile with bigger MAX_IOAPIC!.\n");
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ASSERT(FALSE);
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}
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IOAPICMap[IOAPICCount].ApicId = m->ApicId;
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IOAPICMap[IOAPICCount].ApicVersion = m->ApicVersion;
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IOAPICMap[IOAPICCount].ApicAddress = m->ApicAddress;
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IOAPICCount++;
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}
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static VOID
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HaliMPIntLocalInfo(PMP_CONFIGURATION_INTLOCAL m)
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{
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DPRINT("Lint: type %d, pol %d, trig %d, bus %d,"
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" IRQ %02x, APIC ID %x, APIC LINT %02x\n",
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m->IrqType, m->SrcBusIrq & 3,
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(m->SrcBusIrq >> 2) & 3, m->SrcBusId,
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m->SrcBusIrq, m->DstApicId, m->DstApicLInt);
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/*
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* Well it seems all SMP boards in existence
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* use ExtINT/LVT1 == LINT0 and
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* NMI/LVT2 == LINT1 - the following check
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* will show us if this assumptions is false.
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* Until then we do not have to add baggage.
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*/
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if ((m->IrqType == INT_EXTINT) && (m->DstApicLInt != 0))
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{
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DPRINT1("Invalid MP table!\n");
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ASSERT(FALSE);
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}
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if ((m->IrqType == INT_NMI) && (m->DstApicLInt != 1))
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{
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DPRINT1("Invalid MP table!\n");
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ASSERT(FALSE);
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}
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}
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static BOOLEAN
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HaliReadMPConfigTable(PMP_CONFIGURATION_TABLE Table)
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/*
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PARAMETERS:
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Table = Pointer to MP configuration table
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*/
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{
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PUCHAR Entry;
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ULONG Count;
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if (Table->Signature != MPC_SIGNATURE)
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{
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PUCHAR pc = (PUCHAR)&Table->Signature;
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DPRINT1("Bad MP configuration block signature: %c%c%c%c\n",
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pc[0], pc[1], pc[2], pc[3]);
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KeBugCheckEx(HAL_INITIALIZATION_FAILED, pc[0], pc[1], pc[2], pc[3]);
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return FALSE;
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}
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if (MPChecksum((PUCHAR)Table, Table->Length))
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{
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DPRINT1("Bad MP configuration block checksum\n");
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ASSERT(FALSE);
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return FALSE;
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}
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if (Table->Specification != 0x01 && Table->Specification != 0x04)
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{
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DPRINT1("Bad MP configuration table version (%d)\n",
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Table->Specification);
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ASSERT(FALSE);
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return FALSE;
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}
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if (Table->LocalAPICAddress != APIC_DEFAULT_BASE)
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{
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DPRINT1("APIC base address is at 0x%X. I cannot handle non-standard adresses\n",
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Table->LocalAPICAddress);
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ASSERT(FALSE);
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return FALSE;
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}
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DPRINT("Oem: %.*s, ProductId: %.*s\n", 8, Table->Oem, 12, Table->ProductId);
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DPRINT("APIC at: %08x\n", Table->LocalAPICAddress);
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Entry = (PUCHAR)((ULONG_PTR)Table + sizeof(MP_CONFIGURATION_TABLE));
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Count = 0;
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while (Count < (Table->Length - sizeof(MP_CONFIGURATION_TABLE)))
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{
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/* Switch on type */
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switch (*Entry)
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{
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case MPCTE_PROCESSOR:
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{
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HaliMPProcessorInfo((PMP_CONFIGURATION_PROCESSOR)Entry);
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Entry += sizeof(MP_CONFIGURATION_PROCESSOR);
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Count += sizeof(MP_CONFIGURATION_PROCESSOR);
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break;
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}
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case MPCTE_BUS:
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{
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HaliMPBusInfo((PMP_CONFIGURATION_BUS)Entry);
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Entry += sizeof(MP_CONFIGURATION_BUS);
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Count += sizeof(MP_CONFIGURATION_BUS);
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break;
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}
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case MPCTE_IOAPIC:
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{
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HaliMPIOApicInfo((PMP_CONFIGURATION_IOAPIC)Entry);
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Entry += sizeof(MP_CONFIGURATION_IOAPIC);
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Count += sizeof(MP_CONFIGURATION_IOAPIC);
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break;
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}
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case MPCTE_INTSRC:
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{
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HaliMPIntSrcInfo((PMP_CONFIGURATION_INTSRC)Entry);
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Entry += sizeof(MP_CONFIGURATION_INTSRC);
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Count += sizeof(MP_CONFIGURATION_INTSRC);
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break;
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}
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case MPCTE_LINTSRC:
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{
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HaliMPIntLocalInfo((PMP_CONFIGURATION_INTLOCAL)Entry);
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Entry += sizeof(MP_CONFIGURATION_INTLOCAL);
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Count += sizeof(MP_CONFIGURATION_INTLOCAL);
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break;
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}
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default:
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DPRINT1("Unknown entry in MPC table\n");
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ASSERT(FALSE);
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return FALSE;
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}
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}
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return TRUE;
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}
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static VOID
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HaliConstructDefaultIOIrqMPTable(ULONG Type)
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{
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MP_CONFIGURATION_INTSRC intsrc;
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UCHAR i;
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intsrc.Type = MPCTE_INTSRC;
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intsrc.IrqFlag = 0; /* conforming */
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intsrc.SrcBusId = 0;
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intsrc.DstApicId = IOAPICMap[0].ApicId;
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intsrc.IrqType = INT_VECTORED;
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for (i = 0; i < 16; i++) {
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switch (Type) {
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case 2:
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if (i == 0 || i == 13)
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continue; /* IRQ0 & IRQ13 not connected */
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/* Fall through */
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default:
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if (i == 2)
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continue; /* IRQ2 is never connected */
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}
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intsrc.SrcBusIrq = i;
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intsrc.DstApicInt = i ? i : 2; /* IRQ0 to INTIN2 */
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HaliMPIntSrcInfo(&intsrc);
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}
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intsrc.IrqType = INT_EXTINT;
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intsrc.SrcBusIrq = 0;
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intsrc.DstApicInt = 0; /* 8259A to INTIN0 */
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HaliMPIntSrcInfo(&intsrc);
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}
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static VOID
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HaliConstructDefaultISAMPTable(ULONG Type)
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{
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MP_CONFIGURATION_PROCESSOR processor;
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MP_CONFIGURATION_BUS bus;
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MP_CONFIGURATION_IOAPIC ioapic;
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MP_CONFIGURATION_INTLOCAL lintsrc;
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UCHAR linttypes[2] = { INT_EXTINT, INT_NMI };
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UCHAR i;
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/*
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* 2 CPUs, numbered 0 & 1.
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*/
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processor.Type = MPCTE_PROCESSOR;
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/* Either an integrated APIC or a discrete 82489DX. */
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processor.ApicVersion = Type > 4 ? 0x10 : 0x01;
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processor.CpuFlags = CPU_FLAG_ENABLED | CPU_FLAG_BSP;
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/* FIXME: Get this from the bootstrap processor */
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processor.CpuSignature = 0;
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processor.FeatureFlags = 0;
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processor.Reserved[0] = 0;
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processor.Reserved[1] = 0;
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for (i = 0; i < 2; i++)
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{
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processor.ApicId = i;
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HaliMPProcessorInfo(&processor);
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processor.CpuFlags &= ~CPU_FLAG_BSP;
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}
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bus.Type = MPCTE_BUS;
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bus.BusId = 0;
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switch (Type)
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{
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default:
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DPRINT("Unknown standard configuration %d\n", Type);
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/* Fall through */
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case 1:
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case 5:
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memcpy(bus.BusType, "ISA ", 6);
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break;
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case 2:
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case 6:
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case 3:
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memcpy(bus.BusType, "EISA ", 6);
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break;
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case 4:
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case 7:
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memcpy(bus.BusType, "MCA ", 6);
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}
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HaliMPBusInfo(&bus);
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if (Type > 4)
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{
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bus.Type = MPCTE_BUS;
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bus.BusId = 1;
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memcpy(bus.BusType, "PCI ", 6);
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HaliMPBusInfo(&bus);
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}
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ioapic.Type = MPCTE_IOAPIC;
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ioapic.ApicId = 2;
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ioapic.ApicVersion = Type > 4 ? 0x10 : 0x01;
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ioapic.ApicFlags = MP_IOAPIC_USABLE;
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ioapic.ApicAddress = IOAPIC_DEFAULT_BASE;
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HaliMPIOApicInfo(&ioapic);
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/*
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* We set up most of the low 16 IO-APIC pins according to MPS rules.
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*/
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HaliConstructDefaultIOIrqMPTable(Type);
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lintsrc.Type = MPCTE_LINTSRC;
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lintsrc.IrqType = 0;
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lintsrc.IrqFlag = 0; /* conforming */
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lintsrc.SrcBusId = 0;
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lintsrc.SrcBusIrq = 0;
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lintsrc.DstApicId = MP_APIC_ALL;
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for (i = 0; i < 2; i++)
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{
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lintsrc.IrqType = linttypes[i];
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lintsrc.DstApicLInt = i;
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HaliMPIntLocalInfo(&lintsrc);
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}
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}
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static BOOLEAN
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HaliScanForMPConfigTable(ULONG Base,
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ULONG Size)
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{
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/*
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PARAMETERS:
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Base = Base address of region
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Size = Length of region to check
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RETURNS:
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TRUE if a valid MP configuration table was found
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*/
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PULONG bp = (PULONG)Base;
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MP_FLOATING_POINTER* mpf;
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UCHAR Checksum;
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while (Size > 0)
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{
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mpf = (MP_FLOATING_POINTER*)bp;
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if (mpf->Signature == MPF_SIGNATURE)
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{
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Checksum = MPChecksum((PUCHAR)bp, 16);
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DPRINT("Found MPF signature at %x, checksum %x\n", bp, Checksum);
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if (Checksum == 0 &&
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mpf->Length == 1)
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{
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DPRINT("Intel MultiProcessor Specification v1.%d compliant system.\n",
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mpf->Specification);
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if (mpf->Feature2 & FEATURE2_IMCRP)
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{
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DPRINT("Running in IMCR and PIC compatibility mode.\n");
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}
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else
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{
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DPRINT("Running in Virtual Wire compatibility mode.\n");
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}
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switch (mpf->Feature1)
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{
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case 0:
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/* Non standard configuration */
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break;
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case 1:
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DPRINT("ISA\n");
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|
break;
|
|
case 2:
|
|
DPRINT("EISA with no IRQ8 chaining\n");
|
|
break;
|
|
case 3:
|
|
DPRINT("EISA\n");
|
|
break;
|
|
case 4:
|
|
DPRINT("MCA\n");
|
|
break;
|
|
case 5:
|
|
DPRINT("ISA and PCI\n");
|
|
break;
|
|
case 6:
|
|
DPRINT("EISA and PCI\n");
|
|
break;
|
|
case 7:
|
|
DPRINT("MCA and PCI\n");
|
|
break;
|
|
default:
|
|
DPRINT("Unknown standard configuration %d\n", mpf->Feature1);
|
|
return FALSE;
|
|
}
|
|
Mpf = mpf;
|
|
return TRUE;
|
|
}
|
|
}
|
|
bp += 4;
|
|
Size -= 16;
|
|
}
|
|
return FALSE;
|
|
}
|
|
|
|
static BOOLEAN
|
|
HaliGetSmpConfig(VOID)
|
|
{
|
|
if (Mpf == NULL)
|
|
{
|
|
return FALSE;
|
|
}
|
|
|
|
if (Mpf->Feature2 & FEATURE2_IMCRP)
|
|
{
|
|
DPRINT("Running in IMCR and PIC compatibility mode.\n");
|
|
APICMode = amPIC;
|
|
}
|
|
else
|
|
{
|
|
DPRINT("Running in Virtual Wire compatibility mode.\n");
|
|
APICMode = amVWIRE;
|
|
}
|
|
|
|
if (Mpf->Feature1 == 0 && Mpf->Address)
|
|
{
|
|
if(!HaliReadMPConfigTable((PMP_CONFIGURATION_TABLE)Mpf->Address))
|
|
{
|
|
DPRINT("BIOS bug, MP table errors detected!...\n");
|
|
DPRINT("... disabling SMP support. (tell your hw vendor)\n");
|
|
return FALSE;
|
|
}
|
|
if (IRQCount == 0)
|
|
{
|
|
MP_CONFIGURATION_BUS bus;
|
|
|
|
DPRINT("BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
|
|
|
|
bus.BusId = 1;
|
|
memcpy(bus.BusType, "ISA ", 6);
|
|
HaliMPBusInfo(&bus);
|
|
HaliConstructDefaultIOIrqMPTable(bus.BusId);
|
|
}
|
|
|
|
}
|
|
else if(Mpf->Feature1 != 0)
|
|
{
|
|
HaliConstructDefaultISAMPTable(Mpf->Feature1);
|
|
}
|
|
else
|
|
{
|
|
ASSERT(FALSE);
|
|
}
|
|
return TRUE;
|
|
}
|
|
|
|
BOOLEAN
|
|
HaliFindSmpConfig(VOID)
|
|
{
|
|
/*
|
|
Scan the system memory for an MP configuration table
|
|
1) Scan the first KB of system base memory
|
|
2) Scan the last KB of system base memory
|
|
3) Scan the BIOS ROM address space between 0F0000h and 0FFFFFh
|
|
4) Scan the first KB from the Extended BIOS Data Area
|
|
*/
|
|
|
|
if (!HaliScanForMPConfigTable(0x0, 0x400))
|
|
{
|
|
if (!HaliScanForMPConfigTable(0x9FC00, 0x400))
|
|
{
|
|
if (!HaliScanForMPConfigTable(0xF0000, 0x10000))
|
|
{
|
|
if (!HaliScanForMPConfigTable(*((PUSHORT)0x040E) << 4, 0x400))
|
|
{
|
|
DPRINT("No multiprocessor compliant system found.\n");
|
|
return FALSE;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
if (HaliGetSmpConfig())
|
|
{
|
|
return TRUE;
|
|
}
|
|
else
|
|
{
|
|
DPRINT("No MP config table found\n");
|
|
return FALSE;
|
|
}
|
|
|
|
}
|
|
|
|
/* EOF */
|