mirror of
https://github.com/reactos/reactos.git
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4f0b8d3db0
svn path=/branches/ntvdm/; revision=59241
1516 lines
38 KiB
C++
1516 lines
38 KiB
C++
/*
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* PROJECT: ReactOS Universal Serial Bus Host Controller Interface
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* LICENSE: GPL - See COPYING in the top level directory
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* FILE: drivers/usb/usbuhci/hcd_controller.cpp
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* PURPOSE: USB UHCI device driver.
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* PROGRAMMERS:
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* Michael Martin (michael.martin@reactos.org)
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* Johannes Anderwald (johannes.anderwald@reactos.org)
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*/
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#define INITGUID
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#include "usbuhci.h"
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#include "hardware.h"
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typedef VOID __stdcall HD_INIT_CALLBACK(IN PVOID CallBackContext);
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BOOLEAN
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NTAPI
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InterruptServiceRoutine(
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IN PKINTERRUPT Interrupt,
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IN PVOID ServiceContext);
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VOID
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NTAPI
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UhciDefferedRoutine(
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IN PKDPC Dpc,
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IN PVOID DeferredContext,
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IN PVOID SystemArgument1,
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IN PVOID SystemArgument2);
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VOID
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NTAPI
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TimerDpcRoutine(
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IN PKDPC Dpc,
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IN PVOID DeferredContext,
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IN PVOID SystemArgument1,
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IN PVOID SystemArgument2);
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VOID
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NTAPI
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StatusChangeWorkItemRoutine(PVOID Context);
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class CUSBHardwareDevice : public IUHCIHardwareDevice
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{
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public:
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STDMETHODIMP QueryInterface( REFIID InterfaceId, PVOID* Interface);
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STDMETHODIMP_(ULONG) AddRef()
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{
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InterlockedIncrement(&m_Ref);
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return m_Ref;
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}
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STDMETHODIMP_(ULONG) Release()
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{
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InterlockedDecrement(&m_Ref);
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if (!m_Ref)
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{
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delete this;
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return 0;
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}
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return m_Ref;
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}
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// com
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IMP_IUSBHARDWAREDEVICE
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IMP_IUHCIHARDWAREDEVICE
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// local
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NTSTATUS StartController();
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NTSTATUS StopController();
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NTSTATUS ResetController();
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VOID GlobalReset();
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BOOLEAN InterruptService();
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NTSTATUS InitializeController();
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// friend function
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friend BOOLEAN NTAPI InterruptServiceRoutine(IN PKINTERRUPT Interrupt, IN PVOID ServiceContext);
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friend VOID NTAPI UhciDefferedRoutine(IN PKDPC Dpc, IN PVOID DeferredContext, IN PVOID SystemArgument1, IN PVOID SystemArgument2);
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friend VOID NTAPI TimerDpcRoutine(IN PKDPC Dpc, IN PVOID DeferredContext, IN PVOID SystemArgument1, IN PVOID SystemArgument2);
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friend VOID NTAPI StatusChangeWorkItemRoutine(PVOID Context);
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VOID WriteRegister8(IN ULONG Register, IN UCHAR value);
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VOID WriteRegister16(ULONG Register, USHORT Value);
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VOID WriteRegister32(ULONG Register, ULONG Value);
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UCHAR ReadRegister8(ULONG Register);
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USHORT ReadRegister16(ULONG Register);
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ULONG ReadRegister32(ULONG Register);
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// constructor / destructor
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CUSBHardwareDevice(IUnknown *OuterUnknown){}
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virtual ~CUSBHardwareDevice(){}
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protected:
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LONG m_Ref; // reference count
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PDRIVER_OBJECT m_DriverObject; // driver object
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PDEVICE_OBJECT m_PhysicalDeviceObject; // pdo
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PDEVICE_OBJECT m_FunctionalDeviceObject; // fdo (hcd controller)
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PDEVICE_OBJECT m_NextDeviceObject; // lower device object
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KSPIN_LOCK m_Lock; // hardware lock
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PKINTERRUPT m_Interrupt; // interrupt object
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KDPC m_IntDpcObject; // dpc object for deferred isr processing
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PVOID VirtualBase; // virtual base for memory manager
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PHYSICAL_ADDRESS PhysicalAddress; // physical base for memory manager
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PULONG m_Base; // UHCI operational port base registers
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PDMA_ADAPTER m_Adapter; // dma adapter object
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ULONG m_MapRegisters; // map registers count
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USHORT m_VendorID; // vendor id
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USHORT m_DeviceID; // device id
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PUHCIQUEUE m_UsbQueue; // usb request queue
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ULONG m_NumberOfPorts; // number of ports
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PDMAMEMORYMANAGER m_MemoryManager; // memory manager
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HD_INIT_CALLBACK* m_SCECallBack; // status change callback routine
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PVOID m_SCEContext; // status change callback routine context
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//WORK_QUEUE_ITEM m_StatusChangeWorkItem; // work item for status change callback
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ULONG m_InterruptMask; // interrupt enabled mask
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ULONG m_PortResetChange; // port reset status
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PULONG m_FrameList; // frame list
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PHYSICAL_ADDRESS m_FrameListPhysicalAddress; // frame list physical address
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PUSHORT m_FrameBandwidth; // frame bandwidth
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PUHCI_QUEUE_HEAD m_QueueHead[5]; // queue heads
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PHYSICAL_ADDRESS m_StrayDescriptorPhysicalAddress; // physical address stray descriptor
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PUHCI_TRANSFER_DESCRIPTOR m_StrayDescriptor; // stray descriptor
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KTIMER m_SCETimer; // SCE timer
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KDPC m_SCETimerDpc; // timer dpc
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};
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//=================================================================================================
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// COM
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//
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NTSTATUS
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STDMETHODCALLTYPE
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CUSBHardwareDevice::QueryInterface(
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IN REFIID refiid,
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OUT PVOID* Output)
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{
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if (IsEqualGUIDAligned(refiid, IID_IUnknown))
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{
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*Output = PVOID(PUNKNOWN(this));
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PUNKNOWN(*Output)->AddRef();
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return STATUS_SUCCESS;
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}
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return STATUS_UNSUCCESSFUL;
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}
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LPCSTR
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STDMETHODCALLTYPE
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CUSBHardwareDevice::GetUSBType()
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{
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return "USBUHCI";
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}
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NTSTATUS
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CUSBHardwareDevice::Initialize(
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PDRIVER_OBJECT DriverObject,
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PDEVICE_OBJECT FunctionalDeviceObject,
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PDEVICE_OBJECT PhysicalDeviceObject,
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PDEVICE_OBJECT LowerDeviceObject)
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{
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BUS_INTERFACE_STANDARD BusInterface;
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PCI_COMMON_CONFIG PciConfig;
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NTSTATUS Status;
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ULONG BytesRead;
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DPRINT1("CUSBHardwareDevice::Initialize\n");
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//
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// Create DMAMemoryManager for use with QueueHeads and Transfer Descriptors.
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//
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Status = CreateDMAMemoryManager(&m_MemoryManager);
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if (!NT_SUCCESS(Status))
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{
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DPRINT1("Failed to create DMAMemoryManager Object\n");
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return Status;
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}
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//
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// Create the UsbQueue class that will handle the Asynchronous and Periodic Schedules
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//
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Status = CreateUSBQueue((PUSBQUEUE*)&m_UsbQueue);
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if (!NT_SUCCESS(Status))
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{
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DPRINT1("Failed to create UsbQueue!\n");
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return Status;
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}
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//
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// store device objects
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//
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m_DriverObject = DriverObject;
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m_FunctionalDeviceObject = FunctionalDeviceObject;
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m_PhysicalDeviceObject = PhysicalDeviceObject;
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m_NextDeviceObject = LowerDeviceObject;
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//
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// initialize device lock
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//
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KeInitializeSpinLock(&m_Lock);
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//
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// intialize status change work item
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//
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//ExInitializeWorkItem(&m_StatusChangeWorkItem, StatusChangeWorkItemRoutine, PVOID(this));
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// initialize timer
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KeInitializeTimer(&m_SCETimer);
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// initialize timer dpc
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KeInitializeDpc(&m_SCETimerDpc, TimerDpcRoutine, PVOID(this));
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m_VendorID = 0;
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m_DeviceID = 0;
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Status = GetBusInterface(PhysicalDeviceObject, &BusInterface);
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if (!NT_SUCCESS(Status))
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{
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DPRINT1("Failed to get BusInteface!\n");
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return Status;
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}
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BytesRead = (*BusInterface.GetBusData)(BusInterface.Context,
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PCI_WHICHSPACE_CONFIG,
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&PciConfig,
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0,
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PCI_COMMON_HDR_LENGTH);
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if (BytesRead != PCI_COMMON_HDR_LENGTH)
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{
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DPRINT1("Failed to get pci config information!\n");
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return STATUS_SUCCESS;
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}
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m_VendorID = PciConfig.VendorID;
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m_DeviceID = PciConfig.DeviceID;
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return STATUS_SUCCESS;
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}
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NTSTATUS
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CUSBHardwareDevice::PnpStart(
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PCM_RESOURCE_LIST RawResources,
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PCM_RESOURCE_LIST TranslatedResources)
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{
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ULONG Index;
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PCM_PARTIAL_RESOURCE_DESCRIPTOR ResourceDescriptor;
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DEVICE_DESCRIPTION DeviceDescription;
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NTSTATUS Status;
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DPRINT1("CUSBHardwareDevice::PnpStart\n");
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for(Index = 0; Index < TranslatedResources->List[0].PartialResourceList.Count; Index++)
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{
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//
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// get resource descriptor
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//
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ResourceDescriptor = &TranslatedResources->List[0].PartialResourceList.PartialDescriptors[Index];
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switch(ResourceDescriptor->Type)
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{
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case CmResourceTypeInterrupt:
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{
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KeInitializeDpc(&m_IntDpcObject,
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UhciDefferedRoutine,
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this);
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Status = IoConnectInterrupt(&m_Interrupt,
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InterruptServiceRoutine,
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(PVOID)this,
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NULL,
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ResourceDescriptor->u.Interrupt.Vector,
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(KIRQL)ResourceDescriptor->u.Interrupt.Level,
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(KIRQL)ResourceDescriptor->u.Interrupt.Level,
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(KINTERRUPT_MODE)(ResourceDescriptor->Flags & CM_RESOURCE_INTERRUPT_LATCHED),
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(ResourceDescriptor->ShareDisposition != CmResourceShareDeviceExclusive),
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ResourceDescriptor->u.Interrupt.Affinity,
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FALSE);
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if (!NT_SUCCESS(Status))
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{
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//
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// failed to register interrupt
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//
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DPRINT1("IoConnect Interrupt failed with %x\n", Status);
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return Status;
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}
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break;
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}
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case CmResourceTypePort:
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{
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//
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// Store Resource base
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//
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m_Base = (PULONG)ResourceDescriptor->u.Port.Start.LowPart; //FIXME
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DPRINT1("UHCI Base %p Length %x\n", m_Base, ResourceDescriptor->u.Port.Length);
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break;
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}
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}
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}
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ASSERT(m_Base);
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//
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// zero device description
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//
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RtlZeroMemory(&DeviceDescription, sizeof(DEVICE_DESCRIPTION));
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//
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// initialize device description
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//
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DeviceDescription.Version = DEVICE_DESCRIPTION_VERSION;
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DeviceDescription.Master = TRUE;
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DeviceDescription.ScatterGather = TRUE;
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DeviceDescription.Dma32BitAddresses = TRUE;
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DeviceDescription.DmaWidth = Width32Bits;
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DeviceDescription.InterfaceType = PCIBus;
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DeviceDescription.MaximumLength = MAXULONG;
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//
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// get dma adapter
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//
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m_Adapter = IoGetDmaAdapter(m_PhysicalDeviceObject, &DeviceDescription, &m_MapRegisters);
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if (!m_Adapter)
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{
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//
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// failed to get dma adapter
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//
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DPRINT1("Failed to acquire dma adapter\n");
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return STATUS_INSUFFICIENT_RESOURCES;
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}
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//
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// Create Common Buffer
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//
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VirtualBase = m_Adapter->DmaOperations->AllocateCommonBuffer(m_Adapter,
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PAGE_SIZE * 4,
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&PhysicalAddress,
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FALSE);
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if (!VirtualBase)
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{
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DPRINT1("Failed to allocate a common buffer\n");
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return STATUS_INSUFFICIENT_RESOURCES;
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}
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//
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// Initialize the DMAMemoryManager
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//
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Status = m_MemoryManager->Initialize(this, &m_Lock, PAGE_SIZE * 4, VirtualBase, PhysicalAddress, 32);
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if (!NT_SUCCESS(Status))
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{
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DPRINT1("Failed to initialize the DMAMemoryManager\n");
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return Status;
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}
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//
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// initializes the controller
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//
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Status = InitializeController();
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if (!NT_SUCCESS(Status))
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{
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DPRINT1("Failed to Initialize the controller \n");
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ASSERT(FALSE);
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return Status;
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}
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//
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// Initialize the UsbQueue now that we have an AdapterObject.
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//
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Status = m_UsbQueue->Initialize(PUSBHARDWAREDEVICE(this), m_Adapter, m_MemoryManager, NULL);
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if (!NT_SUCCESS(Status))
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{
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DPRINT1("Failed to Initialize the UsbQueue\n");
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return Status;
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}
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//
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// Start the controller
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//
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DPRINT1("Starting Controller\n");
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Status = StartController();
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//
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// done
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//
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return Status;
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}
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NTSTATUS
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CUSBHardwareDevice::PnpStop(void)
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{
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UNIMPLEMENTED
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return STATUS_NOT_IMPLEMENTED;
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}
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NTSTATUS
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CUSBHardwareDevice::GetDeviceDetails(
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OUT OPTIONAL PUSHORT VendorId,
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OUT OPTIONAL PUSHORT DeviceId,
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OUT OPTIONAL PULONG NumberOfPorts,
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OUT OPTIONAL PULONG Speed)
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{
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if (VendorId)
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{
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//
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// get vendor
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//
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*VendorId = m_VendorID;
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}
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if (DeviceId)
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{
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//
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// get device id
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//
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*DeviceId = m_DeviceID;
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}
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if (NumberOfPorts)
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{
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//
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// get number of ports
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//
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*NumberOfPorts = m_NumberOfPorts;
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}
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if (Speed)
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{
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//
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// speed is 0x100
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//
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*Speed = 0x100;
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}
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return STATUS_SUCCESS;
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}
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NTSTATUS CUSBHardwareDevice::GetDMA(
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OUT struct IDMAMemoryManager **OutDMAMemoryManager)
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{
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if (!m_MemoryManager)
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return STATUS_UNSUCCESSFUL;
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*OutDMAMemoryManager = m_MemoryManager;
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return STATUS_SUCCESS;
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}
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NTSTATUS
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CUSBHardwareDevice::GetUSBQueue(
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OUT struct IUSBQueue **OutUsbQueue)
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{
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if (!m_UsbQueue)
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return STATUS_UNSUCCESSFUL;
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*OutUsbQueue = m_UsbQueue;
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return STATUS_SUCCESS;
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}
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NTSTATUS
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CUSBHardwareDevice::StartController(void)
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{
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ULONG Index;
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USHORT Status;
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//
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// debug info
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//
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DPRINT1("[USBUHCI] USBCMD: %x USBSTS %x\n", ReadRegister16(UHCI_USBCMD), ReadRegister16(UHCI_USBSTS));
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//
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// Set the run bit in the command register
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//
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WriteRegister16(UHCI_USBCMD, ReadRegister16(UHCI_USBCMD) | UHCI_USBCMD_RS);
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for(Index = 0; Index < 100; Index++)
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{
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//
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// wait a bit
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//
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KeStallExecutionProcessor(100);
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//
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// get controller status
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//
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Status = ReadRegister16(UHCI_USBSTS);
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DPRINT1("[USBUHCI] Status %x\n", Status);
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if (!(Status & UHCI_USBSTS_HCHALT))
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{
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//
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// controller started
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//
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break;
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}
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}
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DPRINT1("[USBUHCI] USBCMD: %x USBSTS %x\n", ReadRegister16(UHCI_USBCMD), ReadRegister16(UHCI_USBSTS));
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if ((Status & UHCI_USBSTS_HCHALT))
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{
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//
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// failed to start controller
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//
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DPRINT1("[USBUHCI] Failed to start controller Status %x\n", Status);
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ASSERT(FALSE);
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return STATUS_UNSUCCESSFUL;
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}
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//
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// Set the configure bit
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//
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WriteRegister16(UHCI_USBCMD, ReadRegister16(UHCI_USBCMD) | UHCI_USBCMD_CF);
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for(Index = 0; Index < 2; Index++)
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{
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//
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// get port status
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//
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Status = ReadRegister16(UHCI_PORTSC1 + Index * 2);
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//
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// clear connection change and port suspend
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//
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WriteRegister16(UHCI_PORTSC1 + Index * 2, Status & ~(UHCI_PORTSC_STATCHA | UHCI_PORTSC_SUSPEND));
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}
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DPRINT1("[USBUHCI] Controller Started\n");
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DPRINT1("[USBUHCI] Controller Status %x\n", ReadRegister16(UHCI_USBSTS));
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DPRINT1("[USBUHCI] Controller Cmd Status %x\n", ReadRegister16(UHCI_USBCMD));
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DPRINT1("[USBUHCI] Controller Interrupt Status %x\n", ReadRegister16(UHCI_USBINTR));
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DPRINT1("[USBUHCI] Controller Frame %x\n", ReadRegister16(UHCI_FRNUM));
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DPRINT1("[USBUHCI] Controller Port Status 0 %x\n", ReadRegister16(UHCI_PORTSC1));
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DPRINT1("[USBUHCI] Controller Port Status 1 %x\n", ReadRegister16(UHCI_PORTSC1 + 2));
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|
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// queue timer
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LARGE_INTEGER Expires;
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Expires.QuadPart = -10 * 10000;
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|
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KeSetTimerEx(&m_SCETimer, Expires, 1000, &m_SCETimerDpc);
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|
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//
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// done
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//
|
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return STATUS_SUCCESS;
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}
|
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|
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VOID
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CUSBHardwareDevice::GlobalReset()
|
|
{
|
|
LARGE_INTEGER Timeout;
|
|
|
|
//
|
|
// back up start of modify register
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|
//
|
|
ASSERT(m_Base);
|
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UCHAR sofValue = READ_PORT_UCHAR((PUCHAR)((ULONG)m_Base + UHCI_SOFMOD));
|
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|
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//
|
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// perform global reset
|
|
//
|
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WriteRegister16(UHCI_USBCMD, ReadRegister16(UHCI_USBCMD) | UHCI_USBCMD_GRESET);
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|
|
//
|
|
// delay is 10 ms
|
|
//
|
|
Timeout.QuadPart = 10;
|
|
DPRINT1("Waiting %lu milliseconds for global reset\n", Timeout.LowPart);
|
|
|
|
//
|
|
// convert to 100 ns units (absolute)
|
|
//
|
|
Timeout.QuadPart *= -10000;
|
|
|
|
//
|
|
// perform the wait
|
|
//
|
|
KeDelayExecutionThread(KernelMode, FALSE, &Timeout);
|
|
|
|
//
|
|
// clear command register
|
|
//
|
|
WriteRegister16(UHCI_USBCMD, ReadRegister16(UHCI_USBCMD) & ~UHCI_USBCMD_GRESET);
|
|
KeStallExecutionProcessor(10);
|
|
|
|
|
|
//
|
|
// restore start of modify register
|
|
//
|
|
WRITE_PORT_UCHAR((PUCHAR)((ULONG)m_Base + UHCI_SOFMOD), sofValue);
|
|
}
|
|
|
|
NTSTATUS
|
|
CUSBHardwareDevice::InitializeController()
|
|
{
|
|
NTSTATUS Status;
|
|
ULONG Index;
|
|
BUS_INTERFACE_STANDARD BusInterface;
|
|
USHORT Value;
|
|
PHYSICAL_ADDRESS Address;
|
|
|
|
DPRINT1("[USBUHCI] InitializeController\n");
|
|
|
|
//
|
|
// now disable all interrupts
|
|
//
|
|
WriteRegister16(UHCI_USBINTR, 0);
|
|
|
|
|
|
//
|
|
// UHCI has two ports
|
|
//
|
|
m_NumberOfPorts = 2;
|
|
|
|
//
|
|
// get bus interface
|
|
//
|
|
Status = GetBusInterface(m_PhysicalDeviceObject, &BusInterface);
|
|
if (!NT_SUCCESS(Status))
|
|
{
|
|
DPRINT1("Failed to get BusInteface!\n");
|
|
return Status;
|
|
}
|
|
|
|
//
|
|
// reclaim ownership from BIOS
|
|
//
|
|
Value = 0;
|
|
BusInterface.GetBusData(BusInterface.Context, PCI_WHICHSPACE_CONFIG, &Value, PCI_LEGSUP, sizeof(USHORT));
|
|
DPRINT1("[USBUHCI] LEGSUP %x\n", Value);
|
|
|
|
Value = PCI_LEGSUP_USBPIRQDEN;
|
|
BusInterface.SetBusData(BusInterface.Context, PCI_WHICHSPACE_CONFIG, &Value, PCI_LEGSUP, sizeof(USHORT));
|
|
|
|
DPRINT1("[USBUHCI] Acquired ownership\n");
|
|
Value = 0;
|
|
BusInterface.GetBusData(BusInterface.Context, PCI_WHICHSPACE_CONFIG, &Value, 0x60, sizeof(UCHAR));
|
|
DPRINT1("[USBUHCI] SBRN %x\n", Value);
|
|
|
|
//
|
|
// perform global reset
|
|
//
|
|
GlobalReset();
|
|
|
|
//
|
|
// reset controller
|
|
//
|
|
Status = ResetController();
|
|
if (!NT_SUCCESS(Status))
|
|
{
|
|
//
|
|
// failed to reset controller
|
|
//
|
|
DPRINT1("[USBUHCI] Failed to reset controller\n");
|
|
return Status;
|
|
}
|
|
|
|
//
|
|
// allocate frame list
|
|
//
|
|
Status = m_MemoryManager->Allocate(NUMBER_OF_FRAMES * sizeof(ULONG), (PVOID*)&m_FrameList, &m_FrameListPhysicalAddress);
|
|
if (!NT_SUCCESS(Status))
|
|
{
|
|
//
|
|
// failed to allocate frame list
|
|
//
|
|
DPRINT1("[USBUHCI] Failed to allocate frame list with %x\n", Status);
|
|
return Status;
|
|
}
|
|
|
|
//
|
|
// Set base pointer and reset frame number
|
|
//
|
|
WriteRegister32(UHCI_FRBASEADD, m_FrameListPhysicalAddress.LowPart);
|
|
WriteRegister16(UHCI_FRNUM, 0);
|
|
|
|
//
|
|
// Set the max packet size for bandwidth reclamation to 64 bytes
|
|
//
|
|
WriteRegister16(UHCI_USBCMD, ReadRegister16(UHCI_USBCMD) | UHCI_USBCMD_MAXP);
|
|
|
|
//
|
|
// now create queues
|
|
// 0: interrupt transfers
|
|
// 1: low speed control transfers
|
|
// 2: full speed control transfers
|
|
// 3: bulk transfers
|
|
// 4: debug queue
|
|
//
|
|
for(Index = 0; Index < 5; Index++)
|
|
{
|
|
//
|
|
// create queue head
|
|
//
|
|
Status = m_MemoryManager->Allocate(sizeof(UHCI_QUEUE_HEAD), (PVOID*)&m_QueueHead[Index], &Address);
|
|
if (!NT_SUCCESS(Status))
|
|
{
|
|
//
|
|
// failed to allocate queue head
|
|
//
|
|
DPRINT1("[USBUHCI] Failed to allocate queue head %x Index %x\n", Status, Index);
|
|
return Status;
|
|
}
|
|
|
|
//
|
|
// store queue head
|
|
//
|
|
m_QueueHead[Index]->PhysicalAddress = Address.LowPart;
|
|
m_QueueHead[Index]->ElementPhysical = QH_TERMINATE;
|
|
m_QueueHead[Index]->LinkPhysical = QH_TERMINATE;
|
|
|
|
if (Index > 0)
|
|
{
|
|
//
|
|
// link queue heads
|
|
//
|
|
m_QueueHead[Index-1]->LinkPhysical = m_QueueHead[Index]->PhysicalAddress | QH_NEXT_IS_QH;
|
|
m_QueueHead[Index-1]->NextLogicalDescriptor = m_QueueHead[Index];
|
|
}
|
|
}
|
|
|
|
DPRINT1("Index %d QueueHead %p LinkPhysical %x ElementPhysical %x PhysicalAddress %x Request %p NextElementDescriptor %p\n",
|
|
0,
|
|
m_QueueHead[0],
|
|
m_QueueHead[0]->LinkPhysical,
|
|
m_QueueHead[0]->ElementPhysical,
|
|
m_QueueHead[0]->PhysicalAddress,
|
|
m_QueueHead[0]->Request,
|
|
m_QueueHead[0]->NextElementDescriptor);
|
|
DPRINT1("Index %d QueueHead %p LinkPhysical %x ElementPhysical %x PhysicalAddress %x Request %p NextElementDescriptor %p\n",
|
|
1,
|
|
m_QueueHead[1],
|
|
m_QueueHead[1]->LinkPhysical,
|
|
m_QueueHead[1]->ElementPhysical,
|
|
m_QueueHead[1]->PhysicalAddress,
|
|
m_QueueHead[1]->Request,
|
|
m_QueueHead[1]->NextElementDescriptor);
|
|
|
|
DPRINT1("Index %d QueueHead %p LinkPhysical %x ElementPhysical %x PhysicalAddress %x Request %p NextElementDescriptor %p\n",
|
|
2,
|
|
m_QueueHead[2],
|
|
m_QueueHead[2]->LinkPhysical,
|
|
m_QueueHead[2]->ElementPhysical,
|
|
m_QueueHead[2]->PhysicalAddress,
|
|
m_QueueHead[2]->Request,
|
|
m_QueueHead[2]->NextElementDescriptor);
|
|
DPRINT1("Index %d QueueHead %p LinkPhysical %x ElementPhysical %x PhysicalAddress %x Request %p NextElementDescriptor %p\n",
|
|
3,
|
|
m_QueueHead[3],
|
|
m_QueueHead[3]->LinkPhysical,
|
|
m_QueueHead[3]->ElementPhysical,
|
|
m_QueueHead[3]->PhysicalAddress,
|
|
m_QueueHead[3]->Request,
|
|
m_QueueHead[3]->NextElementDescriptor);
|
|
DPRINT1("Index %d QueueHead %p LinkPhysical %x ElementPhysical %x PhysicalAddress %x Request %p NextElementDescriptor %p\n",
|
|
4,
|
|
m_QueueHead[4],
|
|
m_QueueHead[4]->LinkPhysical,
|
|
m_QueueHead[4]->ElementPhysical,
|
|
m_QueueHead[4]->PhysicalAddress,
|
|
m_QueueHead[4]->Request,
|
|
m_QueueHead[4]->NextElementDescriptor);
|
|
|
|
//
|
|
// terminate last queue head with stray descriptor
|
|
//
|
|
Status = m_MemoryManager->Allocate(sizeof(UHCI_TRANSFER_DESCRIPTOR), (PVOID*)&m_StrayDescriptor, &m_StrayDescriptorPhysicalAddress);
|
|
if (!NT_SUCCESS(Status))
|
|
{
|
|
//
|
|
// failed to allocate queue head
|
|
//
|
|
DPRINT1("[USBUHCI] Failed to allocate queue head %x Index %x\n", Status, Index);
|
|
return Status;
|
|
}
|
|
#if 0
|
|
//
|
|
// init stray descriptor
|
|
//
|
|
m_StrayDescriptor->PhysicalAddress = m_StrayDescriptorPhysicalAddress.LowPart;
|
|
m_StrayDescriptor->LinkPhysical = TD_TERMINATE;
|
|
m_StrayDescriptor->Token = TD_TOKEN_NULL_DATA | (0x7f << TD_TOKEN_DEVADDR_SHIFT) | TD_TOKEN_IN;
|
|
|
|
|
|
//
|
|
// link to last queue head
|
|
//
|
|
m_QueueHead[4]->LinkPhysical = m_StrayDescriptor->PhysicalAddress;
|
|
m_QueueHead[4]->NextLogicalDescriptor = m_StrayDescriptor;
|
|
#endif
|
|
|
|
//
|
|
// allocate frame bandwidth array
|
|
//
|
|
m_FrameBandwidth = (PUSHORT)ExAllocatePool(NonPagedPool, sizeof(USHORT) * NUMBER_OF_FRAMES);
|
|
if (!m_FrameBandwidth)
|
|
{
|
|
//
|
|
// no memory
|
|
//
|
|
DPRINT1("[USBUHCI] Failed to allocate memory\n");
|
|
return STATUS_INSUFFICIENT_RESOURCES;
|
|
}
|
|
|
|
//
|
|
// init frame list
|
|
//
|
|
for (Index = 0; Index < NUMBER_OF_FRAMES; Index++)
|
|
{
|
|
//
|
|
// store frame list interrupt queue
|
|
//
|
|
m_FrameList[Index] = m_QueueHead[UHCI_INTERRUPT_QUEUE]->PhysicalAddress | FRAMELIST_NEXT_IS_QH;
|
|
m_FrameBandwidth[Index] = MAX_AVAILABLE_BANDWIDTH;
|
|
|
|
|
|
}
|
|
|
|
//
|
|
// set enabled interrupt mask
|
|
//
|
|
m_InterruptMask = UHCI_USBSTS_USBINT | UHCI_USBSTS_ERRINT | UHCI_USBSTS_HOSTERR | UHCI_USBSTS_HCPRERR | UHCI_USBSTS_HCHALT;
|
|
|
|
//
|
|
// now enable interrupts
|
|
//
|
|
WriteRegister16(UHCI_USBINTR, UHCI_USBINTR_CRC | UHCI_USBINTR_IOC| UHCI_USBINTR_SHORT);
|
|
|
|
DPRINT1("[USBUHCI] Controller initialized\n");
|
|
return STATUS_SUCCESS;
|
|
}
|
|
|
|
NTSTATUS
|
|
CUSBHardwareDevice::StopController(void)
|
|
{
|
|
ASSERT(FALSE);
|
|
//
|
|
// failed to reset controller
|
|
//
|
|
return STATUS_UNSUCCESSFUL;
|
|
}
|
|
|
|
NTSTATUS
|
|
CUSBHardwareDevice::ResetController(void)
|
|
{
|
|
ULONG Count = 0;
|
|
USHORT Status;
|
|
|
|
// clear run bit
|
|
WriteRegister16(UHCI_USBCMD, ReadRegister16(UHCI_USBCMD) & ~UHCI_USBCMD_RS);
|
|
|
|
// wait for the controller to stop
|
|
while((ReadRegister16(UHCI_USBSTS) & UHCI_USBSTS_HCHALT) == 0)
|
|
{
|
|
DPRINT1("[UHCI] Waiting for the controller to halt\n");
|
|
KeStallExecutionProcessor(10);
|
|
}
|
|
|
|
// clear configure bit
|
|
WriteRegister16(UHCI_USBCMD, ReadRegister16(UHCI_USBCMD) & ~UHCI_USBCMD_CF);
|
|
|
|
//
|
|
// reset controller
|
|
//
|
|
WriteRegister16(UHCI_USBCMD, UHCI_USBCMD_HCRESET);
|
|
|
|
do
|
|
{
|
|
//
|
|
// wait a bit
|
|
//
|
|
KeStallExecutionProcessor(100);
|
|
|
|
//
|
|
// get status
|
|
//
|
|
Status = ReadRegister16(UHCI_USBCMD);
|
|
if (!(Status & UHCI_USBCMD_HCRESET))
|
|
{
|
|
//
|
|
// controller reset completed
|
|
//
|
|
return STATUS_SUCCESS;
|
|
}
|
|
}while(Count++ < 100);
|
|
|
|
DPRINT1("[USBUHCI] Failed to reset controller Status %x\n", Status);
|
|
return STATUS_UNSUCCESSFUL;
|
|
}
|
|
|
|
NTSTATUS
|
|
CUSBHardwareDevice::ResetPort(
|
|
IN ULONG PortIndex)
|
|
{
|
|
ULONG Port;
|
|
USHORT Status;
|
|
ULONG Index;
|
|
LARGE_INTEGER Timeout;
|
|
|
|
DPRINT1("[UHCI] ResetPort Id %lu\n", PortIndex);
|
|
|
|
//
|
|
// sanity check
|
|
//
|
|
ASSERT(PortIndex <= 1);
|
|
|
|
//
|
|
// get register offset
|
|
//
|
|
Port = UHCI_PORTSC1 + PortIndex * 2;
|
|
|
|
//
|
|
// read port status
|
|
//
|
|
Status = ReadRegister16(Port);
|
|
|
|
|
|
|
|
//
|
|
// remove unwanted bits
|
|
//
|
|
Status &= UHCI_PORTSC_DATAMASK;
|
|
|
|
//
|
|
// now reset the port
|
|
//
|
|
WriteRegister16(Port, Status | UHCI_PORTSC_RESET);
|
|
|
|
//
|
|
// delay is 20 ms for port reset
|
|
//
|
|
Timeout.QuadPart = 20;
|
|
DPRINT1("Waiting %lu milliseconds for port reset\n", Timeout.LowPart);
|
|
|
|
//
|
|
// convert to 100 ns units (absolute)
|
|
//
|
|
Timeout.QuadPart *= -10000;
|
|
|
|
//
|
|
// perform the wait
|
|
//
|
|
KeDelayExecutionThread(KernelMode, FALSE, &Timeout);
|
|
|
|
//
|
|
// re-read status
|
|
//
|
|
Status = ReadRegister16(Port);
|
|
|
|
//
|
|
// remove unwanted bits
|
|
//
|
|
Status &= UHCI_PORTSC_DATAMASK;
|
|
|
|
//
|
|
// clear reset port
|
|
//
|
|
WriteRegister16(Port, (Status & ~UHCI_PORTSC_RESET));
|
|
|
|
|
|
//
|
|
// now wait a bit
|
|
//
|
|
KeStallExecutionProcessor(10);
|
|
|
|
for (Index = 0; Index < 100; Index++)
|
|
{
|
|
// read port status
|
|
Status = ReadRegister16(Port);
|
|
|
|
// remove unwanted bits
|
|
Status &= UHCI_PORTSC_DATAMASK;
|
|
|
|
// enable port
|
|
WriteRegister16(Port, Status | UHCI_PORTSC_ENABLED);
|
|
|
|
//
|
|
// wait a bit
|
|
//
|
|
KeStallExecutionProcessor(50);
|
|
|
|
//
|
|
// re-read port
|
|
//
|
|
Status = ReadRegister16(Port);
|
|
|
|
if ((Status & UHCI_PORTSC_CURSTAT) == 0)
|
|
{
|
|
// no device connected. since we waited long enough we can assume
|
|
// that the port was reset and no device is connected.
|
|
break;
|
|
}
|
|
|
|
if (Status & (UHCI_PORTSC_STATCHA | UHCI_PORTSC_ENABCHA))
|
|
{
|
|
// port enabled changed or connection status were set.
|
|
// acknowledge either / both and wait again.
|
|
WriteRegister16(Port, Status);
|
|
continue;
|
|
}
|
|
|
|
if (Status & UHCI_PORTSC_ENABLED)
|
|
{
|
|
// the port is enabled
|
|
break;
|
|
}
|
|
}
|
|
|
|
m_PortResetChange |= (1 << PortIndex);
|
|
DPRINT1("[USBUhci] Port Index %x Status after reset %x\n", PortIndex, ReadRegister16(Port));
|
|
|
|
//
|
|
// is there a callback
|
|
//
|
|
if (m_SCECallBack)
|
|
{
|
|
//
|
|
// issue callback
|
|
//
|
|
m_SCECallBack(m_SCEContext);
|
|
}
|
|
|
|
return STATUS_SUCCESS;
|
|
}
|
|
|
|
NTSTATUS
|
|
CUSBHardwareDevice::GetPortStatus(
|
|
ULONG PortId,
|
|
OUT USHORT *PortStatus,
|
|
OUT USHORT *PortChange)
|
|
{
|
|
USHORT Status;
|
|
|
|
//
|
|
// sanity check
|
|
//
|
|
if (PortId > 1)
|
|
{
|
|
//
|
|
// invalid index
|
|
//
|
|
DPRINT1("[UHCI] Invalid PortIndex %lu\n", PortId);
|
|
return STATUS_INVALID_PARAMETER;
|
|
}
|
|
|
|
//
|
|
// init status
|
|
//
|
|
*PortStatus = 0;
|
|
*PortChange = 0;
|
|
|
|
//
|
|
// read port status
|
|
//
|
|
Status = ReadRegister16(UHCI_PORTSC1 + PortId * 2);
|
|
DPRINT("[USBUHCI] PortId %x Status %x\n", PortId, Status);
|
|
|
|
// build the status
|
|
if (Status & UHCI_PORTSC_CURSTAT)
|
|
{
|
|
*PortStatus |= USB_PORT_STATUS_CONNECT;
|
|
}
|
|
|
|
if (Status & UHCI_PORTSC_ENABLED)
|
|
{
|
|
*PortStatus |= USB_PORT_STATUS_ENABLE;
|
|
}
|
|
|
|
if (Status & UHCI_PORTSC_RESET)
|
|
{
|
|
*PortStatus |= USB_PORT_STATUS_RESET;
|
|
}
|
|
|
|
if (Status & UHCI_PORTSC_LOWSPEED)
|
|
{
|
|
*PortStatus |= USB_PORT_STATUS_LOW_SPEED;
|
|
}
|
|
|
|
if (Status & UHCI_PORTSC_STATCHA)
|
|
{
|
|
*PortChange |= USB_PORT_STATUS_CONNECT;
|
|
}
|
|
|
|
if (Status & UHCI_PORTSC_ENABCHA)
|
|
{
|
|
*PortChange |= USB_PORT_STATUS_ENABLE;
|
|
}
|
|
|
|
if (m_PortResetChange & (1 << PortId))
|
|
{
|
|
*PortChange |= USB_PORT_STATUS_RESET;
|
|
}
|
|
|
|
//
|
|
// port always has power
|
|
//
|
|
*PortStatus |= USB_PORT_STATUS_POWER;
|
|
return STATUS_SUCCESS;
|
|
}
|
|
|
|
NTSTATUS
|
|
CUSBHardwareDevice::ClearPortStatus(
|
|
ULONG PortId,
|
|
ULONG Feature)
|
|
{
|
|
ULONG PortRegister;
|
|
USHORT PortStatus;
|
|
|
|
DPRINT("CUSBHardwareDevice::ClearPortStatus PortId %x Feature %x\n", PortId, Feature);
|
|
|
|
//
|
|
// sanity check
|
|
//
|
|
if (PortId > 1)
|
|
{
|
|
//
|
|
// invalid index
|
|
//
|
|
DPRINT1("[UHCI] Invalid PortIndex %lu\n", PortId);
|
|
return STATUS_INVALID_PARAMETER;
|
|
}
|
|
|
|
//
|
|
// read current status
|
|
//
|
|
PortRegister = UHCI_PORTSC1 + PortId * 2;
|
|
PortStatus = ReadRegister16(PortRegister);
|
|
DPRINT("[UHCI] PortStatus %x\n", PortStatus);
|
|
|
|
if (Feature == C_PORT_RESET)
|
|
{
|
|
//
|
|
// UHCI is not supporting port reset register bit
|
|
//
|
|
m_PortResetChange &= ~(1 << PortId);
|
|
}
|
|
else if (Feature == C_PORT_CONNECTION || Feature == C_PORT_ENABLE)
|
|
{
|
|
//
|
|
// clear port status changes
|
|
//
|
|
WriteRegister16(PortRegister, PortStatus);
|
|
}
|
|
|
|
return STATUS_SUCCESS;
|
|
}
|
|
|
|
|
|
NTSTATUS
|
|
CUSBHardwareDevice::SetPortFeature(
|
|
ULONG PortId,
|
|
ULONG Feature)
|
|
{
|
|
ULONG PortRegister;
|
|
|
|
DPRINT1("[UHCI] SetPortFeature PortId %x Feature %x\n", PortId, Feature);
|
|
|
|
//
|
|
// sanity check
|
|
//
|
|
if (PortId > 1)
|
|
{
|
|
//
|
|
// invalid index
|
|
//
|
|
DPRINT1("[UHCI] Invalid PortIndex %lu\n", PortId);
|
|
return STATUS_INVALID_PARAMETER;
|
|
}
|
|
|
|
PortRegister = UHCI_PORTSC1 + PortId * 2;
|
|
|
|
if (Feature == PORT_RESET)
|
|
{
|
|
//
|
|
// reset port
|
|
//
|
|
return ResetPort(PortId);
|
|
}
|
|
else if (Feature == PORT_ENABLE)
|
|
{
|
|
//
|
|
// reset port
|
|
//
|
|
WriteRegister16(PortRegister, ReadRegister16(PortRegister) | UHCI_PORTSC_ENABLED);
|
|
}
|
|
else if (Feature == PORT_POWER)
|
|
{
|
|
//
|
|
// port power is no op, it is always enabled
|
|
//
|
|
}
|
|
|
|
return STATUS_SUCCESS;
|
|
}
|
|
|
|
|
|
|
|
VOID
|
|
CUSBHardwareDevice::SetStatusChangeEndpointCallBack(
|
|
PVOID CallBack,
|
|
PVOID Context)
|
|
{
|
|
m_SCECallBack = (HD_INIT_CALLBACK*)CallBack;
|
|
m_SCEContext = Context;
|
|
}
|
|
|
|
BOOLEAN
|
|
NTAPI
|
|
InterruptServiceRoutine(
|
|
IN PKINTERRUPT Interrupt,
|
|
IN PVOID ServiceContext)
|
|
{
|
|
CUSBHardwareDevice *This;
|
|
USHORT Status, Acknowledge;
|
|
|
|
//
|
|
// get context
|
|
//
|
|
This = (CUSBHardwareDevice*) ServiceContext;
|
|
|
|
//
|
|
// read register
|
|
//
|
|
Status = This->ReadRegister16(UHCI_USBSTS);
|
|
DPRINT("InterruptServiceRoutine %x\n", Status);
|
|
|
|
//
|
|
// check if the interrupt signaled are from us
|
|
//
|
|
if ((Status & This->m_InterruptMask) == 0)
|
|
{
|
|
if (Status != 0)
|
|
{
|
|
//
|
|
// FIXME: received unexpected interrupt
|
|
//
|
|
DPRINT1("[USBUHCI] Unexpected interrupt %x\n", Status);
|
|
This->WriteRegister16(UHCI_USBSTS, Status);
|
|
}
|
|
|
|
//
|
|
// shared interrupt
|
|
//
|
|
return FALSE;
|
|
}
|
|
|
|
//
|
|
// check for the interrupt cause
|
|
//
|
|
Acknowledge = 0;
|
|
|
|
if (Status & UHCI_USBSTS_USBINT)
|
|
{
|
|
//
|
|
// transfer finished
|
|
//
|
|
Acknowledge |= UHCI_USBSTS_USBINT;
|
|
}
|
|
|
|
if (Status & UHCI_USBSTS_ERRINT)
|
|
{
|
|
//
|
|
// error interrupt
|
|
//
|
|
Acknowledge |= UHCI_USBSTS_ERRINT;
|
|
DPRINT1("[UHCI] Error interrupt\n");
|
|
}
|
|
|
|
if (Status & UHCI_USBSTS_RESDET)
|
|
{
|
|
//
|
|
// resume detected
|
|
//
|
|
DPRINT1("[UHCI] Resume detected\n");
|
|
Acknowledge |= UHCI_USBSTS_RESDET;
|
|
}
|
|
|
|
if (Status & UHCI_USBSTS_HOSTERR)
|
|
{
|
|
//
|
|
// host system error
|
|
//
|
|
DPRINT1("[UHCI] Host System Error\n");
|
|
Acknowledge |= UHCI_USBSTS_HOSTERR;
|
|
}
|
|
|
|
if (Status & UHCI_USBSTS_HCPRERR)
|
|
{
|
|
//
|
|
// processing error
|
|
//
|
|
DPRINT1("[UHCI] Process Error\n");
|
|
Acknowledge |= UHCI_USBSTS_HCPRERR;
|
|
}
|
|
|
|
if (Status & UHCI_USBSTS_HCHALT)
|
|
{
|
|
//
|
|
// controller halted
|
|
//
|
|
DPRINT1("[UHCI] Host controller halted\n");
|
|
|
|
//
|
|
// disable interrupts
|
|
//
|
|
This->WriteRegister16(UHCI_USBINTR, 0);
|
|
This->m_InterruptMask = 0;
|
|
}
|
|
|
|
//
|
|
// do we have something to acknowledge
|
|
//
|
|
if (Acknowledge)
|
|
{
|
|
//
|
|
// acknowledge interrupt
|
|
//
|
|
This->WriteRegister16(UHCI_USBSTS, Acknowledge);
|
|
|
|
//
|
|
// queue dpc
|
|
//
|
|
KeInsertQueueDpc(&This->m_IntDpcObject, UlongToPtr(Status), NULL);
|
|
}
|
|
|
|
//
|
|
// interrupt handled
|
|
//
|
|
return TRUE;
|
|
}
|
|
|
|
|
|
VOID
|
|
CUSBHardwareDevice::WriteRegister8(
|
|
IN ULONG Register,
|
|
IN UCHAR Value)
|
|
{
|
|
WRITE_PORT_UCHAR((PUCHAR)((ULONG)m_Base + Register), Value);
|
|
}
|
|
|
|
|
|
VOID
|
|
CUSBHardwareDevice::WriteRegister16(
|
|
ULONG Register,
|
|
USHORT Value)
|
|
{
|
|
WRITE_PORT_USHORT((PUSHORT)((ULONG)m_Base + Register), Value);
|
|
}
|
|
|
|
|
|
VOID
|
|
CUSBHardwareDevice::WriteRegister32(
|
|
ULONG Register,
|
|
ULONG Value)
|
|
{
|
|
WRITE_PORT_ULONG((PULONG)((ULONG)m_Base + Register), Value);
|
|
}
|
|
|
|
|
|
UCHAR
|
|
CUSBHardwareDevice::ReadRegister8(
|
|
ULONG Register)
|
|
{
|
|
return READ_PORT_UCHAR((PUCHAR)((ULONG)m_Base + Register));
|
|
}
|
|
|
|
|
|
USHORT
|
|
CUSBHardwareDevice::ReadRegister16(
|
|
ULONG Register)
|
|
{
|
|
return READ_PORT_USHORT((PUSHORT)((ULONG)m_Base + Register));
|
|
}
|
|
|
|
|
|
ULONG
|
|
CUSBHardwareDevice::ReadRegister32(
|
|
ULONG Register)
|
|
{
|
|
return READ_PORT_ULONG((PULONG)((ULONG)m_Base + Register));
|
|
}
|
|
|
|
VOID
|
|
CUSBHardwareDevice::GetQueueHead(
|
|
IN ULONG QueueHeadIndex,
|
|
OUT PUHCI_QUEUE_HEAD *OutQueueHead)
|
|
{
|
|
//
|
|
// sanity check
|
|
//
|
|
ASSERT(QueueHeadIndex < 5);
|
|
|
|
//
|
|
// store queue head
|
|
//
|
|
*OutQueueHead = m_QueueHead[QueueHeadIndex];
|
|
}
|
|
|
|
VOID
|
|
NTAPI
|
|
UhciDefferedRoutine(
|
|
IN PKDPC Dpc,
|
|
IN PVOID DeferredContext,
|
|
IN PVOID SystemArgument1,
|
|
IN PVOID SystemArgument2)
|
|
{
|
|
CUSBHardwareDevice *This;
|
|
ULONG Status;
|
|
|
|
//
|
|
// get parameters
|
|
//
|
|
This = (CUSBHardwareDevice*)DeferredContext;
|
|
|
|
DPRINT("UhciDefferedRoutine\n");
|
|
|
|
//
|
|
// get status
|
|
//
|
|
Status = PtrToUlong(SystemArgument1);
|
|
if (Status & (UHCI_USBSTS_USBINT | UHCI_USBSTS_ERRINT))
|
|
{
|
|
//
|
|
// a transfer finished, inform the queue
|
|
//
|
|
This->m_UsbQueue->TransferInterrupt(Status & UHCI_USBSTS_USBINT);
|
|
return;
|
|
}
|
|
|
|
//
|
|
// other event
|
|
//
|
|
DPRINT1("[USBUHCI] Status %x not handled\n", Status);
|
|
}
|
|
|
|
VOID
|
|
NTAPI
|
|
TimerDpcRoutine(
|
|
IN PKDPC Dpc,
|
|
IN PVOID DeferredContext,
|
|
IN PVOID SystemArgument1,
|
|
IN PVOID SystemArgument2)
|
|
{
|
|
CUSBHardwareDevice *This;
|
|
USHORT PortStatus = 0;
|
|
USHORT PortChange = 0;
|
|
|
|
// get parameters
|
|
This = (CUSBHardwareDevice*)DeferredContext;
|
|
|
|
// check port 0
|
|
This->GetPortStatus(0, &PortStatus, &PortChange);
|
|
if (PortChange)
|
|
{
|
|
// invoke status change work item routine
|
|
StatusChangeWorkItemRoutine(DeferredContext);
|
|
return;
|
|
}
|
|
|
|
// check port 1
|
|
This->GetPortStatus(1, &PortStatus, &PortChange);
|
|
if (PortChange)
|
|
{
|
|
// invoke status change work item routine
|
|
StatusChangeWorkItemRoutine(DeferredContext);
|
|
}
|
|
}
|
|
|
|
|
|
VOID
|
|
NTAPI
|
|
StatusChangeWorkItemRoutine(
|
|
PVOID Context)
|
|
{
|
|
//
|
|
// cast to hardware object
|
|
//
|
|
CUSBHardwareDevice * This = (CUSBHardwareDevice*)Context;
|
|
|
|
//
|
|
// is there a callback
|
|
//
|
|
if (This->m_SCECallBack)
|
|
{
|
|
//
|
|
// issue callback
|
|
//
|
|
This->m_SCECallBack(This->m_SCEContext);
|
|
}
|
|
|
|
}
|
|
|
|
NTSTATUS
|
|
NTAPI
|
|
CreateUSBHardware(
|
|
PUSBHARDWAREDEVICE *OutHardware)
|
|
{
|
|
PUSBHARDWAREDEVICE This;
|
|
|
|
This = new(NonPagedPool, TAG_USBUHCI) CUSBHardwareDevice(0);
|
|
|
|
if (!This)
|
|
return STATUS_INSUFFICIENT_RESOURCES;
|
|
|
|
This->AddRef();
|
|
|
|
// return result
|
|
*OutHardware = (PUSBHARDWAREDEVICE)This;
|
|
|
|
return STATUS_SUCCESS;
|
|
}
|