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154 lines
6.5 KiB
C
154 lines
6.5 KiB
C
/*
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* kernel internal memory management definitions for arm
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*/
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#pragma once
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#define _MI_PAGING_LEVELS 2
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/* Memory layout base addresses */
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#define MI_USER_PROBE_ADDRESS (PVOID)0x7FFF0000
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#define MI_DEFAULT_SYSTEM_RANGE_START (PVOID)0x80000000
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#define HYPER_SPACE 0xC0500000
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#define HYPER_SPACE_END 0xC08FFFFF
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#define MI_SYSTEM_CACHE_WS_START (PVOID)0xC0C00000
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#define MI_PAGED_POOL_START (PVOID)0xE1000000
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#define MI_NONPAGED_POOL_END (PVOID)0xFFBE0000
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#define MI_DEBUG_MAPPING (PVOID)0xFFBFF000
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#define MI_HIGHEST_SYSTEM_ADDRESS (PVOID)0xFFFFFFFF
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#define PTE_PER_PAGE 256
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#define PDE_PER_PAGE 4096
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#define PPE_PER_PAGE 1
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/* Misc address definitions */
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#define MI_SYSTEM_PTE_BASE (PVOID)MiAddressToPte(NULL)
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#define MM_HIGHEST_VAD_ADDRESS \
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(PVOID)((ULONG_PTR)MM_HIGHEST_USER_ADDRESS - (16 * PAGE_SIZE))
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#define MI_MAPPING_RANGE_START ((ULONG)HYPER_SPACE)
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#define MI_MAPPING_RANGE_END (MI_MAPPING_RANGE_START + \
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MI_HYPERSPACE_PTES * PAGE_SIZE)
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#define MI_DUMMY_PTE (PMMPTE)(MI_MAPPING_RANGE_END + \
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PAGE_SIZE)
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#define MI_VAD_BITMAP (PMMPTE)(MI_DUMMY_PTE + \
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PAGE_SIZE)
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#define MI_WORKING_SET_LIST (PMMPTE)(MI_VAD_BITMAP + \
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PAGE_SIZE)
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/* Memory sizes */
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#define MI_MIN_PAGES_FOR_NONPAGED_POOL_TUNING ((255 * _1MB) >> PAGE_SHIFT)
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#define MI_MIN_PAGES_FOR_SYSPTE_TUNING ((19 * _1MB) >> PAGE_SHIFT)
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#define MI_MIN_PAGES_FOR_SYSPTE_BOOST ((32 * _1MB) >> PAGE_SHIFT)
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#define MI_MIN_PAGES_FOR_SYSPTE_BOOST_BOOST ((256 * _1MB) >> PAGE_SHIFT)
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#define MI_MIN_INIT_PAGED_POOLSIZE (32 * _1MB)
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#define MI_MAX_INIT_NONPAGED_POOL_SIZE (128 * _1MB)
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#define MI_MAX_NONPAGED_POOL_SIZE (128 * _1MB)
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#define MI_SYSTEM_VIEW_SIZE (32 * _1MB)
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#define MI_SESSION_VIEW_SIZE (48 * _1MB)
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#define MI_SESSION_POOL_SIZE (16 * _1MB)
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#define MI_SESSION_IMAGE_SIZE (8 * _1MB)
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#define MI_SESSION_WORKING_SET_SIZE (4 * _1MB)
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#define MI_SESSION_SIZE (MI_SESSION_VIEW_SIZE + \
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MI_SESSION_POOL_SIZE + \
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MI_SESSION_IMAGE_SIZE + \
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MI_SESSION_WORKING_SET_SIZE)
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#define MI_MIN_ALLOCATION_FRAGMENT (4 * _1KB)
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#define MI_ALLOCATION_FRAGMENT (64 * _1KB)
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#define MI_MAX_ALLOCATION_FRAGMENT (2 * _1MB)
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/* Misc constants */
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#define MM_PTE_SOFTWARE_PROTECTION_BITS 6
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#define MI_MIN_SECONDARY_COLORS 8
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#define MI_SECONDARY_COLORS 64
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#define MI_MAX_SECONDARY_COLORS 1024
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#define MI_MAX_FREE_PAGE_LISTS 4
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#define MI_HYPERSPACE_PTES (256 - 1) /* Dee PDR definition */
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#define MI_ZERO_PTES (32) /* Dee PDR definition */
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#define MI_MAX_ZERO_BITS 21
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#define SESSION_POOL_LOOKASIDES 26 // CHECKME
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/* MMPTE related defines */
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#define MM_EMPTY_PTE_LIST ((ULONG)0xFFFFF)
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#define MM_EMPTY_LIST ((ULONG_PTR)-1)
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/* Easy accessing PFN in PTE */
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#define PFN_FROM_PTE(v) ((v)->u.Hard.PageFrameNumber)
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/* Macros for portable PTE modification */
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#define MI_MAKE_DIRTY_PAGE(x)
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#define MI_MAKE_CLEAN_PAGE(x)
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#define MI_MAKE_ACCESSED_PAGE(x)
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#define MI_PAGE_DISABLE_CACHE(x) ((x)->u.Hard.Cached = 0)
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#define MI_PAGE_WRITE_THROUGH(x) ((x)->u.Hard.Buffered = 0)
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#define MI_PAGE_WRITE_COMBINED(x) ((x)->u.Hard.Buffered = 1)
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#define MI_IS_PAGE_LARGE(x) FALSE
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#define MI_IS_PAGE_WRITEABLE(x) ((x)->u.Hard.ReadOnly == 0)
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#define MI_IS_PAGE_COPY_ON_WRITE(x)FALSE
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#define MI_IS_PAGE_EXECUTABLE(x) TRUE
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#define MI_IS_PAGE_DIRTY(x) TRUE
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#define MI_MAKE_OWNER_PAGE(x) ((x)->u.Hard.Owner = 1)
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#define MI_MAKE_WRITE_PAGE(x) ((x)->u.Hard.ReadOnly = 0)
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/* Macros to identify the page fault reason from the error code */
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#define MI_IS_NOT_PRESENT_FAULT(FaultCode) TRUE
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#define MI_IS_WRITE_ACCESS(FaultCode) TRUE
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#define MI_IS_INSTRUCTION_FETCH(FaultCode) FALSE
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/* Convert an address to a corresponding PTE */
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#define MiAddressToPte(x) \
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((PMMPTE)(PTE_BASE + (((ULONG)(x) >> 12) << 2)))
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/* Convert an address to a corresponding PDE */
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#define MiAddressToPde(x) \
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((PMMPDE)(PDE_BASE + (((ULONG)(x) >> 20) << 2)))
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/* Convert an address to a corresponding PTE offset/index */
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#define MiAddressToPteOffset(x) \
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((((ULONG)(x)) << 12) >> 24)
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/* Convert an address to a corresponding PDE offset/index */
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#define MiAddressToPdeOffset(x) \
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(((ULONG)(x)) >> 20)
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#define MiGetPdeOffset MiAddressToPdeOffset
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/* Convert a PTE/PDE into a corresponding address */
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#define MiPteToAddress(_Pte) ((PVOID)((ULONG)(_Pte) << 10))
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#define MiPdeToAddress(_Pde) ((PVOID)((ULONG)(_Pde) << 18))
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/* Translate between P*Es */
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#define MiPdeToPte(_Pde) ((PMMPTE)0) /* FIXME */
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#define MiPteToPde(_Pte) ((PMMPDE)0) /* FIXME */
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/* Check P*E boundaries */
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#define MiIsPteOnPdeBoundary(PointerPte) \
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((((ULONG_PTR)PointerPte) & (PAGE_SIZE - 1)) == 0)
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//
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// Decodes a Prototype PTE into the underlying PTE
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//
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#define MiProtoPteToPte(x) \
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(PMMPTE)((ULONG_PTR)MmPagedPoolStart + \
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(((x)->u.Proto.ProtoAddressHigh << 9) | (x)->u.Proto.ProtoAddressLow << 2))
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//
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// Decodes a Prototype PTE into the underlying PTE
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//
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#define MiSubsectionPteToSubsection(x) \
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((x)->u.Subsect.WhichPool == PagedPool) ? \
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(PMMPTE)((ULONG_PTR)MmSubsectionBase + \
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(((x)->u.Subsect.SubsectionAddressHigh << 7) | \
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(x)->u.Subsect.SubsectionAddressLow << 3)) : \
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(PMMPTE)((ULONG_PTR)MmNonPagedPoolEnd - \
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(((x)->u.Subsect.SubsectionAddressHigh << 7) | \
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(x)->u.Subsect.SubsectionAddressLow << 3))
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//
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// Number of bits corresponding to the area that a coarse page table occupies (1KB)
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//
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#define CPT_SHIFT 10
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/* See PDR definition */
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#define MI_ZERO_PTE (PMMPTE)(MI_MAPPING_RANGE_END + \
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PAGE_SIZE)
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