mirror of
https://github.com/reactos/reactos.git
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147 lines
3.7 KiB
C
147 lines
3.7 KiB
C
/*
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* PROJECT: ReactOS Kernel
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* LICENSE: BSD - See COPYING.ARM in the top level directory
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* FILE: ntoskrnl/mm/ARM3/miavl.h
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* PURPOSE: ARM Memory Manager VAD Node Algorithms
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* PROGRAMMERS: ReactOS Portable Systems Group
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*/
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/* INCLUDES ******************************************************************/
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/*
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* This is the glue code for the Memory Manager version of AVL Trees that is used
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* to store the MM_AVL_TABLE for Virtual Address Descriptors (VAD) in the VadRoot
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* field in EPROCESS.
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*
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* In this version of the package, the balance and parent pointers are stored in
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* the same field as a union (since we know the parent will be at least 8-byte
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* aligned), saving some space, but requiring special logic to handle setting and
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* querying the parent and balance.
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*
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* The other difference is that the AVL package for Rtl has custom callbacks for
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* comparison purposes (which would access some internal, opaque, user data) while
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* the Mm package stores the user-data inline as StartingVpn and EndingVpn. So
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* when a compare is being made, RtlpAvlCompareRoutine is called, which will either
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* perform the Mm work, or call the user-specified callback in the Rtl case.
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*/
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#define PRTL_AVL_TABLE PMM_AVL_TABLE
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#define PRTL_BALANCED_LINKS PMMADDRESS_NODE
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#define MI_ASSERT(x) ASSERT(x)
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VOID
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FORCEINLINE
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RtlpCopyAvlNodeData(IN PRTL_BALANCED_LINKS Node1,
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IN PRTL_BALANCED_LINKS Node2)
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{
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Node1->u1.Parent = Node2->u1.Parent;
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Node1->LeftChild = Node2->LeftChild;
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Node1->RightChild = Node2->RightChild;
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}
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RTL_GENERIC_COMPARE_RESULTS
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FORCEINLINE
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RtlpAvlCompareRoutine(IN PRTL_AVL_TABLE Table,
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IN PVOID Buffer,
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IN PVOID UserData)
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{
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PRTL_BALANCED_LINKS CurrentNode = (PVOID)((ULONG_PTR)UserData - sizeof(RTL_BALANCED_LINKS));
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ULONG_PTR StartingVpn = (ULONG_PTR)Buffer;
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if (StartingVpn < CurrentNode->StartingVpn)
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{
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return GenericLessThan;
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}
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else if (StartingVpn <= CurrentNode->EndingVpn)
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{
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return GenericEqual;
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}
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else
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{
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return GenericGreaterThan;
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}
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}
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VOID
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FORCEINLINE
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RtlSetParent(IN PRTL_BALANCED_LINKS Node,
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IN PRTL_BALANCED_LINKS Parent)
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{
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Node->u1.Parent = (PRTL_BALANCED_LINKS)((ULONG_PTR)Parent | (Node->u1.Balance & 0x3));
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}
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VOID
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FORCEINLINE
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RtlSetBalance(IN PRTL_BALANCED_LINKS Node,
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IN SCHAR Balance)
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{
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Node->u1.Balance = Balance;
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}
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SCHAR
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FORCEINLINE
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RtlBalance(IN PRTL_BALANCED_LINKS Node)
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{
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return (SCHAR)Node->u1.Balance;
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}
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PRTL_BALANCED_LINKS
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FORCEINLINE
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RtlParentAvl(IN PRTL_BALANCED_LINKS Node)
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{
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return (PRTL_BALANCED_LINKS)((ULONG_PTR)Node->u1.Parent & ~3);
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}
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BOOLEAN
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FORCEINLINE
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RtlIsRootAvl(IN PRTL_BALANCED_LINKS Node)
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{
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return (RtlParentAvl(Node) == Node);
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}
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PRTL_BALANCED_LINKS
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FORCEINLINE
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RtlRightChildAvl(IN PRTL_BALANCED_LINKS Node)
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{
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return Node->RightChild;
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}
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PRTL_BALANCED_LINKS
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FORCEINLINE
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RtlLeftChildAvl(IN PRTL_BALANCED_LINKS Node)
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{
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return Node->LeftChild;
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}
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BOOLEAN
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FORCEINLINE
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RtlIsLeftChildAvl(IN PRTL_BALANCED_LINKS Node)
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{
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return (RtlLeftChildAvl(RtlParentAvl(Node)) == Node);
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}
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BOOLEAN
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FORCEINLINE
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RtlIsRightChildAvl(IN PRTL_BALANCED_LINKS Node)
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{
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return (RtlRightChildAvl(RtlParentAvl(Node)) == Node);
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}
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VOID
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FORCEINLINE
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RtlInsertAsLeftChildAvl(IN PRTL_BALANCED_LINKS Parent,
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IN PRTL_BALANCED_LINKS Node)
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{
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Parent->LeftChild = Node;
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RtlSetParent(Node, Parent);
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}
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VOID
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FORCEINLINE
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RtlInsertAsRightChildAvl(IN PRTL_BALANCED_LINKS Parent,
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IN PRTL_BALANCED_LINKS Node)
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{
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Parent->RightChild = Node;
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RtlSetParent(Node, Parent);
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}
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/* EOF */
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